CN1268824A - P-bus channel selection device for switching device - Google Patents
P-bus channel selection device for switching device Download PDFInfo
- Publication number
- CN1268824A CN1268824A CN00104704A CN00104704A CN1268824A CN 1268824 A CN1268824 A CN 1268824A CN 00104704 A CN00104704 A CN 00104704A CN 00104704 A CN00104704 A CN 00104704A CN 1268824 A CN1268824 A CN 1268824A
- Authority
- CN
- China
- Prior art keywords
- bus
- register
- channel
- mentioned
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/18—Electrical details
- H04Q1/30—Signalling arrangements; Manipulation of signalling currents
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13299—Bus
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/167—Redundancy
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Bus Control (AREA)
Abstract
The invention relates to a P-bus channel selection device for automatically selecting a p-bus double-channel by a hardware. The device includes: a register FCR which can automatically change channel to correct the error outputed by the corresponding channel when the error is produced; a register ISR for monitoring the state of the P-bus and outputing the state of the corresponding signal; a controlling unit which can transport a controlling signal converted by P-bus channel to a controlling register ICR1 and checking the false controlling register ICR1 in a certain period when the error is produced; a controlling register ICR1 which can change a channel selection set value when the controlling signal converted by P-bus channel is inputed and select a p-bus double-channel data line.
Description
The dualization channel of P-bus that the present invention relates to the employing IPC communication modes of switch is selected, particularly the P-bus channel choice device of the switch that the dualization channel of P-bus is selected automatically with hardware.
The P-bus is two buses that dualization channel is arranged that are used for the IPC communication of switch, and it is made up of dual channel, and cross-over connection is between " circuit board 1 " and " circuit board 2 " of switch P-bus.Referring to Fig. 1 and Fig. 4, dualization of the P-bus channel selective mode with regard to existing switch describes below: Fig. 1 is the structure chart of dualization of P-bus of switch.Bus A and B are made of each six roots of sensation holding wire, wherein the selection of the corresponding signal lines of bus A and B is controlled by software respectively.When each holding wire is external, transferring again after with same dualization of signal on the transmission circuit plate, on circuit board for receiving, selecting a signal in the dualization signal.Being used for channel, to select employed register be the P-bus control register (hereinafter referred to as " ICR1 register ") of switch as shown in Figure 2 and the P-bus state register (hereinafter referred to as " ISR register ") of switch as shown in Figure 3.
In the structure of control register shown in Figure 2 (ICR1), bit 7～2nd, dualization bus (BUS) signal, the state of each bit is write above-mentioned control register (ICR1) by software and determines.At this bit is 1 o'clock, selects bus B, and is 0 o'clock at bit, then selects bus A.
The major function of status register shown in Figure 3 (ISR) as long as have at least the state of a bit to change in each bit, is just sent interrupt signal for the state of monitoring P-bus.For bit 0 BRCLKF, if occurring 1024 bytes or the transmission more than 1024 bytes on the bus, then it is high; For bit 1 FRSF,, then be high if do not sending the FRS signal more than 30 milliseconds; For bit 2 ASTCLKF,, then be high if high and low level conversion does not take place at the above ASTCLK of 2 microseconds; For bit 3 LASTF, at ASSERT (AST)
Under the state of remaining valid, if not conversion of BRCLK signal in 2 microseconds then is high; For bit 4 IALARMA,, then be high if P-bus A cable is unsettled; For bit 5 IALARMB,, then be high if P-bus B cable is unsettled.
With reference to above-mentioned status register (ISR), change the setting of above-mentioned control register (ICR1) in software (S/W) mode, make it to select suitable data wire.
Accompanying drawing 4 is that the P-bus channel of explanation existing switch is selected required flow process: if the one or more bits of above-mentioned status register (ISR) are converted to when high by low, just produce interrupt signal, each bit with above-mentioned control register (ICR1) in the software interrupt signal handler is converted to corresponding state, and corresponding data is written in the control register.Therefore usually, in the P-of existing switch bus channel selection mode, handle, according to the coding of hardware adjustment software in the mode that hardware and software interosculates.If problem takes place when transmission of control signals, cause and select control register (ICR1) improper, will cause losing of information.And, make a mistake continually, produce too much interrupt signal, can cause the decreased performance of system.Especially, if hardware makes a mistake, carry out error correction with software, because a plurality of interrupt signals produce simultaneously, must handle each interrupt signal by priority in central processing system (CPU), then the P-bus handling procedure of correcting a mistake will be waited for.Therefore, the handling procedure of executive software needs the long period, and also has the problem of information dropout in this process.
In order to address the above problem, the invention provides a kind of P-bus channel choice device of switch, wherein replace existing software processes program with hardware device, make selective channel rapider, thereby can avoid losing of information as far as possible.
According to the present invention, a kind of P-bus channel choice device of the switch that comprises dualization channel of the P-of use bus is provided, it comprises:
Error correction register (FCR), when mistake appearred in Channel Transmission, exportable corresponding information indicated this channel selector to change channel automatically;
Bus state register (ISR) is used to monitor the state of above-mentioned P-bus, occurs can producing interrupt signal when wrong in the P-bus, and the output corresponding signal;
Bus control register control unit (ICR1 register controlled unit) is used to check the output signal of above-mentioned error correction register, the output signal of bus state register and the feedback signal of bus control register; When mistake appears in the P-bus, P-bus channel changeover control signal is transported to above-mentioned control register (ICR1), and check above-mentioned mistake with some cycles;
P-bus control register (ICR1), it is controlled by above-mentioned P-bus control register control unit, its input signal is from described P-bus control register (ICR1) control unit, be used for when the P-bus channel switching signal of receiving from above-mentioned P-bus control register control unit, changing channel and select the value of setting, select the corresponding data line in the dualization channel of above-mentioned P-bus.
According to preferred embodiment of the present invention, described bus control register control unit comprises an input control part and an output control part, above-mentioned control register (ICR1) control unit input control part is checked the output signal of above-mentioned error correction register (FCR), the output signal of status register and from the feedback signal of bus control register (ICR1), the output signal that this bus control register control unit input control part produces is delivered to above-mentioned bus control register control unit output control part, above-mentioned bus control register (ICR1) control unit output control part output ICR1D and ICR1L0AD signal, select the value of setting with the channel that changes above-mentioned bus control register (ICR1), make it select the data wire of dualization of P-bus channel automatically.
The present invention is described in detail in conjunction with preferred embodiment of the present invention hereinafter with reference to accompanying drawing.
Fig. 1 is dualization of the P-bus structure chart of switch;
Fig. 2 is the structure chart of the P-bus control register (ICR1) of switch;
Fig. 3 is the structure chart of the P-bus state register (ISR) of switch;
Fig. 4 is the existing switch flow chart when selecting the P-bus channel;
Fig. 5 is according to improved control register of the present invention (ICR1) cut-away view;
Fig. 6 is the cut-away view according to control register of the present invention (ICR1) control unit;
Fig. 7 is the internal structure with VHDL language presentation graphs 6;
Fig. 8 is according to FCR register architecture figure of the present invention;
Fig. 9 is the required hardware structure diagram of selection P-bus channel according to switch of the present invention;
Figure 10 is according to embodiments of the invention, the sequential chart of the waveform of each holding wire among the Fig. 6 when making a mistake.
At first, be noted that in each accompanying drawing, adopt prosign to indicate to same parts, even these parts are illustrated in the different accompanying drawings.And, regard to the detailed description of related content of the present invention down, be intended to help to understand the present invention.Personnel as technical field of the present invention should understand, and even without the detailed description about these technology contents, also can implement the present invention.In addition, for clarity, omitted the detailed description of the function and the structure in non-field of the present invention.
For selecting P-bus channel provided by the invention, (ICR1) is transformed into as shown in Figure 5 with existing control register.Fig. 5 is the cut-away view of the improved control register (ICR1) according to the present invention, ICR1L0AD signal and ICR1D[31...24 that its input is exported from the control unit (200) of the control register among Fig. 6 (ICR1)] signal, its output is used to select above-mentioned P-bus channel.
About the structure of above-mentioned control register (ICR1) control unit (200), see shown in Figure 6, the information source that it is inner, as shown in Figure 7.Come the internal structure of presentation graphs 6 among Fig. 7 with VHDL language.Therefrom as can be seen, its input is from the output signal of error correction register FCR (Fault Change Register), the output signal of status register (ISR) and the feedback signal (referring to Fig. 9) of above-mentioned control register (ICR1).The ICR1L0AD signal and the ICR1D[31...24 of control register (300) control unit 200] signal transports to above-mentioned control register (ICR1) (300).Detailed description as for operation will be explained with reference to Fig. 9 below, is omitted at this.
Fig. 8 is the structure chart of error correction register FCR provided by the invention, when making a mistake, above-mentioned error register (FCR) can be set, with the communication channel of automatic change P-bus.Wherein, the error correction register enables minimum 4 effective bit 0-3 that FCREN (Fault Change Register Enable) position (bit 7) is used for allowing/forbidding this error register, if bit 7 is low, even mistake has taken place in remaining bit expression, also can not carry out channel and switch by hardware.
Describe each bit (3-0) of FCR below in detail.
LASTEEN bit (position 3) is high, and it confirms that the ASTF signal becomes height, then indicates to change channel by hardware.At this moment, height takes place just to become when undesired at the AST signal in above-mentioned ASTF signal.
ASTCLKFEN bit (position 2) is high, confirms that the ASTCLKF signal becomes height, then indicates to change channel by hardware.Above-mentioned ASTCLKF signal is at the ASTCLK signal height to take place just to become when undesired.
FRSFEN bit (position 1) is high, confirms that the FRSF signal becomes height, then indicates to change channel by hardware.Height takes place just to become when undesired at the FRS signal in above-mentioned FRSF signal.
BRCLKFEN bit (position 0) is high, confirms that the BRCLKF signal becomes height, then indicates to change channel by hardware.Above-mentioned BRCLKF signal is at the BRCLK signal height to take place just to become when undesired.
According to above-mentioned Fig. 5 and Fig. 8, the P-bus channel is selected required hardware in the switch provided by the invention, as shown in Figure 9.Figure 10 is the sequential chart of each the holding wire waveform of the Fig. 6 when mistake occurring according to an embodiment of the invention.The sequential chart of above-mentioned Figure 10 is to use MAXPLUS2 Version 8.2 simulations.
According to above-mentioned Fig. 5 and Figure 10, describe the P-bus channel choice device of switch provided by the invention below in detail.
For this embodiment is described, in Fig. 9, above-mentioned control register (ICR1) control unit (200) is divided into input control part (210) and control register (ICR1) output control part (220) represents, and above-mentioned control register (ICR1) control unit (200) integral body as shown in Figure 6.
The state of the above-mentioned P-bus of status register (ISR) (120) monitoring produces interrupt signal when the P-bus makes a mistake, corresponding signal is transported to above-mentioned control register (ICR1) control unit (200) input control part (210).Control register (ICR1) control unit (200) input control part (210) is checked output signal, the output signal of status register (ISR register, 120) and the feedback signal that is spread out of by control register (ICR1) (300) of above-mentioned error correction register FCR (110).For fear of making a mistake the state of control register (ICR1) control unit (200) regular check P-bus.The clock frequency of using during proof cycle is 16MHz, and native system adopts the clock of 32MHz, therefore can avoid delay, and in time changes the data of register, thereby makes it to select the P-bus channel.
Above-mentioned control register (ICR1) control unit (200) input control part (210) is checked the output signal of above-mentioned error correction register FCR (110), the output signal of status register (ISR register, 120) and the feedback signal of being exported by control register (ICR1) (300).If find mistake, just P-bus channel changeover control signal is transported to above-mentioned control register (ICR1) control unit (200) output control part (220), above-mentioned control register (ICR1) control unit (200) output control part (220) output ICR1D and ICR1LOAD signal, select the value of setting with the channel that changes above-mentioned control register (ICR1) (300), make it select the data wire of dualization of P-bus channel automatically.At this, above-mentioned ICR1D signal is the data wire of P-bus control register (ICR1), and above-mentioned ICR1LOAD signal is an ICR1 data LOAD signal, is transferred to when high by low, and CR1D latchs with data I.At this moment, as above-mentioned shown in Figure 10, can occur hardly incuring loss through delay.Above-mentioned Figure 10 supposes that error correction register FCR (110) is set to " FF ".As shown in figure 10, after making a mistake, postpone 1.846 microseconds (postponing 1 clock cycle) after, the numerical value of above-mentioned control register (ICR1) just changes, thereby has reduced delay.
In sum, the channel selector of switch provided by the invention when selecting the P-bus channel, replaces the software processes program with hardware handles, has both reduced overload, switching signal rapidly when making a mistake again, so reduced losing of information.
Above according to the present invention, embodiment is illustrated.But, for the person of ordinary skill of the art, can in the scope of spirit of the present invention, make amendment and not break away from inventive concept of the present invention it.Therefore protection scope of the present invention is not limited to the foregoing description, also not only comprises also comprising the content that is equal to claims by the back appended claims.
Claims (4)
1. P-bus channel choice device that uses the switch that comprises dualization channel of P-bus is characterized in that it comprises:
Error correction register (FCR), when mistake appearred in Channel Transmission, exportable corresponding information indicated this channel selector to change channel automatically;
Status register (ISR) is used to monitor the state of above-mentioned P-bus, occurs can producing interrupt signal when wrong in the P-bus, and the output corresponding signal;
Bus control register control unit (ICR1 register controlled unit) is used to check the output signal of above-mentioned error correction register, the output signal of status register and the feedback signal of bus control register; When mistake appears in the P-bus, P-bus channel changeover control signal is transported to above-mentioned control register (ICR1), and check above-mentioned mistake with some cycles;
Bus control register (ICR1), it is controlled by above-mentioned bus control register control unit, its input signal is from described P-bus control register (ICR1) control unit, be used for when the P-bus channel switching signal of receiving from above-mentioned bus control register control unit, changing channel and select the value of setting, select the corresponding data line in the dualization channel of above-mentioned P-bus.
2. the P-bus channel choice device of a kind of switch as claimed in claim 1 is characterized in that:
Described bus control register control unit comprises an input control part and an output control part, above-mentioned control register (ICR1) control unit input control part is checked the output signal of above-mentioned error correction register FCR, the output signal of status register and from the feedback signal of bus control register (ICR1), the output signal that this bus control register control unit input control part produces is delivered to above-mentioned bus control register control unit output control part, above-mentioned bus control register (ICR1) control unit output control part output ICR1D and ICR1LOAD signal, select the value of setting with the channel that changes above-mentioned bus control register (ICR1), make it select the data wire of dualization of P-bus channel automatically.
3. the P-bus channel choice device of a kind of switch as claimed in claim 1 or 2 is characterized in that:
Above-mentioned error correction register is made up of a plurality of signal bit position, when mistake appears in the indication of signal bit position, requires translated channel.
4. the P-bus channel choice device of a kind of switch as claimed in claim 1 or 2 is characterized in that:
The conversion of above-mentioned channel is to realize by the numerical value of revising in the bus control register corresponding to described rub-out signal bit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR9676/99 | 1999-03-22 | ||
| KR1019990009676A KR100318925B1 (en) | 1999-03-22 | 1999-03-22 | P-bus channel selector of exchange |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1268824A true CN1268824A (en) | 2000-10-04 |
| CN1268091C CN1268091C (en) | 2006-08-02 |
Family
ID=19577295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001047043A Expired - Fee Related CN1268091C (en) | 1999-03-22 | 2000-03-22 | P-bus channel selection device for switching device |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR100318925B1 (en) |
| CN (1) | CN1268091C (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970001623B1 (en) * | 1993-12-24 | 1997-02-11 | 양승택 | Abnormal condition processing method in the digital mobile packet router |
-
1999
- 1999-03-22 KR KR1019990009676A patent/KR100318925B1/en not_active IP Right Cessation
-
2000
- 2000-03-22 CN CNB001047043A patent/CN1268091C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR100318925B1 (en) | 2001-12-29 |
| CN1268091C (en) | 2006-08-02 |
| KR20000060973A (en) | 2000-10-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5732094A (en) | Method for automatic initiation of data transmission | |
| DE69128503T2 (en) | Interface circuit for intelligent network | |
| US20070143091A1 (en) | Microcomputer logic development system | |
| EP1199641B1 (en) | Data processing device used in serial communication system | |
| CN110875867B (en) | Bus access arbitration device and method | |
| CN1268091C (en) | P-bus channel selection device for switching device | |
| US5734821A (en) | Method and apparatus for a direct data transmission between a communication network interface and a multimedia data processor | |
| US6889270B2 (en) | Efficient reading of a remote first-in first-out buffer | |
| JPH09319401A (en) | Parallel duplex system electronic interlocking device | |
| CN1324859C (en) | Device and method of processing main spared inversion of synchronous system | |
| US20070230347A1 (en) | Communication interface device and communication method | |
| US7251248B2 (en) | Connection device | |
| US6892362B1 (en) | Hybrid state machine | |
| CN114649794A (en) | Fault protection soft turn-off control method for motor controller | |
| JPH02307124A (en) | Interruption control system | |
| JP2924232B2 (en) | Command check device | |
| US7085864B1 (en) | Method and structure for handling packetized SCSI protocol data overruns in a multi-data channel host adapter | |
| JP3452948B2 (en) | Data transmission method | |
| JPS63307565A (en) | Channel processor | |
| US20020075801A1 (en) | Method and apparatus for transmitting packets onto a network | |
| KR20000033278A (en) | Computer having digital signal processor local bus | |
| JPH03246659A (en) | Multi-cpu system | |
| JPH02277142A (en) | Duplex computer system | |
| JPS6358564A (en) | Interruption controlling system for bus converting device | |
| JPH02173804A (en) | Link interface module for programmable controller |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060802 |