CN1267979C - Method for producing multi-layer circuit thin integrated circuit - Google Patents
Method for producing multi-layer circuit thin integrated circuit Download PDFInfo
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- CN1267979C CN1267979C CN 03130996 CN03130996A CN1267979C CN 1267979 C CN1267979 C CN 1267979C CN 03130996 CN03130996 CN 03130996 CN 03130996 A CN03130996 A CN 03130996A CN 1267979 C CN1267979 C CN 1267979C
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- conducting wire
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- wire layer
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- integrated circuit
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Abstract
The present invention relates to a packaging method of a slim integrated circuit of a multi-layer circuit. Development etching of a surface of a substrate (copper plate) is carried out, then exposure development, electroplating, etc. are repeatedly carried out to form a first conducting wire layer, at least one layer of back-adhesive copper foil layer is pressed and combined with the conducting wire layer, the back-adhesive copper foil layer is utilized to form a second conducting wire layer, the second conducting wire layer is electrically connected with the first conducting wire layer, a multi-layer circuit is formed by the repeated superposition, crystal grains are connected with the conducting wire layers, and a layer of protective colloid is coated on the crystal grains by an adhesive-filling and packaging step; in addition, back etching of the bottom surface of the substrate is carried out, the conducting wires are exposed, the thickness of a final product can be effectively decreased, and the assembly volume can be reduced.
Description
Technical field
The invention relates to a kind of manufacture method of integrated circuit, refer to especially a kind ofly need not use printed circuit board (PCB), can in integrated circuit, form the manufacture method of multilayer line.
Background technology
Electronic product is to integrate multiple function to implement in order to satisfy at present mostly, its complex circuit designs degree often with the design the proportional growth of functional type, and on the other hand, the volume size of product etc. also is subjected to strict requirement restriction, so how under this certain restrictive condition, to meet aforementioned requirement, the research and development emphasis that must pursue for production firm.
General, for effective practice of reduction small product size is to set about from its intraware, after each volume, area of forming assembly dwindled, overall dimension met the requirements naturally.With regard to present integrated circuit (IC) design, say that just as aforementioned institute multi-functional design is to be inexorable trend, but adopt the assembly of single-layer wire line structure must satisfy this designing requirement, so the integrated circuit of multilayer line technology is satisfied development gradually.The method for making of aforementioned multilayer line, be to utilize the multilayer board storehouse to form, yet the product made from this kind technology, its thickness almost is the summation for printed circuit board (PCB) and packing colloid thickness, wherein only the thickness of aforementioned printed circuit board (PCB) promptly has to a certain degree, constitutes greatly for the volume that reduces encapsulating products, thickness etc. and hinders.
Summary of the invention
In view of this, main purpose of the present invention provides a kind of thin type integrated circuit manufacture method of multilayer line, to constitute the ultrathin electronic building brick that sealing thickness is only arranged, not only reduce production cost, and make component thickness significantly reduce and more benefit light and handyization of electronic building brick volume.
For reaching aforementioned purpose, the present invention comprises:
Form the first conducting wire layer in a substrate top surface with development etching and electroplating technology;
On this first conducting wire layer, on the gum copper foil layer, layer of conductive material is arranged in conjunction with at least one gum copper foil layer, on the subregion of electric conducting material, form the second conducting wire layer;
One is electrically connected technology, is to connect the aforementioned first conducting wire layer and the second conducting wire layer;
One adorns brilliant technology, according to the circuit design demand chip is electrically connected on aforementioned first conducting wire or the second layer conducting wire;
One encapsulating packaging technology forms protecting colloid and is encapsulated covering on aforementioned chip;
Wherein, aforesaid substrate is etching in addition from the bottom surface, makes the aforementioned first conducting wire layer be appeared.
Constituting the technology that is electrically connected of aforementioned each layer conducting wire, is to electroplate a conductive material layer with laser drill and in hole wall and finish;
The brilliant technology of aforementioned dress is to utilize the tin ball that chip directly is connected with the conducting wire, or connects with plain conductor.
Aforementioned ground floor conducting wire of exposing is connected because of constituting with chip, so can see through this conducting wire package assembling is connected on any circuit board, because of non-employing printed circuit board (PCB), reduces assembly volume in view of the above.
Description of drawings
Fig. 1: be substrate generalized section of the present invention.
Fig. 2: be the generalized section that the present invention forms first conductive layer.
Fig. 3: the generalized section that is pressing one resin copper foil layer of the present invention.
Fig. 4: be the generalized section that the present invention carries out laser drill.
Fig. 5: be the generalized section that the present invention forms conductive hole.
Fig. 6 and Fig. 7: be the generalized section that the present invention forms second conductive layer.
Fig. 8: be the generalized section that the present invention is provided with chip.
Fig. 9: the generalized section that is encapsulation of the present invention, etch substrate.
Figure 10: the generalized section that is integrated circuit finished product of the present invention.
Figure 11 and Figure 12: the generalized section that is another embodiment of the present invention.
Figure 13 and Figure 14: be the generalized section of the present invention's second conductive layer with the negative film operation.
In the accompanying drawing:
1--substrate 11--concave point
12--line of cut 13--photoresist layer
14,14 '--the first conducting wire layer
The 15--resin
16--Copper Foil 17--laser copper window photoresist layer
20--electric conducting material 21,21 '--photoresist layer
The 22--second conducting wire layer
30a, 30b--chip 31--plain conductor
32--tin ball 40--adhesive body
41--insulating barrier 42--tin paste layer
Embodiment
The present invention is the manufacture method for a kind of thin type integrated circuit of multilayer line, and its circuit number of plies can must be asked according to side circuit and be planned, in the explanation of following preferred embodiment, is to adopt the integrated circuit of double-deck circuit configurations to be illustrated.
See also shown in Figure 1, be formed with several line of cut 12 in a substrate 1 bottom surface, be at the bottom of the working lining of a smaller szie between the two adjacent lines of cut 12, the material of this substrate 1 can be yellow red metal plate, and the end face of substrate 1 is to process etching to form the slick and sly concave point 11 (Dimples) in a plurality of surfaces in advance again.
As shown in Figure 2, substrate 1 surface between two adjacent concave points 11, according to the line design demand, be coated with a photoresist layer 13 earlier, multiple this first conducting wire layer 14 is to possess anticorrosion properties in concave point 11 that does not cover photoresist layer 13 and part substrate 1 electroplating surface one first conducting wire layer 14, can be for the metal surface of gold thread or aluminum steel connection, also can be used as the thin metal layer that connects for the tin lead welding, as copper/nickel/copper/soft nickel/soft gold, soft nickel/soft gold, soft nickel/gold/PD etc.
See also shown in Figure 3, after the first conducting wire layer 14 forms, be again coated with an organic adhesion coating, this organic adhesion coating can be (the Resin Copper Coating of the gum copper foil layer shown in the present embodiment, RCC), utilize high temperature pressing mode to be formed on this substrate 1, this gum copper foil layer includes a resin bed 15 and a copper foil layer 16.
Please refer to shown in Figure 4ly, on aforementioned copper foil layer 16, is to shift a laser copper window photoresist layer 17 is arranged, and does not cover the part of laser copper window photoresist layer 17, promptly is to desire to implement the boring part with laser beam.
As shown in Figure 5, laser hole burning can remove the copper foil layer 16 and the resin bed 15 that appear, and drilling depth be to terminate in the first conducting wire layer 14 by its beam energy of control.After forming perforate, be to electroplate layer of conductive material 20 in the internal face of copper foil layer 16 surfaces and each perforate, make each perforate all become conductive hole.
See also shown in Figure 6, in aforementioned electric conducting material 20 surfaces is according to circuit design, cooperate photolithography plate to use and form a photoresist layer 21, present embodiment is to adopt the positive operation, and the electric conducting material 20 that promptly this photoresist layer 21 covered partly will be in addition etching of subsequent handling.Do not cover the part of photoresist layer 21, then be coated with one second conducting wire layer 22, this second conducting wire layer 22 will be formed at aforementioned conductive hole inside simultaneously.
As shown in Figure 7, after aforementioned photoresist layer 21 was removed, by the circuit that the second conducting wire layer 22 forms, promptly the circuit formation by aforementioned each conductive hole and the below first conducting wire layer, 14 formation was electrically connected, and so far the odt circuit structure is to form.
See also shown in Figure 8, after aforementioned photoresist layer 21 is removed, be to utilize the line of cut 12 on substrate 1 surface that full wafer substrate 1 is cut into multi-disc, with at the bottom of meeting the treatable small size working lining of encapsulation instrument institute, again with chip 30a, 30b is installed on the substrate 1, its chips 30a, the setting of 30b, in the present embodiment, be to place different places respectively, wherein the first chip 30a directly is adhered to the second conducting wire layer 22 with tin ball 32, after another chip 30b then adheres on the aforementioned resin layer 15 with elargol, adopt the routing mode, be connected in plain conductor 31 on the circuit of second conductive layer 22.
As shown in Figure 9, chip 30a, 30b carry out the encapsulating encapsulation process after being provided with and finishing again, form a tamper seal colloid 40 chip 30a, 30b are coated in it.
And aforesaid substrate 1 be from the bottom surface in addition etching remove, manifesting the first conducting wire layer 14 and resin bed 15, the Lower pit 11 that former substrate 1 end face forms, this moment, just generally speaking encapsulation was to be the protruding point, this protruding point promptly connects other circuit board for package assembling.
See also shown in Figure 10, be that reprocessing forms an insulating barrier 41 between resin bed 15 bottom surfaces and the two adjacent protrusion that the manifests first conducting wire layers 14, and the bottom surface of respectively protruding contact is to be coated with in advance to form a tin paste layer 42, because of each contact that protrudes is for being welded on other circuit board, can making contact be easier to be connected with circuit board by this tin paste layer 42.
See also shown in Figure 11ly, be another preferred embodiment of the present invention, wherein the end face of aforesaid substrate 1 is not form the described concave point 11 of first embodiment, and is a flat surfaces.See also shown in Figure 12, the advantage of this kind practice be when on the surface equally via the development etching, repeat to do technologies such as exposure imaging, plating and form the first conducting wire layer 14 ' after, in case substrate 1 is from the bottom surface etching, this first conducting wire layer 14 ' is to become a flat circuit, but same re-plating one tin paste layer 42 of the exposed surface of the first conducting wire layer 14 ', only the thickness of whole finished product can be thinner than first embodiment, more can effectively reduce finished-product volume.
Aforesaid embodiment adopts the positive operation, and promptly the electric conducting material 20 that covers of photoresist layer shown in the earlier figures 6 21 will be in addition etching of subsequent handling, the only also required requirement of attainable cost invention of negative film operation.Please refer to shown in Figure 13, on electric conducting material 20 surfaces is according to circuit design, cooperates photolithography plate to use and forms a photoresist layer 21 ', not by electric conducting material 20 that this photoresist layer 21 ' covered, to be removed (as shown in figure 14) via etching step, and make resin bed 15 be appeared.
After electric conducting material 20 etchings finish, its structure will become aforementioned shown in Figure 7.Earlier aforesaid photoresist layer 21 ' is removed, electroplated second conductive layer 22 more comprehensively, and aforementioned resin layer 15 is because of belonging to non-conductive material, so second conductive layer 22 will only can be attached to inner and not etched electric conducting material 20 surfaces of each conductive hole.
In sum, method for making of the present invention, because of the just etching removal fully after forming the conducting wire of substrate material, only keeping this conductive line is connected with other circuit board, to significantly reduce so integral body is made the thickness of product, moreover its recipe step is more succinct compared to commonly using mode, in meeting under the patent of invention important document prerequisite, file an application in whence mere formality in accordance with the law.
Claims (7)
1. the thin type integrated circuit manufacture method of a multilayer line is characterized in that, includes: form the first conducting wire layer in a substrate top surface with development etching and electroplating technology;
On this first conducting wire layer, on the gum copper foil layer, layer of conductive material is arranged in conjunction with at least one gum copper foil layer, on the subregion of electric conducting material, form the second conducting wire layer;
One is electrically connected technology, connects the aforementioned first conducting wire layer and the second conducting wire layer;
One chip connects technology, according to the circuit design demand chip is electrically connected on the aforementioned first conducting wire layer or the second conducting wire layer;
One encapsulating packaging technology is to cover with the protecting colloid encapsulation on aforementioned chip;
One first conducting wire layer exposes technology, and aforesaid substrate is etching and the aforementioned first conducting wire layer is exposed in addition from the bottom surface.
2. the thin type integrated circuit manufacture method of multilayer line as claimed in claim 1 is characterized in that, this development etching and electroplating technology are to comprise:
The etch substrate surface is to form a plurality of Lower pits;
Form layer of conductive material in each Lower pit, and the electric conducting material of each Lower pit is not interconnect to constitute the aforementioned first conducting wire layer, by this when aforementioned substrate after the etching of bottom surface, and Lower pit is directly to expose as conductive junction point, and constitutes a surface adhesive type integrated circuit package.
3. the thin type integrated circuit of multilayer line as claimed in claim 1 is adorned making method, it is characterized in that this development etching and electroplating technology are to comprise:
The etch substrate surface, and electroplate a conductive layer to form a plurality of flat film wires, this film wire is to be the aforementioned first conducting wire layer, can be for being connected with outside line.
4. the thin type integrated circuit manufacture method of multilayer line as claimed in claim 1 is characterized in that, the wherein aforementioned technology that is electrically connected is to electroplate a conductive material layer with laser drill and in hole wall and connect two adjacent conducting wire layers.
5. as the thin type integrated circuit manufacture method of claim 1,2,3 or 4 described multilayer lines, it is characterized in that aforementioned chip is connected to the first conducting wire layer or the second conducting wire layer on the substrate with plain conductor.
6. as the thin type integrated circuit manufacture method of claim 1,2,3 or 4 described multilayer lines, it is characterized in that aforementioned chip is connected to the first conducting wire layer or the second conducting wire layer on the substrate with the tin ball.
7. as the thin type integrated circuit manufacture method of claim 1,2,3 or 4 described multilayer lines, it is characterized in that the aforementioned first conducting wire layer re-plating that exposes has a tin paste layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03130996 CN1267979C (en) | 2003-05-12 | 2003-05-12 | Method for producing multi-layer circuit thin integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03130996 CN1267979C (en) | 2003-05-12 | 2003-05-12 | Method for producing multi-layer circuit thin integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1549320A CN1549320A (en) | 2004-11-24 |
| CN1267979C true CN1267979C (en) | 2006-08-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03130996 Expired - Fee Related CN1267979C (en) | 2003-05-12 | 2003-05-12 | Method for producing multi-layer circuit thin integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1267979C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100359699C (en) * | 2004-12-30 | 2008-01-02 | 南亚电路板股份有限公司 | Method for fabricating image sensor in CMOS |
| US9831023B2 (en) * | 2014-07-10 | 2017-11-28 | Cyntec Co., Ltd. | Electrode structure and the corresponding electrical component using the same and the fabrication method thereof |
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2003
- 2003-05-12 CN CN 03130996 patent/CN1267979C/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| CN1549320A (en) | 2004-11-24 |
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Granted publication date: 20060802 Termination date: 20140512 |