CN1267136A - Logic circuit and carry lookahead circuit - Google Patents

Abstract

The logic circuit is provided for searching a binary bit string from the most significant bit to the least significant bit for a first ''0'' or ''1'' bit and comprises a NOT gate circuit receiving the most significant bit of said binary bit string and composed of a dynamic logic circuit; NOR gate circuits provided in a one-to-one correspondence to the respective bits of said binary bit string, each NOR gate circuit receiving the bit of said binary bit string corresponding to the bit position of said each NOR gate circuit and, if any, the bit(s) of said binary bit string which is more significant than the bit corresponding to the bit position of said each NOR gate circuit except for the most significant bit; and two-input NOR gate circuits each of which receives two logic signals as output from adjacent ones of said NOT and NOR gate circuits. Logic circuits and carry-lookahead circuits capable of performing high speed operations with simplified designs.

Description

Logical circuit and carry lookahead circuit

The application is based on the patent application of the content of putting down in writing on March 9th, 1999 in the application number that Japan proposes is 62346 patent application, propose priority claim according to Paris Convention, simultaneously with the part of its content as the application.

The application is based on the patent application of the content of putting down in writing on June 30th, 1999 again in the application number that Japan proposes is 186956 patent application, propose priority claim according to Paris Convention, simultaneously with the part of its content as the application.

The present invention relates to logical circuit, particularly relate in the serial data of many bits initial 0 or 1 the logical circuit that occurs of retrieval.

In addition, the present invention relates to constitute the necessary carry lookahead of arithmetic unit (CLA) circuit of many bit long.

In a kind of logical circuit of the hardware that constitutes computer, the circuit that is referred to as 0 search circuit or 1 search circuit is arranged.Sort circuit is initial 0 or 1 the circuit that occurs of retrieval when upper bit begins to check in order the bit of serial data of 2 system numbers, and generates the basic circuit of pricority encoder and so on of the output code of the high line of input of representing the override ranking when being used as the comparison circuit of comparing data string size for example or being input to the above line of input of two row to 0 or 1.

, because a plurality of gates are connected to rectangular or dendritic structure in 0 or 1 original search circuit, so circuit constitutes complexity.And, to spend a lot of times so handle by a plurality of routes from being input between the output.

In addition, the input signal A of input N bit long (a＜N-1 〉, a＜N-2 〉) ..., a＜0, following table is shown a＜N-1:0 〉) and input signal B (b＜N-1 〉, b＜N-2 〉) ..., b＜0, following table is shown b＜N-1:0 〉) and carry out using in the adder of add operation the CLA circuit.The disclosed circuit of Japanese publication JP-3-150630 is arranged in original C LA circuit.This CLA circuit carries out the computing that carry signal is input as the situation of " 0 " and is input as the situation of " 1 " side by side, and selects output either party operation result according to the next carry signal value, usually sort circuit is referred to as carry lookahead circuit.

In the document, show circuit shown in Figure 2 as 4 original bit CLA circuit.When the every bit to input signal A (a＜3:0 〉) and input signal B (b＜3:0 〉) carries out add operation, obtain respectively and transmit signal P＜3:0〉and (a＜3:0〉with b＜3:0 the exclusive OR computing of every bit), generate signal G＜3:0 (a＜3:0〉with b＜3:0 every bit and computing).And signal P＜3:0 〉, signal G＜3:0 and be input to the CLA circuit, output carry signal C＜3:0 then from the carry CIN of prime.

Expression has the formation of the CLA circuit of the formation of exporting according to a side operation result selection among Fig. 3, this formation is provided with carry signal C＜3:0 that computing is 1 situation from the carry Cin of prime〉CLA1 and computing carry Cin carry signal C＜3:0 of being 0 situation CLA2, select the output any one party as carry signal C＜3:0 according to the value of carry Cin 〉.

The CLA circuit arrangement that 4 bits shown in Figure 2 are constituted becomes the group 0 of the 1st～4 bit, and CLA circuit arrangement shown in Figure 3 is become the group 1～7 of the 5th～32 bit, and the CLA circuit that constitutes 32 bits thus is with regard to as shown in Figure 1.From organize 0 begin to the group 1,2 ... generate carry signal C＜0 in order 〉～C＜3, C＜4～C＜7, C＜8～C＜11 ..., and level transmits backward, last output carry signal C＜28 〉～C＜31 〉.

But, in above-mentioned existing C LA circuit, have following problem.From carry signal C＜0 that generates the 1st bit〉to carry signal C＜31 that generate the 32nd bit〉the desired computing relay time is as shown in Figure 4.Being located at from organizing the 0 circuit CLA1 to group 7 in the CLA circuit respectively is the same with the desired time T 1 of the computing of circuit CLA2.But, from organizing carry signal C＜3 of 0 output〉and be fed to group 1 CLA circuit, then according to carry signal C＜3〉select to produce T2 time of delay among the multiplexer MUX of output.Because should time of delay T2 along with from organizing 1 to group 7 accumulations and generate, so, produce T1+T2*7 time of delay at last.Therefore, originally existing problem is to increase with bit number, and the desired time of carry computing just increases.

For solving above-mentioned original problem, the purpose of this invention is to provide the logical circuit that a kind of circuit constitutes simply and can carry out high speed processing.

Other purposes of the present invention provide a kind of logical circuit, and this logical circuit can shorten that to deliver in the group that is made of the m bit and obtain with the group be signal PG, the GG of unit, the computing relay time of KG to signal P, G, the K of every m bit.

For realizing above-mentioned purpose, according to logical circuit of the present invention is initial 0 or 1 the logical circuit that occurs of retrieval when upper bit begins to check in order the bit of serial data of 2 system numbers, and this logical circuit is made of NOT logic, NOR circuit, 2 input NOR circuit; NOT logic is made of dynamic circuit, and accepts the upper bit of the serial data of described 2 system numbers; NOR circuit is made of dynamic circuit, and is corresponding one by one with bit beyond the upper bit of the serial data of described 2 system numbers, imports corresponding to the bit of the serial data of the described 2 system numbers of this bit position and the bit more upper than this bit position; 2 input NOR circuit are accepted two logical signals from the circuit of described NOT logic and NOR circuit adjacency.

According to the preferred embodiment, described NOT logic and NOR circuit are made of the NMOS FET between the output line that is connected in parallel on earthing potential and described NOT logic and NOR circuit.

In addition, according to the preferred embodiment, in the prime of described 2 input NOR circuit, be inserted with phase inverter.

Logical circuit according to other embodiment of the present invention is made of timing circuit, standard-nmos circuit and logic gates; Timing circuit is made of first combinational circuit that is connected between output line and the earthing potential, between precharge phase, control described first combinational circuit, when described earthing potential is cut off described output line, power supply is supplied with described output line, make described output line bring up to " H " level, during output is determined, when the input signal that should estimate is delivered to described first combinational circuit, stop the power supply of described output line is supplied with, selectively described earthing potential and described output line are coupled together according to this logical operation value, export determined logical value through described output line; Standard-nmos circuit is made of second combinational circuit that is connected between output line and the earthing potential, between described precharge phase, control described second combinational circuit, described earthing potential is connected to described output line, make described output line be reduced to " L " level, during described output is determined, when the input signal that should estimate is delivered to described first combinational circuit, power supply is supplied with described output line, selectively described earthing potential is cut off described output line according to this logical operation value, export determined logical value through described output line; Logic gates is connected to described timing circuit, and according to the signal of the described output line of described timing circuit, control is supplied with the power supply of the described output line of described standard-nmos circuit.Described timing circuit is the same or complementary with the logical value that described standard-nmos circuit is determined, during described output is determined, the described output line of described standard-nmos circuit is connected to earthing potential, under the situation that is reduced to " L " level, respond to the variation of the described output line of standard-nmos circuit correspondence, described logic gates stops the power supply of the described output line of described timing circuit is supplied with.

In addition, according to the preferred embodiment, described first combinational circuit and described second combinational circuit are made of the NMOS FET with same logical constitution.

Standard-NMOS logical circuit according to other embodiment of the present invention is made of second standard-nmos circuit, first standard-nmos circuit, first logic gates, second logic gates; Second standard-nmos circuit is made of second combinational circuit that is connected between output line and the earthing potential, between described precharge phase, control described second combinational circuit, described earthing potential is connected to described output line, make described output line be reduced to " L " level, during described output is determined, when the input signal that should estimate is delivered to described first combinational circuit, power supply is supplied with described output line, selectively described earthing potential is cut off described output line according to this logical operation value, export determined logical value through described output line; First standard-nmos circuit is made of first combinational circuit that is connected between output line and the earthing potential, between precharge phase, control described first combinational circuit, described earthing potential is connected to described output line, make described output line be reduced to " L " level, during output is determined, when the input signal that should estimate is delivered to described first combinational circuit, power supply is supplied with described output line, selectively described earthing potential is cut off described output line according to this logical operation value, export determined logical value through described output line; First logic gates basis is supplied with the power supply of the described output line of described first standard-nmos circuit from the signal controlling of the described output line of described second standard-nmos circuit; Second logic gates basis is supplied with the power supply of the described output line of described second standard-nmos circuit from the signal controlling of the described output line of described first standard-nmos circuit.Described first standard-nmos circuit and described second standard-nmos circuit are complementary, during described output is determined, described earthing potential be connected to described first standard-nmos circuit and described second standard-nmos circuit a side described output line and pull down under the situation of " L " level, according to the variation of " H " level of the opposing party's described output line, first or second logic gates stops the power supply of the opposing party's of described standard-nmos circuit described output line is supplied with.

According to the input of the carry lookahead circuit of additional embodiments of the present invention every the transmitting signal P of m (m is the integer 1 or more) bit, produce at least one side among signal G and the erasure signal K, group transmitting signal PG, the group that generates the corresponding group of conduct that is made of the m bit produces signal GG and organizes at least one side among the erasure signal KG; Described carry lookahead circuit is made of logical circuit, priority encoder and selection circuit, all have under the situation of a logical value at described transmitting signal P or all have at counter-rotating group transmitting signal PB under the situation of reverse value of a logical value, the logical circuit output device has described group of transmitting signal PG of a described logical value and/or has the described counter-rotating group transmitting signal PGB of the reverse value of a described logical value; According to from the upper bit to described transmitting signal P of the next ordered retrieval and/or described counter-rotating group transmitting signal PB, and generate the selection signal of effective m bit corresponding to the bit of the signal of the reverse value of the described logical value of initial appearance among the described transmitting signal P or the described logical value of initial appearance among the described counter-rotating group transmitting signal PB, and do not occur in any bit of described transmitting signal P under the situation of reverse value of a described logical value, do not occur under the situation of a described logical value in any bit of perhaps described counter-rotating group transmitting signal PB, priority encoder is exported any bit does not become the effective choice signal; Import described selection signal, and when significant bit is input to described selection signal, selector is selected among described generation signal G and/or the described erasure signal K generation signal G and/or the erasure signal K corresponding to the significant bit of described selection signal, and go as described group of generation signal GG and/or described group of erasure signal KG output respectively, any bit at described selection signal does not become under the effective situation, and the selector output device has described group of generation signal GG and/or described group of erasure signal KG of the reverse value of a described logical value.

According to the carry lookahead circuit input carry signal C of additional embodiments of the present invention, every the transmitting signal P of m (m is the integer more than 1) bit, produce at least one side among signal G and the erasure signal K, group transmitting signal PG, group carry signal CG, the group that generates the corresponding group of conduct that is made of the m bit produces at least one side among signal GG and the group erasure signal KG; Described carry lookahead circuit is made of logical circuit, priority encoder and selection circuit, all have under the situation of a logical value at described transmitting signal P or all have at counter-rotating group transmitting signal PB under the situation of reverse value of a logical value, the logical circuit output device has described group of transmitting signal PG of a described logical value and/or has the described counter-rotating group transmitting signal PGB of the reverse value of a described logical value; According to from upper to described transmitting signal P of the next ordered retrieval and/or described counter-rotating group transmitting signal PB, and generate the selection signal of effective m bit corresponding to the bit of the signal of the reverse value of the described logical value of initial appearance among the described transmitting signal P or the described logical value of initial appearance among the described counter-rotating group transmitting signal PB, and do not occur in any bit of described transmitting signal P under the situation of reverse value of a described logical value, do not occur under the situation of a described logical value in any bit of perhaps described counter-rotating group transmitting signal PB, priority encoder is exported any bit does not become the effective choice signal; Import described selection signal, and when significant bit is input to described selection signal, selector is selected among described generation signal G and the described erasure signal K generation signal G and the erasure signal K corresponding to the significant bit of described selection signal, and go as described group carry signal CG and counter-rotating group carry signal CGB output respectively, any bit at described selection signal does not become under the effective situation, and selector is exported described carry signal C according to described group of transmitting signal PG or counter-rotating group transmitting signal PGB as described group carry signal CG.

Carry lookahead circuit according to additional embodiments of the present invention is made of a plurality of first carry lookahead circuit groups, a plurality of second carry lookahead circuit group and the 3rd carry lookahead circuit; The first carry lookahead circuit group is made of a plurality of first carry lookahead circuits; The second carry lookahead circuit group is made of a plurality of second carry lookahead circuits, and each second carry lookahead circuit is connected to described first carry lookahead circuit of each group that belongs to the described first carry lookahead circuit group; The 3rd carry lookahead circuit is connected on the described second carry lookahead circuit group; The input of described first carry lookahead circuit every the transmitting signal of m (m is the integer 1 or more) bit, produce at least one side in signal and the erasure signal, generate at least one side in first group of transmitting signal of the corresponding group of conduct that constitutes by the m bit, first group of generation signal and the first group of erasure signal; Described first carry lookahead circuit is made of logical circuit, priority encoder and selection circuit, all have under the situation of a logical value at described transmitting signal or all have at counter-rotating group transmitting signal under the situation of reverse value of a logical value, the logical circuit output device has described first group of transmitting signal of a described logical value and/or has the described first counter-rotating group transmitting signal of the reverse value of a described logical value; According to from the upper bit to described transmitting signal of the next ordered retrieval and/or described counter-rotating group transmitting signal, and generate the selection signal of effective m bit corresponding to the bit of the signal of the reverse value of the described logical value of initial appearance among the described transmitting signal or the described logical value of initial appearance among the described counter-rotating group transmitting signal, and do not occur in any bit of described transmitting signal under the situation of reverse value of a described logical value, do not occur in any bit of perhaps described counter-rotating group transmitting signal under the situation of a described logical value, priority encoder is exported any bit does not become the effective choice signal; Import described selection signal, and when significant bit is input to described selection signal, selector is selected among described generation signal and/or the described erasure signal generation signal and/or the erasure signal corresponding to the significant bit of described selection signal, and go as described first group of generation signal and described first group of erasure signal output respectively, any bit at described selection signal does not become under the effective situation, and the selector output device has described first group of generation signal and/or described first group of erasure signal of the reverse value of a described logical value.

Described second carry lookahead circuit is imported described first group of transmitting signal, described first group of at least one side who produces in signal and the described first group of erasure signal, and the second group of transmitting signal, second group that generates the first corresponding carry lookahead circuit group produces at least one side in signal and the second group of erasure signal; Described second carry lookahead circuit is made of logical circuit, priority encoder and selection circuit, all have under the situation of a logical value at described first group of transmitting signal or all have at the described first counter-rotating group transmitting signal under the situation of reverse value of a logical value, the logical circuit output device has described second group of transmitting signal of a described logical value and/or has the described second counter-rotating group transmitting signal of the reverse value of a described logical value; According to from the upper bit to described first group of transmitting signal of the next ordered retrieval and/or the described first counter-rotating group transmitting signal, and generate the selection signal of effective many bits corresponding to the bit of the signal of the reverse value of the described logical value of initial appearance among described first group of transmitting signal or the described logical value of initial appearance among the described first counter-rotating group transmitting signal, and do not occur in any bit of described first group of transmitting signal under the situation of reverse value of a described logical value, do not occur in any bit of the perhaps described first counter-rotating group transmitting signal under the situation of a described logical value, priority encoder is exported any bit does not become the effective choice signal; Import described selection signal, and when significant bit is input to described selection signal, selector selects described first group of first group of producing among signal and/or the described first group of erasure signal corresponding to the significant bit of described selection signal to produce signal and/or first group of erasure signal, and go as described second group of generation signal and/or described second group of erasure signal output respectively, any bit at described selection signal does not become under the effective situation, and the selector output device has described second group of generation signal and/or described second group of erasure signal of the reverse value of a described logical value.

Described the 3rd carry lookahead circuit input carry signal, described second group of transmitting signal, described second group of at least one side who produces in signal and the described second group of erasure signal, the 3rd group of transmitting signal, group carry signal, the 3rd group that generates the second corresponding carry lookahead circuit group produces at least one side in signal and the 3rd group of erasure signal; Described the 3rd carry lookahead circuit is made of logical circuit, priority encoder and selection circuit, all have under the situation of a logical value at described second group of transmitting signal or all have at the described second counter-rotating group transmitting signal under the situation of reverse value of a logical value, the logical circuit output device has described the 3rd group of transmitting signal of a described logical value and/or has second group of transmitting signal of the described second counter-rotating group of the reverse value of a described logical value; According to from the upper bit to described second group of transmitting signal of the next ordered retrieval and/or the described second counter-rotating group transmitting signal, and generate the selection signal of effective many bits corresponding to the bit of the signal of the reverse value of the described logical value of initial appearance among described second group of transmitting signal or the described logical value of initial appearance among the described second counter-rotating group transmitting signal, and do not occur in any bit of described second group of transmitting signal under the situation of reverse value of a described logical value, do not occur in any bit of the perhaps described second counter-rotating group transmitting signal under the situation of a described logical value, priority encoder is exported any bit does not become the effective choice signal; Import described selection signal, and when significant bit is input to described selection signal, selector selects described second group of second group of producing among signal and the described second group of erasure signal corresponding to the significant bit of described selection signal to produce signal and second group of erasure signal, and go as described group carry signal and the output of described counter-rotating group carry signal respectively, any bit at described selection signal does not become under the effective situation, selector utilizes described the 3rd group to produce signal and described the 3rd group of erasure signal, and described carry signal is gone as described group carry signal output.

Fig. 1 is the forming circuit figure of existing 32 bit CLA circuit.

Fig. 2 is the forming circuit figure of the CLA circuit of the group 0 in this CLA circuit.

Fig. 3 has the pie graph of CLA circuit of formation of selecting output one side's operation result according to carry value.

Fig. 4 is carry signal C＜0 from generating the 1st bit in this CLA circuit of expression〉to carry signal C＜31 of generation the 32nd bit〉key diagram of needed computing relay time.

Fig. 5 is the circuit diagram under the situation of the priority encoder that is applicable to 4 bits according to logical circuit of the present invention.

Fig. 6 constitutes circuit diagram under the situation of inverter circuit, NOR circuit of 1 search circuit shown in Figure 5 by timing circuit.

Fig. 7 is the circuit diagram that has appended in the timing circuit of Fig. 6 under the situation of NMOSFET.

Fig. 8 is the circuit diagram that has appended in the timing circuit of Fig. 7 under the situation of static circuit.

Fig. 9 removes the clock control function from timing circuit shown in Figure 75, be used for making logic to carry out circuit diagram under the situation of circuit of static action and appended.

Figure 10 is by the circuit diagram under the situation of 1 search circuit of NAND circuit pie graph 5.

Figure 11 is 1 search circuit that connects a plurality of Fig. 5, further constitutes the circuit diagram under the situation of many bit priorities encoder.

Figure 12 is to use the priority encoder of Fig. 5 to constitute circuit diagram under the situation of employed CLA circuit in the adder.

Figure 13 (a) is a circuit diagram of representing an example of circuit formation in this first and second CLA circuit and circuit AN1.Figure 13 (b) is the key diagram of standard-nmos type.

Figure 14 constitutes circuit diagram under the situation of NOR circuit NR11, NR21, NR31 of priority encoder PE of the 2nd CLA circuit CLA (2) of the CLA circuit CLA (1) of Figure 12 and Figure 17 by timing circuit.

Figure 15 constitutes circuit diagram under the situation of selector SEL1 by PMOSFET, NMOSFET and inverter circuit.

Figure 16 is the sequential chart of timing of the input and output of expression CLA circuit shown in Figure 12.

Figure 17 is connected to circuit diagram under the situation on the circuit of Figure 12 with circuit.

Figure 18 is the sequential chart of timing of the input and output of expression CLA circuit shown in Figure 17.

Figure 19 is to use the 2nd CLA circuit CLA (2) of the CLA circuit CLA (1) of Figure 12 and Figure 17 to constitute circuit diagram under the situation of CLA circuit of 32 bits.

Figure 20 is the key diagram of the computing relay time in the expression CLA circuit shown in Figure 19.

Two signal A of Figure 21 (a) expression input and B (/A and/B), and between A and B, carry out disjunction operation and generate the circuit of output signal P.

Figure 21 (b) expression counter-rotating be added to logic and on signal PB output to circuit between two input signal A and the B.

The circuit of the waveform CB of the carry signal Cin of every bit that Figure 22 (a) expression generation and clock CLK are synchronous.

The circuit of the waveform CB of the counter-rotating carry signal/Cin of every bit that Figure 22 (b) expression generation and clock CLK are synchronous.

Figure 23 is connected to circuit diagram under the situation of standard shown in Figure 17-NMOS NAND circuit 42 to 1 search circuit 2-7, and the part mark identical with Figure 17 is with prosign.

Figure 24 represents standard-NMOS NAND circuit 42, is connected on the dynamic circuit 46 by identical logical constitution.

Figure 26 is the circuit diagram of the configuration example of the synchronous dynamic circuit of expression output and standard-nmos circuit combination.

Figure 27 is the sequential chart of timing of the input and output of expression standard-NMOS NAND circuit 61 shown in Figure 26.

Figure 28 is the circuit diagram of expression according to the configuration example of the logical circuit of complementary standard of the present invention-NMOS NAND circuit formation.

Figure 29 is the sequential chart of timing of the input and output of expression complementary standard-NMOS NAND circuit shown in Figure 28.

Figure 30 is the circuit diagram according to the configuration example of complementary logic circuit of the present invention of representing to use standard-NMOS NAND circuit as the application examples of circuit shown in Figure 28.

Figure 31 is the sequential chart of timing of the input and output of expression complementary standard-NMOS NAND circuit shown in Figure 30.

Embodiments of the invention below are described with reference to the accompanying drawings.

Fig. 5 is the circuit diagram under the situation that is applicable to 4 bit priority encoders according to logical circuit of the present invention.Fig. 1 is the forming circuit figure of the CLA circuit of existing 32 bits.

This priority encoder 1 be generate 4 bits input data (IN＜0 〉, IN＜1, IN＜2, IN＜3) among corresponding to the circuit of 2 bit output codes of the high line of input of override ranking, it constitutes by 1 search circuit 2 with to the encoder 3 that the output of this 1 search circuit 2 is encoded.Here, bidding draws the preferential ranking height of little line of input.

The formation of 1 search circuit 2 is described below.Because encoder 3 is made of existing encoder circuit, omitted explanation.

1 search circuit 2 is by high IN＜0 of preferential ranking 〉, IN＜1 ... sequential search input data I N＜0 〉, IN＜1, IN＜2, IN＜3 each bit value, IN＜i〉occur at 1 o'clock at first in (0≤i≤3), dateout S＜0 〉, S＜1, S＜2, S＜3 in only export to S＜i to 1 (0≤i≤3), the 0 S＜j that exports to other〉(j ≠ i), export to Y to 1.At IN＜i〉(0≤i≤3) all be 0 o'clock, exports to whole S＜i to 1〉(0≤i≤3), export to Y to 0.

1 search circuit 2 shown in Figure 5 is provided with input input data I N＜0〉logical not component 11, input IN＜1, IN＜02 input NOR circuit 12, input IN＜2, IN＜0 and IN＜13 input NOR circuit 13, input IN＜3, IN＜0, IN＜1 and IN＜24 import NOR circuit 14.

The output of logical not component 11, NOR circuit 12～14 further by logical not component 19～22 counter-rotatings, is imported into the incoming line A0～A3 of 2 input NOR circuit 23～26 by 15～18 counter-rotatings of subsequent logical not component then.Simultaneously, bit signal " 0 " is input to the incoming line B0 of NOR circuit 23, the reverse signal of logical not component 15 is input to the incoming line B1 of NOR circuit 24, the reverse signal of logical not component 16 is input to the incoming line B2 of NOR circuit 25, the reverse signal of logical not component 17 is input to the incoming line B3 of NOR circuit 26.The operation result of NOR circuit 23～26 is removed and is used as dateout S＜0 〉, S＜1, S＜2, S＜3; Signal by logical not component 18 counter-rotatings is taken out as dateout Y.

In above-mentioned such 1 search circuit 2 that constitutes, for example observe the input data I N＜3:0 of input bit row " 0101 "〉situation the time, in logical not component 11, NOR circuit 12～14, bit column just becomes " 1000 ", and the bit column in the subsequent logical not component 15～18 just becomes " 0111 ".In the computing hereto, in order the bit inspection of input data is gone down, detect the position that bit column becomes " 0,1 ", and bit value after this all is made as 1 from upper beginning.Therefore, at IN＜3:0 〉=when " 0101 ", IN＜2〉later bit, no matter its value size all becomes 1 (" 0111 ").Then, through logical not component 19～22, NOR circuit 23～25 dateout S＜3:0 bit column be output as " 0100 ".

Equally, during the input data (X can be 0, also can be 1) of input bit row " 1XXX ", " 001X ", " 0001 ", export " 1000 ", " 0010 ", " 0001 " respectively.At input data I N＜3:0〉in comprise under the situation of at least one " 1 ", output 1 is as dateout Y.

On the other hand, at the input data I N＜3:0 of input bit row " 0000 "〉situation under, in logical not component 11, NOR circuit 12～14, bit column becomes " 1111 ", the bit column in the subsequent logical not component 15～18 becomes " 0000 ".Here, because do not import the combination that the bit column of data becomes " 0,1 ", so through the dateout S＜3:0 of logical not component 19～22, NOR circuit 23～25〉bit column become " 0000 ".At input data I N＜3:0〉in do not comprise under the situation of " 1 ", output 0 is as dateout Y.

Next dateout S＜3:0〉be input to encoder 3, generate 2 bit output code Q0, the Q1 of the high incoming line of expression override ranking.By the way, if dateout S＜3:0〉be " 1000 ", just " 00 " of incoming line 0 is represented in output; If " 0100 ", just " 01 " of output expression incoming line 1; If " 0010 ", just " 10 " of output expression incoming line 2; If " 0001 ", just " 11 " of output expression incoming line 3.At dateout Y is 0 o'clock, dateout S＜3:0〉be identified as " 0000 ".

Like this, in pressing 1 search circuit of present embodiment, like that gate is connected to circuit rectangular or that dendroid constitutes and compares with original, circuit constitutes simple.And, because few, handle the needed time so can shorten from being input to the route of seeking between the output.Therefore, can enough simple circuit constitute and realize the logical circuit that to handle at a high speed.

In the present embodiment, 1 search circuit has been described, still, also can have constituted 0 search circuit according to logical circuit of the present invention.

Below, the concrete circuit formation according to 1 search circuit of present embodiment is described.

Fig. 6 is with the circuit diagram under the situation of the logical not component 11 of timing circuit formation 1 search circuit 2 shown in Figure 5, NOR circuit 12～14.Among Fig. 6, PC0～PC3 represents the PMOSFET of subject clock signal (CLK) control respectively, and N00～N33 represents NMOSFET respectively.When observing corresponding to Fig. 5, N00 is corresponding to logical not component 11, and N10, N11 are corresponding to 2 input NOR circuit 12, and N20～N22 is corresponding to 3 input NOR circuit 13, and N30～N33 is corresponding to 4 input NOR circuit 14.

Fig. 7 is the circuit diagram that has appended in the timing circuit 4 of Fig. 6 under the situation of the NMOSFET that starts with clock signal controlling timing circuit.Constitute like that at image pattern 7 under the situation of timing circuit 5,, can prevent from when clock signal precharge, to flow to the perforation electric current in the circuit though responsiveness is a little slower a little than the example of Fig. 6.

Fig. 8 has further appended to be used for making logic to carry out circuit diagram under the situation of static circuit of static action in timing circuit shown in Figure 75.In general timing circuit, be difficult to keep the H level, but constitute like that under the situation of timing circuit 6, because logic is decided to be static state, so can make the action of circuit stable at image pattern 8 by precharge.And, can make the processing speed of Fig. 8 circuit identical substantially with the processing speed of the circuit of Fig. 6.

Fig. 9 removes the clock control function from timing circuit shown in Figure 75, be used for making logic to carry out circuit diagram under the situation of circuit of static action and appended.Constitute like that at image pattern 9 under the situation of timing circuit 7, in case because precharge makes circuit become enable state, and logic just is decided to be static state, so can make the action of circuit stable.And, can make the processing speed of circuit identical substantially with the processing speed of the circuit of Fig. 6.

In Fig. 5, represented to constitute the example of the logical circuit of 1 search circuit 2 by NOR circuit and logical not component, also for example image pattern 10 is made of NAND circuit like that.

Figure 11 couples together circuit diagram under the situation of priority encoder of the many bits of further formation to 1 search circuit of a plurality of Fig. 5.This priority encoder 31 is made of 1 search circuit 32, encoder 33a and 33b that the output of this 1 search circuit 32 is encoded.

The formation of 1 search circuit 32 shown in Figure 11 is described below.

1 search circuit 32 is by 1 search circuit 2-5 of 1 search circuit 2-1～2-4 of 4 bits, same 4 bits, constitute with logical circuit 34～37, multiplexer 38.

The input data I N＜15:0 of 16 bits〉be input to 1 search circuit 2-1～2-4 of configuration arranged side by side by per 4 bits,, export Y0＜3:0 here from 1 search circuit 2-1～2-4 〉, S0＜15:0 as middle output.Wherein, Y0＜3:0〉be imported into 1 search circuit 2-5, S0＜15:0〉be input to respectively and a side's of logical circuit 34～37 the incoming line and the incoming line of multiplexer 38.On the other hand, take out dateout Y, middle output Y1＜3:0 from 1 search circuit 2-5 〉.Wherein, middle output Y1＜3:0〉be imported into and the opposing party's of logical circuit 34～37 the incoming line and the selection holding wire of multiplexer 38.

For example, with logical circuit 36 centre output Y1＜2＞output signal S0＜11:8 when being " 1 "＞, in centre output Y1＜2＞output signal when being " 0 " " 0000 ".Multiplexer 38 goes to any one output S0＜i+3:i＞(i=0,4,8,12) from 1 search circuit 2-1～2-4 according to the signal of selecting holding wire as middle output T＜3:0＞output.If with the dateout S＜15:0 of logical circuit 34～37＞for being connected to the data of 16 not shown bit encoder.

In the priority encoder 31 that constitutes as described above, to input data I N＜15:0＞with the dateout S＜15:0 of logical circuit 34～37＞and Y＜3:0＞become and the identical data of situation that 1 search circuit 2 of Fig. 5 is imported as 16 bits.

On the other hand, the 2 the next and upper bits to dateout S＜15:0＞when carrying out priority encoding output to respectively from output T＜3:0 in the middle of the multiplexer 38＞and from output Y1＜3:0 in the middle of the 1 search circuit 2-5＞in.And, in encoder 33a by 2 upper bits of Y1＜3:0＞generation, in encoder 33b by 2 the next bits of T＜3:0＞generation.

For example: suppose input data I N＜15:0＞bit column be " 0000001XXXXXXXXX ", at Y1＜3:0＞interior upper 2 bits " 01 " as output code Q2, Q3 output is gone, at T＜3:0＞interior the next 2 bits " 10 " as output code Q0, Q1 output is gone, and generates 4 bit output codes " 0110 " of the high incoming line (being " 6 " in this case) of expression override ranking thus.Under any circumstance dateout Y is 0 o'clock, S＜15:0＞be identified as " 0000000000000000 ".

In circuit shown in Figure 11, generate dateout S＜15:0＞, intermediate data T＜3:0＞, intermediate data Y1＜3:0＞, but also can only generate wherein S＜15:0＞or T＜3:0＞, Y1＜3:0＞.

Like this, owing to priority encoder is made multilevel hierarchy,, can realize that also circuit constitutes logical circuit simple and the energy high speed processing even under the situation of many bit inputs with 1 search circuit of Fig. 5.

Figure 12 is to use the priority encoder of Fig. 5 to constitute circuit diagram under the situation of used CLA (carry lookahead) circuit of adder.Here, because do not use the 4-1 encoder, so, only utilize 1 search circuit.The CLA circuit is the circuit that generates the PG/PGB/GG/KG group from the P of each bit of taking on (propagation)/G (generation)/K (elimination) signal, is made of 4 bits standard-NMOS NAND circuit AN1, same 4 bit priority encoder PE and 4 * 1 selector SEL1.

Standard-NMOS NAND circuit AN1 is the circuit by the P signal generation group PG signal of each bit.

Priority encoder PE generates output S＜3:0＞and the circuit of PGB signal by the PB signal of each bit.

Selector SEL1 is the double track timing multiplexer that is made of 4 * 1 multiplexer MUX1 and multiplexer MUX2.This selector SEL1 is by G, K signal generation group GG and the KG signal of each bit.Figure 14 is the circuit diagram that is made of selector SEL1 PMOSFET, NMOSFET and logical not component.

Figure 16 is the input and output sequential chart regularly of expression CLA circuit shown in Figure 12.

By precharge, during CLK was " H " level, P is passed with PB was different states during CLK is " L " level for the P (solid line among the figure) of input and PG (dotted line among the figure), that is: when P was " 1 ", PB was " 0 "; When P was " 0 ", PB was " 1 ".P be " 1 " during, G (solid line among the figure), K (dotted line among the figure) both sides are " 0 ", only PB be " 1 " during, a certain side of G or K is " 0 ".According to above-mentioned P, PB, G, timing output group PG/PGB/GG/KG signal that the K signal is identical.

In the sort of CLA circuit shown in Figure 12, because logic element is not constituted dendroid, so can constitute CLA circuit at a high speed.

Figure 17 is connected circuit diagram under the situation of output stage of circuit of Figure 12 with logical circuit, represents with same symbol with the part that Figure 12 is equal.This CLA circuit is by the P/G/K signal of each bit and the group carry input signal C next life circuit of PG/PBG/GG/KG signal and group carry output signal in groups, and connecting from the PGB of priority encoder PE and from the output of selector SEL1 as 2 inputs of input with logical circuit 44,45.Figure 18 is the input and output sequential chart regularly of expression CLA circuit shown in Figure 17.

Like this, constitute like that at Figure 17 under the situation of CLA circuit, also can make the calculating high speed of CG (group carry).

Owing to Figure 12 and CLA circuit shown in Figure 17 are connected to a plurality of dendroids,, in this case, in output stage, adopt CLA circuit shown in Figure 17 so can constitute bigger CLA circuit.

Below, be described in detail in employed CLA circuit in the add operation of many bits as concrete example.

CLA circuit according to present embodiment is characterised in that, whole bit number N (N is the integer greater than 1) is categorized as the group of a plurality of bit m (m is the integer less than N), in each group with the transmitting signal P＜i of every bit, produce signal G＜i, erasure signal K＜i generate group transmitting signal PG, group generation signal GG that the group that constitutes with many bits is a unit, organize erasure signal KG, and use these signals to obtain the carry signal CN-1 of the upper bit of last necessity.

For example: establish N=16, m=4 so, is categorized as 4 groups to input signal A and B:

A＝(a15～a12，a11～a8，a7～a4，a3～a0) ……(1)

B＝(b15～b12，b11～b8，b7～b4，b3～b0) ……(2)

Obtain the carry signal C3 of each group then, C7, C11, C15.

C3＝f(a3～a0，b3～b0) ……(3)

C7＝f(a7～a4，b7～b4)+C3 ……(4)

C11＝f(a11～a7，b11～b7)+C7 ……(5)

C15＝f(a15～a11，b15～b11)+C11 ……(6)

In order to obtain each such group carry signal, must generate with the group from the signal P/G/K of the every bit in organizing is the signal PG/GG/KG of unit, refers again to Figure 12, illustrates that the circuit of a CLA circuit CLA (1) who carries out such computing constitutes.

The one CLA circuit CLA (1) is the circuit of output as the signal PG/GG/KG of the group that is made of 4 bits, is generated the signal P＜3:0 of the every bit in corresponding group in advance by not shown circuit according to following formula〉(=P＜3 〉～P＜0 〉)/G＜3:0〉(=G＜3 〉～G＜0 〉)/K＜3:0〉(=K＜3 〉～K＜0 〉).

P<i>＝/a<i>*/b<i>

G<i>＝a<i>ExOR?b<i>

K<i>＝a<i>*b<i>

The one CLA circuit CLA (1) be provided with generate signal PG with logical circuit AN1, generate and select signal S＜3:0 priority encoder PE, according to selecting signal S＜3:0 generate the selector SEL1 of signal GG, KG.

Import whole P＜3:0 with logical circuit AN1〉signal, and carry out as shown in Figure 7 and logical operation, then its result is exported as PG signal output and/or as the PGB signal that makes the PG counter-rotating.

PG＝P<3>*P<2>*P<1>*P<0> ……(7)

PGB＝/(P<3>*P<2>*P<1>*P<0>)

＝/P<3>+/P<2>+/P<1>+/P<0>

＝PB<3>+/PB<2>+/PB<1>+/PB<0>……(8)

This is corresponding to promptly have only P＜3:0 under the situation of all conducting from the 0th bit to the 3 bits 〉=following carry signal Cin that is withdrawn from by the group of prime of the situation of " 1 " be as the carry signal CG level transmission backward in the corresponding group of its former state.At this moment, signal GG and KG become " 0 " simultaneously.

Whole P＜3:0〉in the signal at least one be under the situation of " 0 ", just must carry out the computing of priority encoder PE.Priority encoder PE be provided with input through the counter-rotating transmitting signal PB＜3:0 NOR circuit NR11, the phase inverter IN11 and the IN12 of the output of input circuit NR11, the NOR circuit NR12 of the output of input phase inverter IN11 and IN12, input counter-rotating group transmitting signal PB＜3:1〉NOR circuit NR21, the phase inverter IN21 and the IN22 of the output of input circuit NR21, the NOR circuit NR22 of the output of input phase inverter IN21 and IN22, input signal PB＜3:2〉NOR circuit NR31, the phase inverter IN31 and the IN32 of the output of input circuit NR31, the NOR circuit NR32 of the output of input phase inverter IN31 and IN42, input signal PB＜3〉NOR circuit NR41, the phase inverter IN41 of the output of input circuit NR21, IN42 and IN43, the output of input phase inverter IN43 and the NOR circuit NR41 of earthing potential " 0 ".Select signal S＜0 from NOR circuit NR12, NR22, NR32, NR41 output respectively 〉～S＜3 〉.

At least some signal P＜3:0〉be (or some at least signal PB＜3:0〉be under the situation of " 1 ") under the situation of " 0 ", priority encoder PE determines signal G＜3:0 〉, K＜3:0 in some signal GG, KG that is taken as group.Here, from signal PB＜3〉begin to retrieve in order, in signal PB＜3〉be under the situation of " 1 ", signal S＜3 〉=" 1 ", other all are " 0 ".In signal PB＜3〉be " 0 " and signal PB＜2 be under the situation of " 1 ", signal S＜2 〉=" 1 ", other all are " 0 ".Like this, some signal S＜3:0〉become " 1 ", other all are " 0 ".

Such selection signal S＜3:0〉be input to selector SEL1.Selector SEL1 has multiplexer MUX1 and MUX2, and selection signal S＜3:0〉be input to each multiplexer MUX1 and MUX2, selecting bit then is the signal G＜3:0 of " 1 " 〉, K＜3:0, and go as the signal GG and the KG output of group respectively.

Here, signal GG and KG represent with following formula.

GG＝P<3>*P<2>*P<1>*G<0>+P<3>*P<2>*G<1>

+P<3>*G<2>*G<3> ……(9)

KG＝P<3>*P<2>*P<1>*K<0>+P<3>*P<2>*K<1>

+ P＜3〉* K＜2〉* K＜3〉... (10) when with selecting signal S＜3:0〉when representing such signal GG and KG, be expressed as follows.At first, import following logical formula.Q<0>＝PG＝P<3>*P<2>*P<1>*P<0>

＝/(PB<3>+PB<2>+PB<1>+PB<0>)……(11)Q<1>＝P<3>*P<2>*P<1>

＝/(PB<3>+PB<2>+PB<1>) ……(12)Q<2>＝P<3>*P<2>

＝/(PB<3>+PB<2>) ……(13)Q<3>＝P<3>

＝/PB<3> ……(14)/Q<0>＝PGB＝/(P<3>*P<2>*P<1>*P<0>)

＝PB<3>+PB<2>+PB<1>+PB<0> ……(15)/Q<1>＝/(P<3>*P<2>*P<1>)

＝PB<3>+PB<2>+PB<1> ……(16)/Q<2>＝/(P<3>*P<2>)

＝PB<3>+PB<2> ……(17)/Q<3>＝/P<3>

=PB＜3〉... (18) S＜0 〉=Q＜1〉*/Q＜0〉... (19) S＜1 〉=Q＜2〉*/Q＜1〉... (20) S＜2 〉=Q＜3〉*/Q＜2〉... (21) S＜3 〉=1*/Q＜3〉... (22) P＜3 wherein〉* PB＜3 〉=P＜2〉* PB＜2 〉=P＜1〉* PB＜1 〉

=P＜0〉* PB＜0 〉=" 0 " ... (23) therefore, above-mentioned (11)～(18) formula becomes following expression.

S<0>＝P<3>*P<2>*P<1>*(PB<3>+PB<2>+PB<1>+PB<0>)＝P<3>*P<2>*P<1>*PB<0> ……(24)

S<1>＝P<3>*P<2>*(PB<3>+PB<2>+PB<1>)

＝P<3>*P<2>*PB<1> ……(25)

S<2>＝P<3>*(PB<3>+PB<2>)

＝P<3>*PB<2> ……(26)

S<3>＝1*PB<3>

＝PB<3> ……(27)

By PB＜3〉* G＜3 〉=G＜3 〉, PB＜2〉and * G＜2 〉=G＜2 〉,

PB＜1〉* G＜1 〉=G＜1 〉, PB＜0〉and * G＜0 〉=G＜0 〉, obtain following relation:

S<0>*G<0>+S<1>*G<1>+S<2>*G<2>+S<3>*G<3>

＝P<3>*P<2>*PB<1>*PB<0>*G<0>+P<3>*P<2>*

PB<1>*G<1>+P<3>*PB<2>*G<2>+PB<3>*G<3>

＝P<3>*P<2>*P<1>*G<0>+P<3>*P<2>*G<1>+P<3

>*G<2>+G<3>

＝GG ……(28)

S<0>*G<0>+S<1>*G<1>+S<2>*G<2>+S<3>*K<3>

＝P<3>*P<2>*P<1>*PB<0>*K<0>+P<3>*P<2>*

PB<1>*K<1>+P<3>*PB<2>*K<2>+PB<3>*K<3>

＝P<3>*P<2>*P<1>*K<0>+P<3>*P<2>*K<1>+P<3

>*K<2>+K<3>

＝KG ……(29)

Obtain following formula (30), (31) thus:

GG＝S<0>*G<0>+S<1>*G<1>+S<2>*G<2>

+S<3>*G<3> ……(30)

GG＝S<0>*K<0>+S<1>*K<1>+S<2>*K<2>

+S<3>*K<3> ……(31)

At first import following logical equation:

Q<0>＝PG＝P<3>*P<2>*P<1>*P<0>

＝/(PB<3>+PB<2>+PB<1>+PB<0>)……(11)

Q<1>＝P<3>*P<2>*P<1>

＝/(PB<3>+PB<2>+PB<1>) ……(12)

Q<2>＝P<3>*P<2>

＝/(PB<3>+PB<2>) ……(13)

Q<3>＝P<3>

＝/PB<3> ……(14)

/Q<0>＝PGB＝/(P<3>*P<2>*P<1>*P<0>)

＝PB<3>+PB<2>+PB<1>+PB<0> ……(15)

/Q<1>＝/(P<3>*P<2>*P<1>)

＝PB<3>+PB<2>+PB<1> ……(16)

/Q<2>＝/(P<3>*P<2>)

＝PB<3>·+PB<2> ……(17)

/Q<3>＝/P<3>

＝PB<3> ……(18)

S<0>＝Q<1>*/Q<0> ……(19)

S<1>＝Q<2>*/Q<1> ……(20)

S<2>＝Q<3>*/Q<2> ……(21)

S<3>＝1*/Q<3> ……(22)

As above-mentioned (8), (24)～(27) formula and shown in Figure 12, select signal S＜3:0〉be PB＜3:0 as the logic of importing that is referred to as priority encoder.

That is: as mentioned above, press PB＜3 〉, PB＜2 〉, PB＜1 〉, PB＜0 sequence arrangement the time, PB＜i 〉=during " 1 " (wherein i=3～0), S＜i 〉=" 1 ", other S＜j〉be " 0 " (wherein j is 3～0 beyond the i), and PBG=" 1 ".

In PB＜3 〉, PB＜2 〉, PB＜1〉and, PB＜0〉when all being " 0 ", whole S＜i 〉=PBG=" 0 ".

Therefore, formula (30), (31) just mean that each logic that generates signal GG/KG is according to selecting signal S＜3:0〉from each four signal G＜3:0, K＜3:0 the multiplexer (4-1MUX) of selection.

As mentioned above, CLA electricity CLA (1) with 4 bits be the group of unit as unit, have and logical circuit AN1, priority encoder PE and selector SEL1, and generate with the group be unit transmitting signal PG, produce signal GG and erasure signal KG.

Here, in a CLA circuit CLA (1), be provided with the formation that generates signal PG, GG, KG fully, still, also can generate signal PG and GG or signal PG and KG.Under the situation that generates signal PG and GG, selector SEL1 has only multiplexer MUX1, and under the situation that generates signal PG and KG, selector SEL1 has only multiplexer MUX2.

The 2nd CLA circuit CLA (2) is described below.

The 2nd CLA circuit CLA (2) is different with an above-mentioned CLA circuit CLA (1), not only generation group transmitting signal PG, group produce signal GG and group erasure signal KG in corresponding group, and use these signals PG, GG, KG to obtain and export group carry signal CG.As concrete formation, the same with formation and the above embodiments of logical circuit AN1 and priority encoder PE as shown in figure 17, still, selector SEL11 is different, and it further adds has and logical circuit AN11 and AN12.

Selector SEL11 has multiplexer MUX11 and MUX12, and multiplexer MUX11 input is from the selection signal S＜3:0 of priority encoder PE output 〉, the G＜3:0 of every bit, from the carry signal C of hyte down, from the signal PG of logical circuit AN1 output.Multiplexer MUX12 input select signal S＜3:0 〉, the K＜3:0 of every bit, from counter-rotating carry signal CB, the signal PG of hyte down.

As mentioned above, at whole signal P＜3:0〉all be under the situation of " 1 ", the signal PG of output " 1 " and the signal PGB of " 0 ".In this case, former state output is from the carry signal C of following hyte and group carry signal CG and the counter-rotating group carry signal CGB of carry signal CB as respective sets that reverse.At this moment, signal PGB all is " 0 ".Therefore, respectively from that import this signal PGB and signal GG and KG logical circuit AN11 and AN12 output " 0 ".

At some at least signal P＜i〉be under the situation of " 0 ", signal PG is " 0 ", signal PGB is " 1 ".Signal G＜3:0 is selected in signal CG in this case and the generation of CGB at first respectively 〉, K＜3:0 in corresponding to selection signal S＜i with " 1 " value signal G＜i, K＜i, then it is exported as the signal CG and the CGB that with the group are unit respectively.And then the PGB of " 1 " signal and signal CGB be input to and logical circuit AN11, and output signal GG; PGB of " 1 " signal and signal CGB are input to and logical circuit AN12, and output signal KG.

, signal CG is expressed as follows as logical formula.

CG＝PG*Cin+GG ……(32)

CGB＝/CG＝PG*/Cin+KG ……(33)

With above-mentioned (30), (31) formula, obtain:

CG＝PG*Cin+S<0>*G<0>+S<1>*G<1>+S<2>*G<2>

+S<3>*G<3> ……(34)

CGB＝PG*/Cin+S<0>*K<0>+S<1>*K<1>+S<2>*K<2>

+S<3>*K<3> ……(35)

Here, by above-mentioned formula (7), (24)～(27), signal PG, S＜3:0〉in have only a signal to be " 1 ", other signals all are " 0 ".

Therefore, the logic that is generated group carry signal CG, CGB by above-mentioned (34) and (35) formula is exactly to select signal PG and S＜3:0 by 5〉5 signal Cin of selection and G＜3:0, and select 5 signal/Cin and K＜3:0 the 5-1 multiplexer.

And by formula (9), (10), (32), (33):

CG*PGB＝GG ……(36)

CGB*PGB＝KG ……(37)

Therefore, as mentioned above, during PG=" 0 " (PGB=" 1 "), get by (36) formula

CG＝GG，KG＝CGB.

In Figure 18, represented the sequential of the input/output signal in the 2nd CLA circuit CLA (2).Here, solid line is represented the level of signal P, G, K, and dotted line is represented the level of each reverse signal PB, GB, KB.

With clock signal clk input signal P＜3:0 synchronously 〉, G＜3:0, K＜3:0 and from the group carry signal C of hyte down, and follow the operating delay time to produce signal GG, group carry signal CG by same timing output group transmitting signal PG, group.

Here, in the 2nd CLA circuit CLA (2), possesses the formation that generates whole signal PG, GG, KG, CG, CGB.But also can possess formation that generates signal PG, GG and CG or the formation that generates signal PG, KG and CGB.Under the situation that generates signal PG, GG and CG, selector SEL11 has only multiplexer MUX1, and generates signal CG with what follow therewith with logical circuit AN11; Under the situation that generates signal PG, KG and CGB, selector SEL11 has only multiplexer MUX2, and uses and logical circuit AN12 generation signal KG.

Then, expression constitutes with the circuit under the situation of the CLA circuit of an above-mentioned CLA circuit CLA (1) and the 2nd CLA circuit CLA (2) formation 32 bits in Figure 19.This CLA circuit is divided into 3 group stratum " 0～2 ", and group stratum " 0～1 " uses a CLA circuit CLA (1), and group stratum " 2 " uses the 2nd CLA circuit CLA (2).

In group stratum " 0 ", every group CLA circuit of group 7～0 generate each signal PG (7), GG (7), KG (7), PG (6), GG (6), KG (6) ..., PG (0), GG (0), KG (0).

In group stratum " 1 ", per 4 groups 7～4, organizing 3～0, to compile respectively be a group, generates signal PGG＜1 of per 16 bits, GGG＜1, KGG＜1, PGG＜0, GGG＜0, KGG＜0.

In group stratum " 2 ", by the 2nd CLA circuit CLA (2) generation whole 32 bits being compiled is signal PGGG, GGGG, the KGGG of a group, and further generates last carry signal CGGG.This signal GGGG is equivalent to carry signal C＜31 of 32 bits 〉.

Desired time of computing and group stratum " 0 " shown in Figure 20, each time of delay in " 1 " and " 2 ", the bulk delay time was T11*3 just when being taken as same T11 in the CLA circuit that constitutes like this.This operating delay time T 11*3 means the time of delay of only accumulating 3 stratum, therefore, compares with the situation that original C LA circuit shown in Figure 4 is accumulated such time of delay every group, according to present embodiment, has shortened computing time.

The example of Figure 13 (b) expression and logical circuit AN1.Circuit symbol represented in the image pattern 13 (a) is such, should generally lead the phase inverter combination in the known NAND circuit as standard-nmos type with logical circuit AN1 to constitute.Clock signal clk is between low period, is connected the NMOSFETN1 conducting between earth terminal and the node ND1, node ND1 discharge.When clock signal clk becomes high level, PMOSFET P1 conducting, the NMOSFET N1 that is connected between earth terminal and the node ND1 ends.

Signal P＜3:0〉respectively after phase inverter IN104～IN101 counter-rotating, be imported into the NMOSFET N14～N11 that is connected between node ND1 and the node ND2.Have only signal P＜3:0〉in signal when all being " 1 ", NMOSFET N14～N11 is all conductings, node ND1 is by PMOSFET P1 discharge, and the signal PG of output " 1 ".Signal P＜3:0〉in some at least signals when being " 0 ", import the FET conducting of this signal, node ND1 is connected with splicing ear, and the signal PG of output " 0 ".Adopt undersized PMOSFET in PMOSFET P1, even among when this PMOSFET P1 conducting, the voltage of the earth terminal of node ND1 just appears approximately approaching being connected at least one NMOSFET N14～N11 conducting.

Owing to use the such standard-nmos type and the logical circuit AN1 that are synchronized with the clock signal clk action, so can make the circuit operation high speed.

Figure 14 represents the example that the circuit of priority encoder PE constitutes.Figure 14 constitutes circuit diagram under the situation of NOR circuit NR11, NR12, NR13 of priority encoder PE of the 2nd CLA circuit CLA (2) of the CLA circuit CLA (1) of Figure 12 and Figure 17 by timing circuit.This priority encoder PE also synchronously carries out the timing action with clock signal clk, input signal PB＜3:0〉NOR circuit constitute by PMOSFET P11～P14, NMOSFET N21～N32, PMOSFET P11～P14 is connected between power supply terminal and the node ND11～ND14, and clock signal clk is input to gate circuit.Be between low period at clock signal clk, node ND11～ND14 is recharged.

NMOSFETN21～N24 is connected in parallel between node ND11～ND21, and NMOSFET N25 is connected between node ND21 and the earth terminal.NMOSFET N26～N28 is connected in parallel between node ND12～ND22, and NMOSFET N29 is connected between node ND22 and the earth terminal.NMOSFET N30～N31 is connected in parallel between node ND13～ND23, and NMOSFET N32 is connected between node ND23 and the earth terminal.NMOSFET N33 is connected between node ND14～ND24, and NMOSFET N34 is connected between node ND24 and the earth terminal.

Clock signal clk is input to the gate circuit of NMOSFET N25, N29, N32, N34, signal P＜O〉be input to the gate circuit of NMOSFET N21, signal P＜1〉be input to the gate circuit of NMOSFET N22 and N26, signal P＜2〉be input to the gate circuit of NMOSFET N23, N27, N30, signal P＜3〉be input to the gate circuit of NMOSFET N24, N28, N31, N33.

At clock CLK is between low period, PMOSFET P11～P14 conducting, and node ND11～ND14 all charges, when clock CLK becomes high level, NMOSFET N25, N29, N32, N34 conducting, node ND21～ND24 discharge.

Only at signal PB＜3:0〉whole signals be under the situation of " 0 ", from node ND11 output high level signal, be under the situation of " 1 " at some at least signals, output low level signal, and the signal PGB that reversed by phase inverter IN111 of output.Only at signal PB＜3:1〉whole signals be under the situation of " 0 ", from node ND12 output high level signal, at some at least signals is under the situation of " 1 ", the output low level signal, and by after the phase inverter IN113 counter-rotating, output with phase inverter IN112 is input to NOR circuit NR101, then output signal S＜0 〉.Only at signal PB＜3:2〉whole signals be under the situation of " 0 ", from node ND13 output high level signal, at some at least signals is under the situation of " 1 ", the output low level signal, and by after the phase inverter IN115 counter-rotating, output with phase inverter IN114 is input to NOR circuit NR102, then output signal S＜1 〉.Only in signal PB＜3〉be under the situation of " 0 ", from node ND14 output high level signal, this signal is under the situation of " 1 ", the output low level signal, and by after the phase inverter IN117 counter-rotating, output with phase inverter IN116 is input to NOR circuit NR103, then output signal S＜2 〉.After phase inverter IN118 reverses the output of phase inverter IN117, further by NOR circuit NR104 counter-rotating, then as signal S＜3〉output.

Figure 15 is with the circuit diagram under the situation of PMOSFET, NMOSFET and logical not component formation selector SEL1.

Multiplexer MUX1, MUX2 with selector SEL1 for example possess the circuit shown in Figure 15 (a) and (b) respectively and constitute, and the PMOSFET P21 of multiplexer MUX1 is connected between power supply terminal and the node ND31; NMOSFET N41 and N42 are connected between node ND31 and the earth terminal; NMOSFET N43 and N44 series connection are in parallel therewith again; NMOSFET N45 and N46 series connection are in parallel therewith again; NMOSFET N47 and N48 series connection are in parallel therewith again.Signal S＜0:3〉be imported into the gate circuit of NMOSFET N41, N43, N45, N47, signal G＜0:3〉be imported into the gate circuit of NMOSFET N42, N44, N46, N48.

Clock signal clk is between low period, PMOSFET P21 conducting, node ND31 charging.When clock signal clk becomes high level, at least have signal S＜0〉and G＜0, signal S＜1 and G＜1, signal S＜2 and G＜2, signal S＜3 and G＜3 among the both become " 1 " combination situation under, node ND31 becomes low level.The level of node ND31 is output as signal GG after being reversed by phase inverter IN21.

Multiplexer MUX2 has the formation the same with multiplexer MUX1, be equivalent to multiplexer MUX1 in signal G＜3:0 be replaced into signal KG＜3:0.PMOSFET P22 is connected between power supply terminal and the node ND32; NMOSFET N51 and N52 are connected between node ND32 and the earth terminal; NMOSFET N53 and N54 series connection are in parallel therewith again; NMOSFET N55 and N56 series connection are in parallel therewith again; NMOSFET N57 and N58 series connection are in parallel therewith again.Signal S＜0:3〉be imported into the gate circuit of NMOSFET N51, N53, N55, N57, signal K＜0:3〉be imported into the gate circuit of NMOSFET N52, N54, N56, N58.

Clock signal clk is between low period, PMOSFET P22 conducting, node ND31 charging.When clock signal clk becomes high level, at least have signal S＜0〉and K＜0, signal S＜1 and K＜1, signal S＜2 and K＜2, signal S＜3 and K＜3 among the both become " 1 " combination situation under, node ND32 becomes low level.The level of node ND32 is output as signal KG after being reversed by phase inverter IN22.

As the circuit that in every bit, generates P, G, K signal, also can use for example circuit shown in Figure 21 (a)～(d).Two input signal A of circuit shown in Figure 21 (a) input and B (/A and/B), between A and B, carry out disjunction operation then, produce and output signal P.Clock signal clk is imported into the gate circuit of PMOSFET P31, between low period, and node ND41 charging.When clock signal clk became high level, the gate circuit of NMOSFET N63 was imported this level and conducting.The gate circuit difference input signal A of NMOSFET N61, N62, N64, N65 ,/B ,/A, B, according to the combination of these level, keep the charged state or the discharge of having filled electric node ND41.The level of this node ND41 is by being outputted as signal P after the phase inverter IN131 counter-rotating.

Circuit shown in Figure 21 (b) logic and on added counter-rotating signal PB output between two input signal A and the B.This circuit be equivalent to the combination A of the signal of the gate circuit that is input to NMOSFETN61, N62 in the circuit of Figure 21 (a), N64, N65 ,/B ,/A, B be replaced into A, B ,/A ,/circuit of B.

Circuit shown in Figure 21 (c) is the circuit that carries out logic product computing and output signal G between A and B.Clock signal clk is imported into the gate circuit of PMOSFET P33, between low period, and node ND43 charging.Signal A, B are imported into NMOSFET N81, N82 respectively, according to the combination of these level, keep the charged state or the discharge of having filled electric node ND43.When clock signal clk became high level, the gate circuit of NMOSFET N33 was imported this level and conducting.The level of this node ND43 is by being outputted as signal G after the phase inverter IN133 counter-rotating.

Circuit shown in Figure 21 (d) carries out exclusive disjunction operation and output signal K between A and B, and this circuit is equivalent to combination A, the B of the signal of the gate circuit that is input to NMOSFET N81, N82 in the circuit of Figure 21 (c) are replaced into/A ,/B.

Figure 22 (a) and (b) respectively expression generate with clock signal clk synchronous the carry signal Cin of every bit and an example of the circuit of the waveform C of counter-rotating carry signal/Cin and CB.

As top illustrated, CLA circuit of the present invention is delivered to signal P, G, the K of every m bit in the group that is made of the m bit, and to obtain with the group be signal PG, GG, the KG of unit, so, even when asking the carry of the many computings of bit number, in many groups, use every group to obtain next signal PG, GG, KG, thereby can shorten the computing relay time.

For example, in circuit shown in Figure 19 constitutes, the computing of whole 32 bits is divided into the group of per 4 bits, asks every group signal PG, GG, KG, obtain carry signal CGGG at last again with 3 groups group stratum.Constituting with the physical circuit of logical circuit AN1, priority encoder PE, selector SE is an example, also can form various distortion.

Circuit diagram under the situation that Figure 23 is standard-NMOS NAND circuit 42 shown in Figure 17 with 1 search circuit 2-7 is connected is represented with same label with the part that Figure 17 is equal.This standard-NMOS NAND circuit 42, as shown in figure 24, this standard-nmos circuit 62 is connected on the timing circuit 46 by same logical constitution, and timing circuit 46 is parts of 1 search circuit 2-7.Standard-nmos circuit 62 is connected in parallel between earthing potential and the holding wire X, by the NMOSFET of the reverse signal of the P signal of accepting each bit, power supply be connected PMOS gate circuit 47 on the holding wire X, NAND circuit 48 that control signal is delivered to PMOS gate circuit 47 constitutes.Equally, timing circuit 46 is connected in parallel between earthing potential and the holding wire X, by the NMOSFET of the PB signal of accepting each bit, power supply is connected holding wire X ^*On PMOS gate circuit 49 constitute.

Figure 25 is the sequential chart of timing of the input and output of expression standard-NMOS NAND circuit 42 shown in Figure 24.

Input signal to standard-nmos circuit 62 is thus lifted to " H " level between precharge phase, therefore, holding wire X pulled down to " L " level.

Input signal to timing circuit 46 is thus lifted to " H " level between precharge phase, therefore, and holding wire X ^*Pulled down to " H " level simultaneously.On the other hand, during output is determined,, import signal P＜3:0 of each bit P as to the input signal of standard-nmos circuit 62 with to the input signal of timing circuit 46〉and signal PB＜3:0 of each bit P.

Between precharge phase, because the output signal OUTPUT* of timing circuit 46 (counter-rotating of OUTPUT) is precharged to " H " level, so, allow signal En to make the output of control signal 48 become " 1 ", 47 conductings of PMOS gate circuit.During later output is determined, determine the logical value of full-scale input, but here logic is (that is: holding wire X and earthing potential is disconnected) under the situation of non-establishment, because the holding wire X of standard-nmos circuit 62 is not pulled down to the current path of " L " level, PMOS gate circuit 47 makes holding wire X be fixed on " H " level, so, do not flow through current sinking.On the other hand, under the situation that logic is set up, because there is the current path that holding wire X is pulled down to " L " level, PMOS gate circuit 47 conductings and consume useless electric current.But, in timing circuit 46, make holding wire X because logic sets up ^*Be changed to " L " level, be changed to " L " level output signal OUTPUT*.Like this, PMOS gate circuit 47 is ended, so flow through with regard to the no consumption electric current by control circuit 48.

Above formation generally be applied to the moving such timing circuit of output and the combination of standard-nmos circuit, that is: Figure 26 is the circuit diagram of configuration example of the combination of the synchronously such timing circuit of output and standard-nmos circuit.This standard-nmos circuit 62 and timing circuit 46 are that the NMOSFET by same logical constitution constitutes.But, if holding wire X and holding wire X ^*The same logical value of output during output is determined, just there is no need to constitute by same logic especially, such standard-nmos circuit is set up in parallel between earthing potential and holding wire X, and by the NMOSFET of the P signal of accepting each bit, power supply be connected to the PMOS gate circuit 47 of holding wire X, the NAND circuit 48 that control signal is added to PMOS gate circuit 47 constitutes.Equally, timing circuit 46 is connected in parallel between earthing potential and the holding wire X, by the NMOSFET of the PB signal of accepting each bit, power supply is connected holding wire X ^*On PMOS gate circuit 49 constitute.

Figure 27 is the sequential chart of timing of the input and output of expression standard-NMOS NAND circuit 61 shown in Figure 26.

Input signal INPUT[N:0 to standard-NMOS NAND circuit 62] and to the input signal INPUT*[N:0 of timing circuit 63 input] be the signal of during input is determined, getting equal logical value.

Input signal INPUT[N:0 to standard-NMOS NAND circuit 62] between precharge phase, be promoted to " H " level, therefore, holding wire X by drop-down be " L " level.

Input signal INPUT*[N:0 to timing circuit 46 inputs] between precharge phase, be promoted to " H " level, therefore, holding wire X ^*Simultaneously by drop-down be " H " level.On the other hand, during output is determined, be input as INPUT[N:0 to the input signal of standard-NMOS NAND circuit 62 with to the input signal that should estimate of timing circuit 46] and INPUT*[N:0].

Because the output signal OUTPUT* of timing circuit 46 (counter-rotating of OTPUT) is charged to " H " level, so, allow signal En to make the output of control circuit 48 become " 1 ", 47 conductings of PMOS gate circuit.After this during output is determined, determine the logical value of full-scale input, but here logic is (that is: holding wire X and earthing potential is disconnected) under the situation of non-establishment, because the holding wire X of standard-nmos circuit 62 is not pulled down to the current path of " L " level, PMOS gate circuit 47 makes holding wire X be fixed on " H " level, so, do not flow through current sinking.On the other hand, under the situation that logic is set up, because there is the current path that holding wire X is pulled down to " L " level, PMOS gate circuit 47 conductings and consume useless electric current.But, in timing circuit 46, make holding wire X because logic sets up ^*Be changed to " L " level, output signal 0UTPUT* also is changed to " L " level.Like this, PMOS gate circuit 47 is ended, so flow through with regard to the no consumption electric current by control circuit 48.

Figure 28 is the circuit diagram of the logical circuit of the standard-standard-NMOS NAND circuit formation according to complementation of the present invention.This logical circuit 71 possess first standard-nmos circuit 72 and with the second standard-PMOS circuit 73 of this first standard-nmos circuit 72 complementations.First standard-nmos circuit 72 is made of the combinational circuit 72n through the NMOS FET of PMOS gate circuit 74 supply powers, and second standard-PMOS circuit 73 also is made of the combinational circuit 73n through the NMOS FET of PMOS gate circuit 75 supply powers.In addition, NAND circuit 76,77 is connected in two standard-nmos circuits, logical value during the output signal precharge of NAND circuit 76,77 these two circuit of usefulness cause is ended the PMOS gate circuit 74,75 of standard-nmos circuit, and logic is set up and PMOS gate circuit 74,75 the other side each other during counter-rotating.

Figure 29 is the sequential chart of timing of input and output of the standard-standard-NMOS NAND circuit of expression complementation shown in Figure 28.

If produce complementary output, also can be any signal promptly to the combination of the gate signal of NMOS FET key element to the input signal of first standard-nmos circuit 72 with to second standard-PMOS circuit 73 input signals.For example: as to the input signal of first standard-nmos circuit 72 with to second standard-PMOS circuit 73 input signals, the input signal INPUT[N:0 of the logical value of mutual counter-rotating is got in input during output is determined] and INPUT* (counter-rotating of INPUT) [N:0].

Between precharge phase, to the input signal INPUT[N:0 of first standard-nmos circuit 72] and to second standard-PMOS circuit 73 input signal INPUT*[N:0] be promoted to " H " level, therefore, holding wire X and holding wire X ^*Drop-down is " L " level.

Because the output signal OUTPUT of first standard-nmos circuit 72 is precharged to " H " level, so, during output is determined, allow signal En to make NAND circuit 76 be output as " 1 ", 74 conductings of PMOS gate circuit.

Equally, because the output signal OUTPUT* of second standard-nmos circuit 73 is precharged to " H " level, so, during output is determined, allow signal En to make NAND circuit 77 be output as " 1 ", 75 conductings of PMOS gate circuit.After this, during output is determined, determine the logical value of full-scale input, here, either party establishment of combinational circuit 72n and combinational circuit 73n, the opposing party just is false.Therefore, holding wire X or the X in standard-nmos circuit of just logic not being set up ^*Drop-down is the current path of " L " level, and PMOS gate circuit 74 or 75 is holding wire X or X ^*Be fixed on " H " level, so there is not current sinking to flow through.On the other hand, in standard-nmos circuit that logic is set up, because exist holding wire X or X ^*Drop-down is the current path of " L " level, thus PMOS gate circuit 73 or 74 conductings, and consume useless electric current.But, because the output signal OUTPUT of standard-nmos circuit that logic is not set up or OUTPUT* are changed to " L " level, thus NAND circuit 76 or 77 conductings, and PMOS gate circuit 74 or 75 ends, and does not have current sinking to flow through.

Figure 30 is the circuit diagram as the logical circuit of the complementation of the present invention of the application examples use standard-NMOS NAND circuit of circuit shown in Figure 28.This logical circuit 81 possesses first standard-nmos circuit 82 and has second standard-PMOS circuit 83 with the output of this first standard-nmos circuit 82 complementations.First standard-nmos circuit 82 is made of the combinational circuit 82n through the NMOS FET of PMOS gate circuit 84 supply powers, and second standard-PMOS circuit 83 also is made of the combinational circuit 83n through the NMOS FET of PMOS gate circuit 85 supply powers.As to the input signal of first standard-nmos circuit 82 with to the input signal of second standard-PMOS circuit 83, the input signal INPUT[N:0 of the logical value of mutual counter-rotating is got in input during output is determined] and input signal INPUT* (counter-rotating of INPUT) [N:0].Here, N=2 according to the formula of De Morgan, is made as the combinational circuit 83n of the combinational circuit 82n of NMOS FET and NMOS FET:

/(([0]*[1]+[2]-(/[0]+/[1])*/[2]

Figure 31 is the sequential chart of timing of input and output of the standard-standard-NMOS NAND circuit of complementation shown in Figure 30.

If produce complementary output, also can be any combination promptly to the combination of the gate signal of NMOS FET key element to the input signal of first standard-nmos circuit 82 with to second standard-PMOS circuit 83 input signals.For example: as to the input signal of first standard-nmos circuit 82 with to second standard-PMOS circuit 83 input signals, the input signal INPUT[2:0 of the logical value of mutual counter-rotating is got in input during output is determined] and INPUT* (counter-rotating of INPUT) [2:0].

Between precharge phase, to the input signal INPUT[2:0 of first standard-nmos circuit 82] and to second standard-PMOS circuit 83 input signal INPUT*[2:0] be promoted to " H " level, therefore, holding wire X and holding wire X ^*By drop-down be " L " level.

Because the output signal OUTPUT of first standard-nmos circuit 82 is precharged to " H " level, so, during output is determined, allow signal En to make NAND circuit 86 be output as " 1 ", 84 conductings of PMOS gate circuit.

Equally, because the output signal OUTPUT* of second standard-nmos circuit 83 is precharged to " H " level, so, during output is determined, allow signal En to make NAND circuit 87 be output as " 1 ", 85 conductings of PMOS gate circuit.After this, during output is determined, determine the logical value of full-scale input, here, either party establishment of combinational circuit 82n and combinational circuit 83n, the opposing party just is false.Therefore, holding wire X or the X in standard-nmos circuit of just logic not being set up ^*Drop-down is the current path of " L " level, and PMOS gate circuit 84 or 85 is holding wire X or X ^*Be fixed on " H " level, so there is not current sinking to flow through.On the other hand, in standard-nmos circuit that logic is set up, because exist holding wire X or X ^*Drop-down is the current path of " L " level, thus PMOS gate circuit 83 or 84 conductings, and consume useless electric current.But, because the output signal OUTPUT of standard-nmos circuit that logic is not set up or OUTPUT* are changed to " L " level, thus NAND circuit 86 or 87 conductings, and PMOS gate circuit 84 or 85 ends, and does not have current sinking to flow through.

In addition, NAND circuit 86,87 is connected in two standard-nmos circuits, logical value during the output signal precharge of NAND circuit 86,87 these two circuit of usefulness cause is ended the PMOS gate circuit 84,85 of standard-nmos circuit, and logic is set up and PMOS gate circuit 84,85 the other side each other of standard-nmos circuit during counter-rotating.

Claims (9)

1. initial logical circuit of 0 or 1 that occurs of retrieval when upper bit begins to check in order the bit of serial data of 2 system numbers comprises:

Constitute and accept the NOT logic of upper bit of the serial data of described 2 system numbers by dynamic circuit;

Constitute by dynamic circuit respectively, corresponding one by one with the bit beyond the upper bit of the serial data of described 2 system numbers, input is corresponding to the bit of the serial data of the described 2 system numbers of this bit position and be in the NOR circuit of the bit more upper than this bit position;

Accept 2 input NOR circuit of two logical signals from the circuit of described NOT logic and NOR circuit adjacency.

2. according to the logical circuit of claim 1, it is characterized in that described NOT logic and NOR circuit are made of the NMOS FET that is connected in parallel between the output line that is connected in parallel on earthing potential and described NOT logic and NOR circuit.

3. according to the logical circuit of claim 1, it is characterized in that being inserted with phase inverter in the prime of described 2 input NOR circuit.

4. a logical circuit is made of timing circuit, standard-nmos circuit and logic gates;

Timing circuit is made of first combinational circuit that is connected between output line and the earthing potential, between precharge phase, control described first combinational circuit, when described earthing potential is cut off described output line, power supply is supplied with described output line, make described output line bring up to " H " level, during output is determined, when the input signal that should estimate is delivered to described first combinational circuit, stop the power supply of described output line is supplied with, selectively described earthing potential and described output line are coupled together according to this logical operation value, export determined logical value through described output line;

Standard-nmos circuit is made of second combinational circuit that is connected between output line and the earthing potential, between described precharge phase, control described second combinational circuit, described earthing potential is connected to described output line, make described output line be reduced to " L " level, during described output is determined, when the input signal that should estimate is delivered to described first combinational circuit, power supply is supplied with described output line, selectively described earthing potential is cut off described output line according to this logical operation value, export determined logical value through described output line;

Logic gates is connected to described timing circuit, and according to the signal of the described output line of described timing circuit, control is supplied with the power supply of the described output line of described standard-nmos circuit;

Described timing circuit is the same or complementary with the logical value that described standard-nmos circuit is determined, during described output is determined, the described output line of described standard-nmos circuit is connected to earthing potential, under the situation that is reduced to " L " level, respond to the variation of the described output line of standard-nmos circuit correspondence, described logic gates stops the power supply of the described output line of described timing circuit is supplied with.

5. according to the logical circuit of claim 4, it is characterized in that described first combinational circuit and described second combinational circuit are made of the NMOS FET with same logical constitution.

6. standard-NMOS logical circuit is made of second standard-nmos circuit, first standard-nmos circuit, first logic gates, second logic gates;

Second standard-nmos circuit is made of second combinational circuit that is connected between output line and the earthing potential, between described precharge phase, control described second combinational circuit, described earthing potential is connected to described output line, make described output line be reduced to " L " level, during described output is determined, when the input signal that should estimate is delivered to described first combinational circuit, power supply is supplied with described output line, selectively described earthing potential is cut off described output line according to this logical operation value, export determined logical value through described output line;

First standard-nmos circuit is made of first combinational circuit that is connected between output line and the earthing potential, between precharge phase, control described first combinational circuit, described earthing potential is connected to described output line, make described output line be reduced to " L " level, during described output is determined, when the input signal that should estimate is delivered to described first combinational circuit, power supply is supplied with described output line, selectively described earthing potential is cut off described output line according to this logical operation value, export determined logical value through described output line;

First logic gates basis is supplied with the power supply of the described output line of described first standard-nmos circuit from the signal controlling of the described output line of described second standard-nmos circuit;

Second logic gates basis is supplied with the power supply of the described output line of described second standard-nmos circuit from the signal controlling of the described output line of described first standard-nmos circuit;

Described first standard-nmos circuit and described second standard-nmos circuit are complementary, during described output is determined, described earthing potential be connected to described first standard-nmos circuit and described second standard-nmos circuit a side described output line and pull down under the situation of " L " level, according to the variation of " H " level of the opposing party's described output line, first or second logic gates stops the power supply of the opposing party's of described standard-nmos circuit described output line is supplied with.

7. carry lookahead circuit, input every the transmitting signal P of m (m is the integer more than 1) bit, produce at least one side among signal G and the erasure signal K, group transmitting signal PG, the group that generates the corresponding group of conduct that is made of the m bit produces at least one side among signal GG and the group erasure signal KG; Described carry lookahead circuit is made of logical circuit, priority encoder and selection circuit;

All have under the situation of a logical value at described transmitting signal P or all have at counter-rotating group transmitting signal PB under the situation of reverse value of a described logical value, the logical circuit output device has described group of transmitting signal PG of a described logical value and/or has the described counter-rotating group transmitting signal PGB of the reverse value of a described logical value;

According to from the upper bit to described transmitting signal P of the next ordered retrieval and/or described counter-rotating group transmitting signal PB, and generate the selection signal of effective m bit corresponding to the bit of the signal of the reverse value of the described logical value of initial appearance among the described transmitting signal P or the described logical value of initial appearance among the described counter-rotating group transmitting signal PB, and do not occur in any bit of described transmitting signal P under the situation of reverse value of a described logical value, do not occur under the situation of a described logical value in any bit of perhaps described counter-rotating group transmitting signal PB, priority encoder is exported any bit does not become the effective choice signal;

Import described selection signal, and when significant bit is input to described selection signal, selector is selected among described generation signal G and/or the described erasure signal K generation signal G and/or the erasure signal K corresponding to the significant bit of described selection signal, and go as described group of generation signal GG and/or described group of erasure signal KG output respectively, any bit at described selection signal does not become under the effective situation, and the selector output device has described group of generation signal GG and/or described group of erasure signal KG of the reverse value of a described logical value.

8. carry lookahead circuit, input carry signal C, every the transmitting signal P of m (m is the integer more than 1) bit, produce at least one side among signal G and the erasure signal K, group transmitting signal PG, group carry signal CG, the group that generates the corresponding group of conduct that is made of the m bit produces at least one side among signal GG and the group erasure signal KG; Described carry lookahead circuit is made of logical circuit, priority encoder and selection circuit;

All have under the situation of a logical value at described transmitting signal P or all have at counter-rotating group transmitting signal PB under the situation of reverse value of a described logical value, the logical circuit output device has described group of transmitting signal PG of a described logical value and/or has the described counter-rotating group transmitting signal PGB of the reverse value of a described logical value;

According to from upper to described transmitting signal P of the next ordered retrieval and/or described counter-rotating group transmitting signal PB, and generate the selection signal of effective m bit corresponding to the bit of the signal of the reverse value of the described logical value of initial appearance among the described transmitting signal P or the described logical value of initial appearance among the described counter-rotating group transmitting signal PB, and do not occur in any bit of described transmitting signal P under the situation of reverse value of a described logical value, do not occur under the situation of a described logical value in any bit of perhaps described counter-rotating group transmitting signal PB, priority encoder is exported any bit does not become the effective choice signal;

Import described selection signal, and when significant bit is input to described selection signal, selector is selected among described generation signal G and the described erasure signal K generation signal G and the erasure signal K corresponding to the significant bit of described selection signal, and go as described group carry signal CG and counter-rotating group carry signal CGB output respectively, any bit at described selection signal does not become under the effective situation, and selector is exported described carry signal C according to described group of transmitting signal PG or described counter-rotating group transmitting signal PGB as described group carry signal CG.

9. a carry lookahead circuit is made of a plurality of first carry lookahead circuit groups, a plurality of second carry lookahead circuit group and the 3rd carry lookahead circuit;

The first carry lookahead circuit group is made of a plurality of first carry lookahead circuits;

The second carry lookahead circuit group is made of a plurality of second carry lookahead circuits, and each second carry lookahead circuit is connected to described first carry lookahead circuit of each group that belongs to the described first carry lookahead circuit group;

The 3rd carry lookahead circuit is connected on the described second carry lookahead circuit group;

The input of described first carry lookahead circuit every the transmitting signal of m (m is the integer 1 or more) bit, produce at least one side in signal and the erasure signal, generate at least one side in first group of transmitting signal of the corresponding group of conduct that constitutes by the m bit, first group of generation signal and the first group of erasure signal;

Described first carry lookahead circuit is made of logical circuit, priority encoder and selection circuit,

Described transmitting signal all has under the situation of a logical value or all has at counter-rotating group transmitting signal under the situation of reverse value of a logical value, and the logical circuit output device has described first group of transmitting signal of a described logical value and/or has the described first counter-rotating group transmitting signal of the reverse value of a described logical value;

According to from the upper bit to described transmitting signal of the next ordered retrieval and/or described counter-rotating group transmitting signal, and generate the selection signal of effective m bit corresponding to the bit of the signal of the reverse value of the described logical value of initial appearance among the described transmitting signal or the described logical value of initial appearance among the described counter-rotating group transmitting signal, and do not occur in any bit of described transmitting signal under the situation of reverse value of a described logical value, do not occur in any bit of perhaps described counter-rotating group transmitting signal under the situation of a described logical value, priority encoder is exported any bit does not become the effective choice signal;

Import described selection signal, and when significant bit is input to described selection signal, selector is selected among described generation signal and/or the described erasure signal generation signal and/or the erasure signal corresponding to the significant bit of described selection signal, and go as described first group of generation signal and described first group of erasure signal output respectively, any bit at described selection signal does not become under the effective situation, and the selector output device has described first group of generation signal and/or described first group of erasure signal of the reverse value of a described logical value.

Described second carry lookahead circuit is imported described first group of transmitting signal, described first group of at least one side who produces in signal and the described first group of erasure signal, and the second group of transmitting signal, second group that generates the first corresponding carry lookahead circuit group produces at least one side in signal and the second group of erasure signal;

Described second carry lookahead circuit is made of logical circuit, priority encoder and selection circuit;

All have under the situation of a logical value at described first group of transmitting signal or all have at the described first counter-rotating group transmitting signal under the situation of reverse value of a logical value, the logical circuit output device has described second group of transmitting signal of a described logical value and/or has the described second counter-rotating group transmitting signal of the reverse value of a described logical value;

According to from the upper bit to described first group of transmitting signal of the next ordered retrieval and/or the described first counter-rotating group transmitting signal, and generate the selection signal of effective many bits corresponding to the bit of the signal of the reverse value of the described logical value of initial appearance among described first group of transmitting signal or the described logical value of initial appearance among the described first counter-rotating group transmitting signal, and do not occur in any bit of described first group of transmitting signal under the situation of reverse value of a described logical value, do not occur in any bit of the perhaps described first counter-rotating group transmitting signal under the situation of a described logical value, priority encoder is exported any bit does not become the effective choice signal;

Import described selection signal, and when significant bit is input to described selection signal, selector selects described first group of first group of producing among signal and/or the described first group of erasure signal corresponding to the significant bit of described selection signal to produce signal and/or first group of erasure signal, and go as described second group of generation signal and/or described second group of erasure signal output respectively, any bit at described selection signal does not become under the effective situation, and the selector output device has described second group of generation signal and/or described second group of erasure signal of the reverse value of a described logical value;

Described the 3rd carry lookahead circuit input carry signal, described second group of transmitting signal, described second group of at least one side who produces in signal and the described second group of erasure signal, the 3rd group of transmitting signal, group carry signal, the 3rd group that generates the second corresponding carry lookahead circuit group produces at least one side in signal and the 3rd group of erasure signal;

Described the 3rd carry lookahead circuit is made of logical circuit, priority encoder and selection circuit,

Described second group of transmitting signal all has under the situation of a logical value or all has at the described second counter-rotating group transmitting signal under the situation of reverse value of a logical value, and second group of transmitting signal organized in described second counter-rotating that the logical circuit output device has described the 3rd group of transmitting signal of a described logical value and/or has a reverse value of a described logical value;

According to from the upper bit to described second group of transmitting signal of the next ordered retrieval and/or the described second counter-rotating group transmitting signal, and generate the selection signal of effective many bits corresponding to the bit of the signal of the reverse value of the described logical value of initial appearance among described second group of transmitting signal or the described logical value of initial appearance among the described second counter-rotating group transmitting signal, and do not occur in any bit of described second group of transmitting signal under the situation of reverse value of a described logical value, do not occur in any bit of the perhaps described second counter-rotating group transmitting signal under the situation of a described logical value, priority encoder is exported any bit does not become the effective choice signal;

Import described selection signal, and when significant bit is input to described selection signal, selector selects described second group of second group of producing among signal and the described second group of erasure signal corresponding to the significant bit of described selection signal to produce signal and second group of erasure signal, and go as described group carry signal and the output of described counter-rotating group carry signal respectively, any bit at described selection signal does not become under the effective situation, selector utilizes described the 3rd group to produce signal and described the 3rd group of erasure signal, and described carry signal is gone as described group carry signal output.

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