CN1265264C - Circuit andm ethod for coordinating south-north bridge circuit and CPU at different energy saving state - Google Patents
Circuit andm ethod for coordinating south-north bridge circuit and CPU at different energy saving state Download PDFInfo
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- CN1265264C CN1265264C CN 200410082586 CN200410082586A CN1265264C CN 1265264 C CN1265264 C CN 1265264C CN 200410082586 CN200410082586 CN 200410082586 CN 200410082586 A CN200410082586 A CN 200410082586A CN 1265264 C CN1265264 C CN 1265264C
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Abstract
The present invention provides a circuit and a correlative method for coordinating a south bridge circuit, a north bridge circuit and a central processor to switch among different energy saving states. In a better embodiment of the present invention, an indication online circuit is arranged between the south bridge circuit and the north bridge circuit with an open drain electrode configuration. When the south bridge circuit and the north bridge circuit process bus master requirements, the south bridge circuit and the north bridge circuit can respectively send out indication signals on the indication online circuit; the open drain electrode configuration can cause signals on the indication online circuit to simultaneously reflect processing situation required by the south bridge circuit and the north bridge circuit to the bus master. According to the signals on the indication online circuit, the south bridge circuit and the north bridge circuit can control the central processor to switch to an appropriate energy saving state so as to serve the requests of the bus master, and the central processor does not need to recover to a weakest energy saving state in a global function to coordinate and process the requests of the bus master.
Description
Technical field
The present invention relates to a kind ofly can coordinate circuit and the correlation technique that north and south bridge circuit and central processing unit switch on different power save modes, particularly relate to and a kind ofly indicate online circuit to make the north and south bridge circuit can coordinate central processing unit to switch on circuit and the correlation technique of C2/C3 power save mode with the snoop bus master service with the drain electrode framework of opening of simplifying.
Background technology
Computer system is one of most important hardware foundation of advanced information society.Except the pursuit to usefulness, modern computer system also will be particular about the reduction of power consumption.So also will reducing power consumption, modern information manufacturer is considered as one of emphasis of computer system research and development.
In computer system, can be provided with the processing and the computing of central processing unit major control data data, the chipset that is formed by north bridge circuit, south bridge circuit then is in charge of the exchanges data of central processing unit and other peripheral unit.For instance, north bridge circuit can be connected in system storage and graphics acceleration card by its bus, and south bridge circuit then can be connected in peripheral units such as Winchester disk drive, CD-ROM drive, keyboard, mouse by bus.Because central processing unit can the whole computer system of master control carry out the different running of many kinds, in order to reduce the power consumption under different situations, modern central processing unit can both operate on the power save mode of multiple different levels.As known to persons skilled in the art, Xian Dai central processing unit can operate on various power save modes from shallow to deep such as C0, C1, C2, C3, C4 and C5.Under state C0, central processing unit can be brought into play the function of various computings, control fully, can normally receive/send various instructions, signal and clock, and relatively its power consumption is also the highest.Under darker power save mode C1, central processing unit will enter awaits orders (halt) state and stops to send instruction, and central processing unit just was unlike in and can brings into play function completely under the state C0 this moment; Relatively, its power consumption also can reduce.Under the more further power save mode C2 than state C1, except buttoned-up function under the state C1, central processing unit also can further stop the output of clock, only keeps the running of its inner phase-locked loop (PLL) with electric power; And the volatile cache memory in the central processing unit (cache) also only is to keep the content that it is write down with electric power.In other words, under state C2, the function ratio state C1 that central processing unit can carry out is also few, but the power consumption under the state C2 also can come lowly than state C1.
By that analogy, arrived darker power save mode C3, central processing unit also can further cut out inner phase-locked loop to save more energy; Under state C3,1/5 to 1/10 under the C0 state reduced in the power consumption of central processing unit.After entering darker state C4, C5, the power consumption of central processing unit is lower, and relatively its function that can bring into play is also just more and more limited.
Enter darker power save mode the power consumption of central processing unit is reduced, but in order to keep the normal operation of whole computer system, central processing unit still must switch, return to more shallow power save mode according to circumstances.For instance, when the peripheral unit of north bridge, south bridge circuit was needing data in the access system storer, peripheral unit can require south bridge circuit to pass through the north bridge circuit access memory, and this behavior is called bus master (bus master).When carrying out bus master for peripheral unit, the north and south bridge circuit is except will managing the exchanges data between this peripheral unit and system storage, north bridge circuit also wants to carry out spying upon (snooping) running to central processing unit earlier (promptly please check in the internal cache (Cache) whether have this document by central processing unit, and be up-to-date value), to guarantee the consistance of data in cache memory in the central processing unit and the system storage.As known to persons skilled in the art, central processing unit is at executive routine, when handling data, and data that may it is required are loaded on by system storage in the cache memory of central processing unit itself, to accelerate the access speed to these data.Yet, after central processing unit carries out content update to the data in the cache memory, the but corresponding data in the update system storer at once not necessarily.At this moment, when wanting the access system storer if there is peripheral unit to send the bus master requirement, just these not data updated are arrived in access mistakenly.Can not take place in order to ensure above-mentioned this situation, when peripheral unit sends the bus master requirement, north bridge circuit can provide the service of spying upon running, to check whether the high-speed buffer storage data in the central processing unit belongs to the data that peripheral unit is wanted access, guarantee peripheral access to data have correct content.
In order to support north bridge circuit to carry out the above-mentioned running of spying upon, when peripheral unit sent the bus master requirement, central processing unit will operate on state C2 or more shallow power save mode at least.If central processing unit operates on state C3 or darker power save mode, just can't support that north bridge circuit provides the service of spying upon.And in known technology, the relevant running in order to want snoop bus master to require then will wake central processing unit up to the most shallow power save mode C0; Its process can be summarized as follows.When central processing unit operates on the C3 state, require signal to give south bridge circuit if there is peripheral unit to propose bus master, south bridge circuit can be transformed into numeral 1 with state signal STPCLK# (# represents anti-phase STPCLK) and SLP# by numeral 0 in regular turn, so just can make its switching operate on Full Featured state C0 with central processing unit by waking up among the state C3.After central processing unit returns to state C0, just can send the requirement of change buffer, another buffer (stoping bus master to require signal to north bridge circuit) IO22 (or claiming ARB_DIS) that is positioned at south emigrant's circuit is changed into numeral 0 by numeral 1, represent north bridge circuit and central processing unit can support to spy upon service.In view of the above, the north and south bridge circuit will formally begin to handle the bus master of peripheral unit, provides the service of spying upon by north bridge circuit.
Yet one of shortcoming of above-mentioned known technology is exactly its power consumption that can't effectively reduce central processing unit.Central processing unit just can be supported the service of spying upon of north bridge circuit at state C2 in fact, so central processing unit will being waken up to state C0 of above-mentioned known technology, be because central processing unit could change the state of buffer IO22 under state C0, and guarantee further that north bridge circuit is switched to by state C3 and could support to spy upon service more than the state C2.Except changing buffer IO22, the bus master of peripheral unit requires only to need to respond processing by the north and south bridge circuit, does not need central processing unit that other computing service is provided.So above-mentioned central processing unit is waken up to state C0 handled the known technology that bus master requires, and can cause unnecessary highly energy-consuming.
Summary of the invention
Therefore, fundamental purpose of the present invention, be that proposition is a kind of to indicate online circuit to coordinate the circuit and the relevant apparatus of north and south bridge circuit service bus master control requirement, making central processing unit only need return to state C2 can the snoop bus master requirement, overcomes known technology and need make central processing unit return to state C0 and the shortcoming that increases power consumption.
The invention provides the chipset that a kind of tunable north and south bridge circuit operates on different power save modes, it includes: a north bridge circuit, it has a north bridge and exports into end, when this north bridge circuit receives a bus master of being sent by a peripheral unit that is connected to this north bridge circuit, export into end by this north bridge and to send one first indicating signal; One south bridge circuit, it has a south bridge exports into end, when this south bridge circuit receives a bus master of being sent by a peripheral unit that is connected to this south bridge circuit, exports into end by this south bridge and to send one second indicating signal; And the online circuit of an indication, export into this first indicating signal of end and this south bridge according to this north bridge and to export this second indicating signal into end, carry out a logical operation and produce state adjustment signal, this state adjustment signal controls this north bridge circuit and this south bridge circuit carries out a pair of should the running, wherein all do not send indicating signal if this indicates the state adjustment reaction signal of online circuit to go out this north and south bridge circuit, this correspondence running is that the control central processing unit operates on this dark power save mode; And if this is indicated the reaction signal of online circuit to go out in this north and south bridge circuit and has arbitrary circuit to send indicating signal, this correspondence running is that the control central processing unit operates on this shallow power save mode.
The present invention also provides a kind of control one chipset and a central processing unit to operate on the method for different power save modes, be provided with a south bridge circuit and a north bridge circuit in this chipset, be connected respectively to the online circuit of an indication, and this method includes: when south bridge circuit or this north bridge circuit receive a bus master, can send one first indicating signal respectively and one second indicating signal is indicated online circuit to this; Make this state of indicating online circuit adjust that signal can react this north bridge circuit and whether this south bridge circuit has one of them to send indicating signal; And make this north bridge circuit and this south bridge circuit indicate the state adjustment signal of online circuit to carry out a pair of should the running according to this, wherein all do not send indicating signal if this indicates the state adjustment reaction signal of online circuit to go out this north and south bridge circuit, this correspondence running is that this central processing unit of control operates on this dark power save mode; And if this is indicated the reaction signal of online circuit to go out in this north and south bridge circuit and has arbitrary circuit to send indicating signal, this correspondence running is that this central processing unit of control operates on this shallow power save mode.
In preferred embodiment of the present invention, be the online circuit of indication to be set between the bridge circuit of north and south to open being disposed at of drain electrode, the north and south bridge circuit can both indicate online circuit to send indicating signal to this when the service bus master control requires, and whether the configuration of opening drain electrode makes signal on the online circuit of indication can react the north and south bridge circuit to have one of them to send indicating signal.And south bridge circuit just can be judged whether north bridge circuit has been finished according to the signal of the online circuit of indication and spies upon running, otherwise north bridge circuit also can be learnt south emigrant's circuit whether new bus master requirement is arranged, and during the bridge circuit associated treatment bus master of north and south, central processing unit only need operate on state C2, need not return to the state that state C0 changes signal IO22, also therefore the present invention can significantly reduce the power consumption of central processing unit during bus master.
The process that north and south of the present invention bridge circuit service bus master control requires can be described below.When central processing unit operates on state C3, if there is the peripheral unit of south bridge circuit to require bus master and want the access system storer, south bridge circuit can make state signal SLP# be transferred to numeral 1 and be made central processing unit revert to state C2 by numeral 0, and on the online circuit of indication, send indicating signal, to determine that north bridge circuit is waken up state C2 or more than the C2, makes it return back to the state that can support to spy upon running.When north bridge circuit can be spied upon running by the time, it was that peripheral unit provides the service of spying upon that south bridge circuit can begin with signal UPCMD prompting north bridge circuit.Provide the service spied upon at north bridge circuit, carry out bus master during, north bridge circuit also can continue to send indicating signal in indication on the online circuit.If peripheral unit is data will be write to system storage, south bridge circuit with the data transmission of peripheral unit to north bridge circuit, can stop to send indicating signal, this moment, the indicating signal that sends of north bridge circuit can make signal on the online circuit of indication react constantly to still have circuit (being north bridge circuit) carrying out the relevant running of bus master.By the time north bridge circuit is finished all services that bus master is required, north bridge circuit will stop to send indicating signal, and indicate the signal on the online circuit also can to change thereupon, reflect the north and south bridge circuit and all finished the related service of bus master requirement and stopped sending indicating signal.In view of the above, south bridge circuit just can make central processing unit return to state C3 once again.
On the other hand, if peripheral unit is the data of wanting in the reading system storer, then north bridge circuit finish spy upon operate and with the system storage data transmission to south bridge circuit, can stop to send indicating signal.The data transmission that north bridge circuit is transmitted Deng south bridge circuit is to peripheral unit, and south bridge circuit will stop to send indicating signal.Indicate signal on the online circuit can reflect the north and south bridge circuit and all finish the related service that bus master requires and stop to send indicating signal, so south bridge circuit just can make central processing unit return to state C3.
Because the north and south bridge circuit among the present invention can be by the bus master requirement of indicating online circuit to come the Coordination Treatment peripheral unit, so during the service bus master control requires, central processing unit does not need to get back to the state that state C0 changes buffer IO22, only need get back to the running of spying upon that state C2 supports north bridge circuit; Also therefore, the present invention can significantly save the power consumption of central processing unit.
Description of drawings
Fig. 1 is the function block schematic diagram of computer system of the present invention.
The synoptic diagram of each related signal waveform sequential when Fig. 2, Fig. 4 are Fig. 1 computer system operation.
The schematic flow sheet of Fig. 3 for operating among Fig. 2.
Fig. 5 is the power consumption synoptic diagram of computer system among Fig. 1.
The reference numeral explanation
10 computer systems, 12 central processing units
14 north bridge circuits, 16 south bridge circuits
18 storeies, 20 graphics acceleration cards
22 peripheral units 24 are spied upon module
26A-26B indicating module 28 control modules
The online circuit 102-116 step of 30 indications
Ta0-ta7, tb0-tb7, tc0-tc5 time point
Op1-op2 exports into end V, G Dc bias
The Q1-Q2 transistor
WRDY, RRDY, UPCMD, SLP, BMI_SB, BMI_NB, BMI signal
Embodiment
Please refer to Fig. 1.Fig. 1 is the function block schematic diagram of computer system 10 of the present invention.The north bridge circuit 14 that be provided with central processing unit 12 in the computer system 10, forms a chipset and south bridge circuit 16, as storer 18 (for example being dynamic RAM), graphics acceleration card 20 and other the peripheral unit 22 of system storage.Central processing unit 12 is used for data processing, the data operation of host computer system 10, the exchanges data between south bridge circuit 16,14 management central processing units 12 of north bridge circuit, storer 18 and other each peripheral unit.Wherein, graphics acceleration card 20 can be considered the peripheral unit of north bridge circuit 14, is used for process graphical data, and the operation situation of computer system 10 can be shown in the mode of graphic picture; South bridge circuit 16 can be connected in one or more peripheral units (among Fig. 1 with peripheral unit 22 as representative), and this peripheral device can be a Winchester disk drive, CD-ROM drive, adapter miscellaneous (similarly being sound card, network card) or input medias such as keyboard, mouse.
In order to realize the present invention, be provided with one in the north bridge circuit 14 and spy upon a module 24 and an indicating module 26A, and be provided with a control module 28 and another indicating module 26B in the south bridge circuit 16.In preferred embodiment of the present invention, 14 of south bridge circuit 16 and north bridge circuits can be provided with one open the drain electrode framework (open-drained configuration) the online circuit 30 of indication.As shown in Figure 1, indicating module 26A in the north bridge circuit 14 can open drain electrode framework circuit via one, for example goes into end (IO pad) op1 by the grid of a transistor (can be n-type metal oxide semiconductor transistor) Q1, drain electrode in the output of north bridge circuit and is electrically connected in the online circuit 30 of indication; Similarly, indicating module 26B in the south bridge circuit 16 also can open drain electrode framework circuit via another, for example goes into to hold op2 to be electrically connected to indication online circuit 30 (wherein V, G are the DC voltage of bias voltage) by the grid of a transistor Q2, drain electrode in the output of south bridge circuit.When north bridge circuit 14 when carrying out the related service that bus master requires, indicating module 26A in the north bridge circuit 14 will driving transistors Q1 grid make its conducting, be equivalent on the online circuit 30 of indication, send the north bridge indicating signal BMI_NB# (# represents anti-phase BMI_NB) of (assert) numeral 0.In like manner, when south bridge circuit 16 when carrying out the related service that bus master requires, the indicating module 26B of south bridge circuit 16 then can driving transistors Q2 grid make its conducting, be equivalent on the online circuit 30 of indication, send the south bridge indicating signal BMI_SB# of a numeral 0.Owing to open the configuration of drain electrode framework circuit, indicate signal BMI# on the online circuit 30 just to be equivalent to the result of both logical operations of indicating signal BMI_SB#, BMI_NB# (for example OR computing), whether indicating module 26B, the 26A that can reflect in the bridge circuit of north and south have one of them to send indicating signal (being signal BMI_SB# or BMI_NB#).And this signal BMI# just can be considered state adjustment signal.So, the north and south bridge circuit just can indicate online circuit 30 to coordinate mutually by this, for example make north bridge circuit carry out state variation (for example becoming C2) by C3, and need not make central processing unit get back to the state that state C0 changes buffer IO22, as long as the north and south bridge circuit makes bus master require not influenced by buffer IO22 by internal mechanism, allow north bridge circuit proceed to spy upon running, and the control module 28 in the south bridge circuit 16 also just can control the power save mode (for example getting back to state C2) that central processing unit 12 is operated with signal SLP# and STPCLK# (not showing at this) according to signal BMI#.When the online circuit 30 of indication did not all send indicating signal with signal BMI# reaction north and south bridge circuit, control module 28 will make central processing unit 12 dormancy in state C3; One of them is arranged also when sending indicating signal when the online circuit 30 of indication reflects the north and south bridge circuit, control module 28 will make central processing unit 12 operate on state C2.In addition,, when carrying out the relevant treatment of bus master, spy upon module 24 and can spy upon at north bridge circuit 14 central processing unit 12 of state C2.
Situation when further specifying the invention process please continue with reference to figure 2 (and in the lump with reference to figure 1); Fig. 2 is among Fig. 1 during computer system operation, the synoptic diagram of each related signal waveform sequential; The transverse axis of Fig. 2 is the time.As shown in Figure 2, supposed before time point ta0 that central processing unit 12 dormancy are in state C3.Arrived time point ta0, peripheral unit 22 requires south bridge circuit 16 to carry out a bus master service that writes, and data be write to storer 18.In order to carry out bus master, the control module 28 of south bridge circuit 16 will begin signal SLP# is changed to numeral 1 by numeral 0 after time point ta0, make central processing unit 12 switch to state C2 by state C3, with the service of spying upon of supporting that north bridge circuit 14 will carry out after a while at time point ta0.At time point ta1, indicating module 26B in the south bridge circuit 16 also begins driving transistors Q2, sends the south bridge indicating signal BMI_SB# (for example using the voltage of Vcc and the ground terminal voltage of the numeral 1 corresponding GND of use in this numeral 0) of numeral 0 on the online circuit 30 in indication; And the signal BMI# on the online circuit 30 of the indication of opening drain electrode equally also just changes numeral 0 into, and reflecting has circuit to begin to send indicating signal.Simultaneously after online circuit 30 receives south bridge indicating signal BMI_SB# by indication, will make north bridge circuit 14 enter more shallow power save mode (similarly being state C2), so its inner phase-locked loop resume operation just can provide and spies upon running and serve at time point ta1.On the other hand, north bridge circuit can provide a specific state signal (not being shown in Fig. 1), south bridge circuit 16 make south bridge circuit 16 can know that north bridge circuit will open the phase-locked loop again and just can provide service, so can wait for that one period long time delay is to determine that north bridge circuit 14 can service bus master control requirement.Certainly, under the possible situation of another kind, north bridge circuit 14 just has been in the state that can serve when time point ta0, and its phase-locked loop and operates with specific its phase-locked loop of state reaction signal in running; So after time point ta1, south bridge circuit 16 will be learnt that as long as wait for one period short time delay, north bridge circuit 14 just can provide service by this particular state signal.
When time point ta2, south bridge circuit 16 has determined that north bridge circuit 14 can provide the related service (comprising the service spied upon, data transmission or the like) of bus master, south bridge circuit 16 will be with the 14 beginning service bus master control requirements of numeral 1 signal UPCMD notice north bridge circuit, and the data transmission that peripheral unit 22 will be write to storer 18 is to north bridge circuit 14; In Fig. 2, signal WR level is the part of numeral 1, the period that transmission is carried out with regard to representative data.Arrived time point ta3, north bridge circuit 14 also sends north bridge indicating signal BMI_NB# on the online circuit 30 of indication, represents north bridge circuit 14 beginning service bus master control requirements.With data transmission to north bridge circuit 14, south bridge circuit 16 sends numeral 1 signal WRDY representative transmission at time point ta4 and finishes, and stops to send south bridge indicating signal BMI_SB# at time point ta5; So far, in the necessary running that the service bus master control requires, south bridge circuit 16 has been finished its required part of carrying out.But, as shown in Figure 2, at time point ta5, north bridge circuit 14 is not also finished the service that bus master is required, thus also continue to send north bridge indicating signal BMI_NB#, and indicate the signal BMI# on the online circuit 30 also just to be maintained at numeral 0 jointly.Arrived time point ta6, north bridge circuit 14 is finished service that bus master is required (comprise writing data into memory 18 and spy upon or the like), just can stop to send the north bridge indicating signal BMI_NB# of numeral 0, north bridge indicating signal BMI_NB# is replied be digital 1.Because the north and south bridge circuit all no longer sends indicating signal, indicate the signal BMI# on the online circuit 30 also to be numeral 1 with regard to replying.According to the conversion of signal BMI# at time point ta6, the control module 28 in the south bridge circuit 16 will switch to numeral 0 with signal SLP# by numeral 1 at time point ta7, makes central processing unit 12 by the state C2 C3 that gets the hang of once again.So just finished the service that the north and south bridge circuit requires the bus master that writes.
On the other hand, suppose that the peripheral unit 22 of south bridge circuit proposes a bus master requirement of reading, and the data in the storer 18 be read in to peripheral unit at time point tb0.So at time point tb0, south bridge circuit 16 makes signal SLP# change numeral 1 into by numeral 0 once again, makes central processing unit 12 return to state C2 by state C3, with the service of spying upon of supporting that north bridge circuit 14 will carry out after a while.At time point tb1, south bridge circuit 16 also begins to send to the online circuit 30 of indication the south bridge indicating signal BMI_SB# of numeral 0, represents south bridge circuit 16 beginning service bus master control requirements.Be similar to the running between the time point ta1 to ta2, north bridge circuit 14 can begin the service of preparing at time point tb1, but and south bridge circuit 16 can be known according to north bridge circuit 14 specific state signals and will wait time delay how long so that north bridge circuit 14 returns to service state; But after returning to service state, north bridge circuit 14 can be notified south bridge circuit 16 once again.
At time point tb2, but north bridge circuit 14 has returned to service state, and south bridge circuit 16 is just with the 14 beginning service bus master control requirements of the 1 signal UPCMD of the numeral between time point tb2, tb3 notice north bridge circuit.After time point tb3, north bridge circuit 14 beginning service bus master control requirements similarly are to spy upon, south bridge circuit 16 is read and transferred to the data in the storer 18; Carry out these runnings during, north bridge circuit 14 can continue to send the north bridge indicating signal BMI_NB# of numeral 0.At time point tb4, north bridge circuit 14 is notified south bridge circuit 16 with the signal RRDY of numeral 1, and stops to send north bridge indicating signal BMI_NB# at time point tb5, and representative is in bus master requires, and north bridge circuit 14 has been finished its required running of carrying out and service.But, the data transmission that south bridge circuit 16 also will transmit north bridge circuit 14 is to peripheral unit, so the service that 16 pairs of bus masters of south bridge circuit require can be extended to time point tb6, the numeral 0 south bridge indicating signal BMI_SB# that south bridge circuit 16 sends also can continue to be issued to tb6.Along with north bridge circuit 14, south bridge circuit 16 successively stop to send indicating signal at time point tb5, tb6, indicate the signal BMI# of online circuit 30 also can get back to numeral 1 by numeral 0 at time point tb6.According to the variation of signal BMI# at time point tb6, south bridge circuit 16 just can change signal SLP# into numeral 0 by numeral 1 at time point tb7, makes central processing unit 12 get back to C3 by state C2, finishes the service that bus master is required.
Above-mentioned control flow is summarized in Fig. 3; Please refer to Fig. 3, Fig. 3 is chipset of the present invention carries out the bus master service for the south bridge circuit periphery process flow diagram.Flow process among Fig. 3 includes the following step:
Step 102: in the time of at the beginning, central processing unit 12 operates on state C3.
Step 104: the peripheral unit of south bridge circuit 16 requires to carry out bus master.
Step 106A: for carrying out bus master, south bridge circuit 16 sends the signal SLP# of numeral 1, makes central processing unit return back to state C2 by state C3.
Step 106B: south bridge circuit 16 sends the south bridge indicating signal BMI_SB# of numeral 0, makes signal BMI# also become numeral 0, is equivalent to send on the online circuit 30 of indication the signal BMI# of numeral 0.
Step 108: according to signal BMI#, north bridge circuit 14 prepares to carry out the related service of bus master.As previously mentioned, north bridge circuit 14 restarts its inner phase-locked loop possibly, and to return to service available state, north bridge circuit 14 reinforms south bridge circuit 16 then, agrees to carry out the bus master service.
Step 110: when central processing unit 12 continued to operate on state C2, north bridge circuit 14 carried out the required running of bus master, comprises the data access to storer 18, and central processing unit 12 is spied upon.
Step 112: when the north and south bridge circuit was all finished the required operation of carrying out of bus master, the both can send the indicating signal of numeral 1, made the signal BMI# on the online circuit 30 of indication also become numeral 1.
Step 114: according to the variation of signal BMI# in the step 112, south bridge circuit 16 will be reissued the SLP# signal of numeral 0.
Step 116: according to the SLP# signal that south bridge circuit in the step 112 16 sends, central processing unit 12 returns back to state C3 again.
As seen from the above description, the present invention can coordinate the north and south bridge circuit with the online circuit 30 of the indication of opening drain configuration and finish the service that bus master is required together, so do not need the state C0 that central processing unit is returned to highly energy-consuming to set buffer IO22 (ARB_DIS), only need the state C2 that central processing unit is switched to low power consuming just can support north and south bridge circuit service bus master control requirement, reduce the energy of central processing unit required consumption during handling the bus master requirement.
Except the bus master service was provided for the south bridge circuit peripheral unit, the online circuit 30 of indication of the present invention also can propose to coordinate when bus master requires the running of north and south bridge circuit at the north bridge circuit peripheral unit.About this situation, please refer to Fig. 4 (and in the lump with reference to figure 1); Fig. 4 is a computer system 10 when the north bridge circuit peripheral unit proposes bus master and requires, the synoptic diagram of related signal waveform sequential; The transverse axis of Fig. 4 is the time.Supposed that before time point tc0 central processing unit 12 dormancy are in state C3.Arrived time point tc0, the peripheral unit of north bridge circuit 14 (for example being graphics acceleration card 20) proposes the bus master requirement, and north bridge circuit 14 will send the north bridge indicating signal BMI_NB# of numeral 0 after time point tc0; Jointly, indicate the signal BMI# on the online circuit 30 also can change numeral 0 into, representative has a circuit to send indicating signal.According to the change of signal BMI#, south bridge circuit 16 will begin to transfer signal SLP# to numeral 1 by numeral 0 at time point tc1, makes central processing unit 12 return back to state C2 by state C3, prepares to support spying upon of north bridge circuit 14.Central processing unit 12 is waken up to state C2, and south bridge circuit 16 can begin service bus master control requirement with the signal UPCMD notice north bridge circuit 14 of numeral 1 at time point tc2.Between time point tc3, tc4, north bridge circuit 14 just can be served the bus master requirement that its peripheral unit proposes, and spies upon and to data access of storer 18 or the like.Arrived time point tc4, north bridge circuit 14 finishes service, stop to send north bridge indicating signal BMI_NB#, and signal BMI# also returns back to numerical digit 1 at time point tc4.According to the transformation of signal BMI#, south bridge circuit 16 just can switch to numeral 0 with signal SLP# at time point tc5, makes central processing unit 12 get back to C3 by state C2.Because it mainly is by the north bridge circuit service that the bus master that proposed of north bridge circuit peripheral unit requires,, can not send digital 0 south bridge indicating signal BMI_SB# so south bridge circuit 16 all needn't service bus master control requirement between time point tc0 to tc5 yet.Yet, the switching of central processing unit 12 between state C2/C3 still will be controlled by the signal SLP# of south bridge circuit 16, so the online circuit 30 of indication of the present invention still can be brought into play the function of coordinating north and south bridge circuit running, do not need to allow central processing unit 12 get back to state C0 yet and could support to handle the bus master requirement.
Please refer to Fig. 5.Fig. 5 is the synoptic diagram of computer system 10 power consumption situations of the present invention; The transverse axis of Fig. 5 is the time, and the longitudinal axis is the size of power consumption.As shown in Figure 5, the present invention is that the state with central processing unit C3/C2/C3 switches and comes the supporting chip group to handle bus master, and it is lower to consume energy.That compares is following, and known technology need switch with the C3/C0/C3 state of central processing unit handles bus master, and its power consumption will significantly increase.
In summary, in preferred embodiment of the present invention, the online circuit of drain electrode indication of opening of can utilization structure simplifying is coordinated the north and south bridge circuit and is served the bus master requirement that various peripheral units propose, so during the service bus master control requires, just do not need central processing unit has been waken up to the C0 state of highly energy-consuming.When computer system of the present invention requires in the bus master of service peripheral unit, central processing unit only need return back to state C2, state C0 under the known technology, the power consumption of central processing unit can be reduced to 1/5 to 1/10 in the present invention, so can significantly reduce the power consumption of central processing unit, also can reduce the heat production of central processing unit.In some computer system (as notebook computer), be the electricity consumption that comes supplied computer system with battery, if adopt technology of the present invention, then can increase the durable degree of battery electric power.In fact, under the framework of modem computer systems, having many runnings not need that central processing unit is maintained at state C0 just can carry out, similarly be when the user utilize computer system listen to music, when watching dynamic image, only need to carry out these multimedia functions, and allow the central processing unit dormancy in state C3 by sound card, graphics acceleration card.If central processing unit will be waken up to state C0 ability service bus master control requirement as known technology, central processing unit certainly will will switch between state C3/C0 continually, increases power consumption on foot.Relatively, the present invention just can save a large amount of electric power.In Fig. 1, the function of each module in the north and south bridge circuit 14,16 can use firmware or hardware to realize widely.For instance, the function of spying upon module 24 and indicating module 26A in the north bridge circuit 14 can use the controller of same sequencing to be realized.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (15)
1. a tunable north and south bridge circuit operates on the chipset of different power save modes, and it includes:
One north bridge circuit, it has a north bridge exports into end, when this north bridge circuit receives a bus master of being sent by a peripheral unit that is connected to this north bridge circuit, exports into end by this north bridge and to send one first indicating signal;
One south bridge circuit, it has a south bridge exports into end, when this south bridge circuit receives a bus master of being sent by a peripheral unit that is connected to this south bridge circuit, exports into end by this south bridge and to send one second indicating signal; And
The online circuit of one indication, export into this first indicating signal of end and this south bridge according to this north bridge and to export this second indicating signal into end, carry out a logical operation and produce state adjustment signal, this state adjustment signal controls this north bridge circuit and this south bridge circuit carries out a pair of should the running, wherein all do not send indicating signal if this indicates the state adjustment reaction signal of online circuit to go out this north and south bridge circuit, this correspondence running is that the control central processing unit operates on this dark power save mode; And if this is indicated the reaction signal of online circuit to go out in this north and south bridge circuit and has arbitrary circuit to send indicating signal, this correspondence running is that the control central processing unit operates on this shallow power save mode.
2. chipset as claimed in claim 1, wherein this north bridge circuit comprises that spying upon module, one first indicating module and one first opens drain electrode framework circuit, this first indicating module connects to be spied upon module and first opens the framework circuit that drains with this, this first is opened drain electrode framework circuit and is connected to this north bridge and exports into end, this south bridge circuit comprises that a control module, one second indicating module and one second open drain electrode framework circuit, this second indicating module connects this control module and this second and opens drain electrode framework circuit, and this second is opened drain electrode framework circuit and be connected to this south bridge and export into end.
3. chipset as claimed in claim 2, wherein this first to open drain electrode framework circuit be to be made of a transistor, this transistorized grid is by this first indicating module control, drain electrode is connected to a high voltage and this north bridge is exported into end, source electrode is connected to a low-voltage.
4. chipset as claimed in claim 2, wherein this second to open the drain electrode framework be to be made of a transistor, this transistorized grid is by the control of this second indicating module, drain electrode is connected to a high voltage and this south bridge is exported into end, source electrode is connected to a low-voltage.
5. chipset as claimed in claim 1, wherein this south bridge circuit is when receiving a bus master of being sent by a peripheral unit that is connected to this south bridge circuit, change this south bridge and export a logic level, and a logic level that makes this state adjust signal changes into second indicating signal of end.
6. chipset as claimed in claim 5, wherein when this state was adjusted the logic level change of signal, this north bridge circuit produces this correspondence running made north bridge circuit switch to a shallow power save mode by a dark power save mode.
7. chipset as claimed in claim 6, wherein after this north bridge circuit returns to this shallow power save mode, this spies upon module can carry out spying upon running to this central processing unit, and carry out during this spies upon running at this north bridge circuit, this north bridge is exported a logic level that changes this first indicating signal into end.
8. chipset as claimed in claim 5, wherein when the logic level of this second indicating signal changed, this south bridge circuit produces this reaction running made a central processing unit switch to a shallow power save mode by a dark power save mode.
9. chipset as claimed in claim 1, wherein when this north bridge circuit receives a bus master of being sent by a peripheral unit that is connected to this north bridge circuit, change this north bridge and export a logic level into first indicating signal of end, a logic level that makes this state adjust signal changes.
10. chipset as claimed in claim 9, wherein when this state was adjusted the logic level change of signal, this south bridge circuit produced this correspondence running, makes central processing unit switch to a shallow power save mode by a dark power save mode.
11. a control one chipset and a central processing unit operate on the method for different power save modes, are provided with a south bridge circuit and a north bridge circuit in this chipset, be connected respectively to one and indicate online circuit, and this method includes:
When south bridge circuit or this north bridge circuit receive a bus master, can send one first indicating signal respectively and one second indicating signal is indicated online circuit to this;
Make this state of indicating online circuit adjust that signal can react this north bridge circuit and whether this south bridge circuit has one of them to send indicating signal; And
Make this north bridge circuit and this south bridge circuit indicate the state of online circuit to adjust signal and carry out a pair of should the running according to this, wherein all do not send indicating signal if this indicates the state adjustment reaction signal of online circuit to go out this north and south bridge circuit, this correspondence running is that this central processing unit of control operates on this dark power save mode; And if this is indicated the reaction signal of online circuit to go out in this north and south bridge circuit and has arbitrary circuit to send indicating signal, this correspondence running is that this central processing unit of control operates on this shallow power save mode.
12. method as claimed in claim 11, wherein this state adjustment signal is to be produced through a logical operation by this first indicating signal and this second indicating signal.
13. method as claimed in claim 11, it also includes:
When making this central processing unit operate on this shallow power save mode, this central processing unit is carried out spying upon running with this north bridge circuit; And
Carry out making this north bridge circuit continue to send this first indicating signal during this spies upon running at this north bridge circuit.
14. method as claimed in claim 11, wherein this south bridge circuit also is electrically connected at least one peripheral unit, and this north bridge circuit also is electrically connected in a storer, and it also includes:
When this peripheral unit will write to this storer with data, make this south bridge circuit continue to send this second indicating signal; And
When this south bridge circuit with data transmission to this north bridge circuit, make this south bridge circuit stop to send this second indicating signal.
15. method as claimed in claim 14, it also includes:
When this peripheral unit will read data in this storer, make this south bridge circuit continue to send second indicating signal; And
When this north bridge circuit with data transmission to this south bridge circuit, make this north bridge circuit stop to send this second indicating signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410082586 CN1265264C (en) | 2004-09-21 | 2004-09-21 | Circuit andm ethod for coordinating south-north bridge circuit and CPU at different energy saving state |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410082586 CN1265264C (en) | 2004-09-21 | 2004-09-21 | Circuit andm ethod for coordinating south-north bridge circuit and CPU at different energy saving state |
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| CN1588274A CN1588274A (en) | 2005-03-02 |
| CN1265264C true CN1265264C (en) | 2006-07-19 |
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| CN100458662C (en) * | 2005-04-22 | 2009-02-04 | 精拓科技股份有限公司 | Efficiency execution device and method for dynamic load-adjusting device |
| CN102214132B (en) * | 2011-05-16 | 2014-07-02 | 曙光信息产业股份有限公司 | Method and device for debugging Loongson central processing unit (CPU), south bridge chip and north bridge chip |
| CN104932654B (en) * | 2015-01-09 | 2018-04-13 | 大唐微电子技术有限公司 | A kind of clock control method and device |
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