CN1263149C - Non-volatile memory and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a nonvolatile memory element and a manufacturing method thereof. The nonvolatile memory can be a silicon nitride memory element, and an ONO layer is arranged below at least one character line. Firstly, the ONO layer is formed on a base; secondly, a patterned photoresistive layer is formed on the ONO layer; thirdly, the photoresistive layer is used as an embedded mask to form at lease one bit line in the base; fourthly, a material layer is formed on the base, and the material layer is flattened until the photoresistive layer is exposed; fifthly, the photoresistive layer is removed, and a high molecular material layer is formed on the surface of the material layer; sixthly, the high molecular material layer is used as an etching mask to define silicon oxide and silicon nitride at the top of the ONO layer; finally, the material layer and the high molecular material layer are removed.

Description

Nonvolatile memory and manufacture method thereof

Technical field

The invention relates to a kind of non-volatile memory device and manufacture method thereof, and particularly relevant for a kind of non-volatile memory device and manufacture method thereof with double places memory cell.

Background technology

The nonvolatile semiconductor memory element is in order to the stored routine data, even the power supply supply disappears, stored data still can not disappear.And read-only memory (ROM) is a kind of nonvolatile memory wherein, and it is used in the electronic equipment usually, for example little processing digital device and handheld electronic apparatus, for example mobile phone.

General read-only memory element is arranged to a plurality of memory cell arrays, and each memory cell comprises a transistor.Wherein, typical transistor comprises a metal oxide semiconductor field effect transistor (MOSFET), itself and be listed in two bit lines and a word line between.In addition, be kept in the data bit in these memory cell transistors or the physics or characteristic electron that is stored in each memory cell for a long time of encoding (up to painstakingly erasing).Therefore, the non-volatile character of read-only memory can be described as the data that are stored in the memory component and only can be read.

Present a kind of non-volatile memory device is that silicon nitride memory (NROM) is in development.The floating grid memory that the silicon nitride memory was developed in the past in 30 years provides more advantage, but wherein the floating grid memory for example be can erase and the read-only memory (EPROM) of program, flash memory (Flash) but and can electricity remove and the read-only memory (EEPROM) of program, wherein the floating grid memory be with Charge Storage in a conduction floating grid.

The silicon nitride memory cell comprises two memory cell, its with Charge Storage in silicon monoxide-silicon-nitride and silicon oxide (ONO) dielectric layer.This silicon nitride memory cell comprises a n type passage MOSFET element, and wherein silicon nitride layer is used as the capture material layer between a top and bottom oxide layer.And this ONO structure replaces the gate dielectric layer in the floating grid element, and the thickness of oxide layer of its top and bottom must be greater than 50 dusts, and the infringement because of any oxide layer causes electronics to wear then in programmed process to avoid.

The silicon nitride memory can be added in the standard CMOS process, and wherein the formation step of ONO layer is arranged after the isolation structure on the scene but before the gate oxidation step.And the step that adds the silicon nitride memory is very little to the influence of CMOS process heat budget usually.In addition, the mode sequencing that the silicon nitride memory cell is injected with channel hot electron (CHE) usually, and promote hot hole (TEHH) injection mode and erase to wear then.And the partial charge that is operating as of silicon nitride memory cell stores, and it can make the electric charge of catching only be retained in decanting point.Therefore, the not enough problem in single position can be improved in the experience of past floating grid technology, and is not influencing under the element function, can also improve the density of element and promote the microminiaturization of element.

The silicon nitride memory can provide many important advantages than the floating grid memory.One, in the silicon nitride memory, position size and crystallite dimension can than the floating grid memory little 3 times or more than.In addition, the silicon nitride memory component only need be less than the light shield technology in 6 to 8 roads, so its process complexity is lower, and its easy and long-pending bodyization of cmos element.Moreover because the start voltage of erasing of silicon nitride memory is low, so the silicon nitride memory is suitable for being used in the low-voltage product.Yet, the silicon nitride memory component but has a problem, the problem that horizontal both hole and electron migration is arranged between two silicon nitride memory cell exactly easily, particularly after portion of hot technology, the horizontal both hole and electron of this kind moves the easier generation of problem of (claiming again to disturb).

Summary of the invention

The present invention is relevant for a kind of nonvolatile memory and manufacture method thereof, and particularly relevant for the manufacture method of a kind of silicon nitride memory component and improvement thereof.The process of this improvement can reduce electron transfer and/or the hole migration between two in the silicon nitride memory cell, and this electron transfer and/or hole migration are just disturbed, and this interference can occur in after the portion of hot technology especially.

According to purpose of the present invention, the present invention cuts the silicon nitride layer of ONO stack architecture in each memory cell, can produce the problem of disturbing to eliminate in the above-mentioned memory cell between two.And method of the present invention can overcome the restriction of lithography process and the ONO stack architecture is patterned into 0.15 micron size.Utilize method of the present invention can use ultraviolet wavelength with patterning photoresist layer and make this element, and the size of component that can make formation is less than ultraviolet wavelength.

According to the present invention's purpose, a kind of method that forms at least one non-volatile memory device comprises provides a substrate, wherein has been formed with the photoresist layer of catching a layer and a patterning in the substrate; Utilizing this photoresist layer is that an implantation mask is to form at least one bit line; Between the photoresist layer, form a material layer; Remove the photoresist layer; On the surface of material layer, form a polymer material layer; And utilize this polymer material layer to catch layer to define this as an etching mask.

According to another object of the present invention, a kind of method of formation one non-volatile memory device is included in the substrate and forms one and catch layer; Catching the photoresist layer that forms a patterning on the layer; Utilizing this photoresist layer is that an implantation mask carries out an ion implantation step to form at least one bit line; On photoresist layer and the surface of catching layer, form a material layer; This material layer of planarization is to expose the photoresist layer; Remove the photoresist layer; On the surface of material layer, form a polymer material layer; This catches layer as an etching mask patternsization to utilize this polymer material layer, catches layer to form at least one strip; Remove material layer and polymer material layer; Catch at least one word line of formation on the layer at least one strip.

This catches layer and comprises one first oxide layer, a silicon nitride layer and one second oxide layer, and wherein first oxide layer, silicon nitride layer and second oxide layer constitute the ONO stack architecture.This ONO stack architecture can be only patterning second oxide layer and silicon nitride layer, is not patterned and keep first oxide layer.In addition, material layer comprises a bottom anti-reflection layer (BARC).In addition, the method for formation polymer material layer is formed with a plasma enhanced chemical vapor deposition method (PECVD) on material surface.And the method for smoothing material layer comprises and carries out an etch back process.In addition, at least one bit line comprises multiple bit lines, and at least one strip is caught layer and comprised that many strips catch layer, and at least one word line comprises many word lines.

According to a further object of the present invention, a kind of method that forms a non-volatile memory device in the semiconductor substrate comprises provides the semiconductor substrate; On the semiconductor-based end, form one and catch layer; With a photoresist layer patternization to catch on the layer photoresist layer that forms a plurality of strips; Implanting ions in the semiconductor-based end optionally is to form multiple bit lines; At the photoresist layer of patterning and catch on the surface of layer and form a material layer; This material layer of planarization is to expose the photoresist layer; Remove the photoresist layer; On the surface of material layer, form a polymer material layer; Etch-back is partly caught layer and is caught layer to form a plurality of strips; Remove material layer and polymer material layer; And form many word lines.

After this ion implantation step, can also change into a plurality of dual strips and catch layer catching layer pattern.This catches layer and comprises one first oxide layer, a silicon nitride layer and one second oxide layer, to constitute an ONO stack architecture, wherein may consume the part silicon nitride layer when growing up second oxide layer in above-mentioned method.In addition, polymer material layer is formed with a plasma enhanced chemical vapor deposition method (PECVD), and formed polymer material layer is to be used for being positioned at rete under it as an etching mask with protection in etch process.

According to purpose of the present invention, a kind of non-volatile memory device comprises the semiconductor substrate, has implanted multiple bit lines at wherein semiconductor-based the end.This non-volatile memory device comprises a plurality ofly catches block structure and is configured in many word lines of catching on the block structure corresponding to a plurality of.The block structure of catching between two bit lines is separated from each other in the direction of word line, and each catches block structure corresponding single position in a memory cell.And these a plurality of block structures of catching can comprise an oxide layer and a silicon nitride layer.

Description of drawings

Fig. 1 is the schematic diagram of the silicon nitride memory semiconductor element after word line and bit line form;

Fig. 2 is the generalized section of silicon nitride memory semiconductor element in a middle process step;

Fig. 3 is the generalized section after the ion implantation step among Fig. 2;

Fig. 4 is the generalized section that adds a material layer among Fig. 3;

Fig. 5 is the generalized section after the planarisation step among Fig. 4;

Fig. 6 is the generalized section that removes among Fig. 5 behind all photoresist layers;

Fig. 7 is the generalized section that adds a polymer material layer among Fig. 6;

Fig. 8 is the generalized section after the etch process step among Fig. 7;

Fig. 9 removes polymer material layer and material layer generalized section afterwards among Fig. 8;

Figure 10 is the stereogram with the silicon nitride memory of Fig. 9 same process step;

Figure 11 is the generalized section of silicon nitride memory component in a middle process step, and its tangent plane with Fig. 2 to Fig. 9 is vertical;

Figure 12 is the generalized section of silicon nitride memory component after an etch process step of Figure 11;

Figure 13 is the stereogram with the silicon nitride memory of Figure 12 same process step;

Figure 14 is the generalized section of silicon nitride memory component after an etch process step of Fig. 3;

Figure 15 is the generalized section of another kind of silicon nitride memory component in a middle process step;

Figure 16 is the stereogram with the silicon nitride memory of Figure 15 same process step; And

Figure 17 is that the silicon nitride memory component of Figure 16 forms word line stereogram afterwards.

21: bit line

23,62: word line

The section of 25:A-A '

The section of 27:B-B '

30: the first oxide layers

32: silicon nitride layer

34: the second oxide layers

36: substrate

The 38:ONO storehouse

40: the photoresist layer

43: implanting ions

45: material layer

47: polymer material layer

49: distance b

51: apart from a

54: memory cell

56,58: the position

60: the ON layer of strip

The 65:ON block structure

Embodiment

In the icon of present embodiment, same or analogous reference number is meant identical or similar part.And icon is all schematic diagram, and it is not an actual size.At this for convenience and clearly demonstrate, disclosed direct project, for example top, bottom, the left side, the right, up, down, on, under, beneath, front and back, be the explanation that illustrates according to icon.And directly project is not to constitute restriction of the present invention.

Though in the present embodiment with special icon to describe it in detail, be not in order to limit the present invention.Below detailed description, though be a preferred embodiment, without departing from the spirit and scope of the present invention, when doing a little change and modification.The operator who for example is familiar with the NROM element can use it for the replacement non-volatile memory device, for example floating grid technology such as EPROM, flash memory and EEPROM.

Processing step described herein or structure are not that a complete flow process is to make the NROM memory component.The present invention can knownly combine at the ic manufacturing technology that uses with many, and generally also is included in this at the processing step of carrying out.

Please refer to Fig. 1, its be multiple bit lines 21 and with many word lines 23 of multiple bit lines 21 arranged perpendicular.And bit line 21 can be produced in the semiconductor substrate (silicon of doping) with word line 23, and it is made and be produced on the mutually same wafer with cmos element along cmos element usually.The making of silicon nitride memory (NROM) memory cell can be in order to use a standard CMOS process, and it comprises an isolation technology and ion doping step.

In the part of A-A ' tangent line 25, the direction of its extension is the position at vertical bit line 21 and A-A ' tangent line 25 places and undefined word line 23 arranged, and the part of A-A ' tangent line 25 corresponding to Fig. 2 to Fig. 9 and the 14th with the profile of Figure 15.Same, in the part of B-B ' tangent line 27, also undefinedly there is bit line 21 position at vertical word line 23 of the direction of its extension and B-B ' tangent line 27 places, and the part of B-B ' tangent line 27 corresponding to the 11st with the profile of Figure 12.

Please refer to Fig. 2, one catches layer deposition and/or grows up in a substrate 36, wherein catches layer and preferably comprises one first oxide layer 30, a silicon nitride layer 32 and one second oxide layer 34.Though substrate 36 preferably comprises a silicon base, substrate 36 can also use other known any suitable semiconductor material to replace, and for example germanium nitride (GaN), arsenic germanium (GaAs) wait other material.

The thickness of first oxide layer 30 and second oxide layer 34 must be enough thick, produce electronics with the electronics of avoiding catching between silicon nitride layer 32 and bit line 21 or word line 23 and wear then, the thickness that this situation may occur in first oxide layer 30 and second oxide layer 34 is less than 50 dusts the time.Therefore preferably, the growth of first oxide layer 30 or deposit thickness are about 50 dust to 100 dusts, and the thickness of silicon nitride layer 32 is about 35 dust to 75 dusts, and the thickness of second oxide layer 34 is about 50 dust to 150 dusts.

Be not that mode with deposition is formed on the silicon nitride layer 32 if second oxide layer 34 is grown up on silicon nitride layer 32, part silicon nitride layer 32 can be consumed in forming the process of oxide layer, and the speed of its consumption roughly is the silicon nitride that the silica of every formation 2 dusts can consume 1 dust.Therefore, the thickness of silicon nitride layer 32 is 35 dust to 75 dusts preferably, and it is second oxide layer, 34 thickness half.If for example to form the thickness of second oxide layer 34 be 150 dusts to desire, and the thickness of silicon nitride layer 32 is 50 dusts, then the thickness that deposits at the beginning of silicon nitride layer 32 must be 125 dusts (50 dusts+75 dusts).

First oxide layer 30, silicon nitride layer 32 and second oxide layer 34 are defined as ONO storehouse 38.In silicon nitride layer 32, and second oxide layer 34 and first oxide layer 30 act on electrical isolation with charge-trapping in the effect of this ONO storehouse 38.

Afterwards, on ONO storehouse 38, form a photoresist layer 40, wherein, photoresist layer 40 can be a positive photoresist layer or a negative photoresist layer, follow with general lithography process this photoresist layer 40 of patterning, to form the photoresist layer of patterning, the photoresist layer of patterning extends toward the direction of paper, as shown in Figure 2.As known method, at first with a photoresist layer rotary coating on wafer, afterwards wafer is placed in the stepper (little shadow instrument of patterned wafer), afterwards wafer is aimed at a light shield, be exposed to again in the ultraviolet light.The size of this light shield may be only can the cover part wafer, so wafer need go through repeatedly step in stepper, meaning is promptly exposed each part of wafer one by one, is all arrived by ultraviolet photoetching up to whole wafer.Afterwards, wafer is seated in the chemical tank with dissolving by the photoresist layer of ultraviolet photoetching, just can forms patterning photoresist layer 40 afterwards with specific pattern.Utilize known lithography process at this, its exposure wavelength with 248nm exposes, and the crack is about 1300 dust to 3000 dusts between the formed photoresist layer 40.

Please refer to Fig. 3, utilize an ion implantation technology an alloy 43 is implanted in the substrate 36 of exposure, for example arsenic or phosphorus of alloy 43 wherein, and form source electrode and drain electrode or a plurality of bit line 21.This ion implantation step can pass through ONO storehouse 38, so ONO storehouse 38 can provide a surface so that the ion of implanting can not need to implant with the substrate lattice structure of its bottom, therefore can avoid ion to produce passage phenomenon (Ion Channeling).

Please refer to Fig. 4, a material layer 45 is formed on the surface of photoresist layer 40 and ONO storehouse 38.The bottom anti-reflection layer (BARC) that this material layer 45 for example is an organic material.Usually BARC in Patternized technique, be configured in the photoresist layer under, in order to absorb the exposure light that major part penetrates the photoresist layer, so as to reducing reflection indenture, standing wave effect and light scattering situation.Yet in the present invention, the BARC layer is not the usefulness that is used for promoting Patternized technique.This BARC layer is formed on photoresist layer 40 and the ONO storehouse 38, and its thickness is enough thick so that it has a smooth surface, for example the BARC layer extends to photoresist layer 40 top and has a smooth surface, and it does not have bad influence to photoresist layer 40.

Continue it, please refer to Fig. 5, smoothing material layer 45 comes out up to photoresist layer 40, and wherein the method for smoothing material layer 45 for example is to carry out an etch back process.

Please refer to Fig. 6, optionally remove photoresist layer 40, and retain material layer 45.At this, different processing steps can also carry out removing photoresist layer 40, only otherwise can bad influence be arranged to the structure or the composition of material layer 45.This photoresist layer 40 can be by a selectivity wet etch process removing the photoresist layer 40 of a specified quantitative (all), and the material layer 45 that the desire of a specified quantitative can't be kept removes.In the present embodiment, material layer 45 is a BARC layer, and photoresist layer 40 can be by an exposure technology and a developing process to remove it.

Please refer to Fig. 7, on material layer 45 surfaces that expose, form polymer material layer 47.In the present embodiment, the method for formation polymer material layer 47 is to utilize a plasma enhanced chemical vapor deposition method (PECVD).And the method and the device that form polymer material layer 47 can be referred to the application case No.09/978 that files an application October 18 calendar year 2001,546, the application case 10/145 of filing an application on May 13rd, 2002,203 and the application case 10/178,795 of filing an application on June 24th, 2002.In the present embodiment, the material of polymer material layer 47 comprises fluorocarbon, and polymer material layer 47 thickness that are formed at material layer 45 tops are 0 dust to 1000 dust, and polymer material layer 47 thickness that are formed at material layer 45 sides are 500 dust to 1000 dusts.Can change relatively with the thickness that is formed on side though be formed on the thickness at top, it can also be identical thickness.At this, the macromolecular material layer thickness be controlled to be control its have one the distance " b " 49 and greater than the distance " b " 49 one the distance " a " 51.Wherein, distance " a " 51 for example is 1300 dust to 3000 dusts, and distance " b " 49 for example is 300 dust to 1000 dusts.About the formation of polymer material layer 47, can adjust the deposition/rate of etch of the parameter of an etching machine with the control reaction, form polymer material layer 47 with sidewall and top at material layer 45.

Polymer material layer 45 is used for as an etching mask, is removed in the etch-back process of follow-up second oxide layer 34 with silicon nitride layer 32 with the rete of avoiding being arranged in its bottom.The etch-rate ratio of second oxide layer 34 and silicon nitride layer 32 is preferably greater than 25: 1, and the etch-rate ratio of the silicon nitride layer 32 and first oxide layer 30 is preferably greater than 10: 1.As shown in Figure 8, second oxide layer 34 and the silicon nitride layer 32 that are exposed out will be removed in etch process fully, and stay first oxide layer 30 that exposes.

Please refer to Fig. 9, polymer material layer 47 and material layer 45 are removed.This removes step and can utilize the mode of an ashing (Ashing) and/or dissolution with solvents and polymer material layer 47 and material layer 45 removed.And other known suitable clearance technique can also be used for removing polymer material layer 47 and material layer 45.Silicon nitride layer 32 in the ONO storehouse 38 of each memory cell 54 (dotted line) separately forms the position of two separation, as first 56 and second 58.

Therefore, ONO storehouse 38 is patterned to silica-silicon nitride (ON) layer (for example being that strip is caught layer) of a plurality of strips, and it is positioned on first oxide layer 30.Please refer to the stereogram of Figure 10, the ON layer 60 of each strip is positioned at the top of a corresponding bit lines 21 and overlapping with corresponding bit lines 21.Therefore many strip ON layers 60 form and extend in parallel above multiple bit lines 21.

In the profile of Figure 11 NROM, its be among Fig. 1 along the section of B-B ', deposition one polysilicon layer and form many word lines 62 on an already present structure.Formation step about word line 62, comprise the application, patterning of a photoresist and with the development of standard lithographic techniques, and forming the photoresist structure of a plurality of extensions, the photoresist structure of this extension afterwards is used for the etching polysilicon layer and extends grids or word line structure 62 to form many.And word line structure 62 is configured on the corresponding strip ON layer 60, and strip ON layer 60 is to extend with the direction of vertical word line 62.

Please refer to Figure 12, a plurality of strip ON layers 60 are etched into a plurality of ON block structures 65.About this etching step, word line 62 is positioned at rete under it as an etching mask with protection in etching process.Each word line structure 62 correspondence is configured in the top of a plurality of ON block structures 65.

Figure 13 is the stereogram of NROM element among Figure 12.The direction that bit line 21 is extended is perpendicular to word line 62, and each word line and two corresponding bit lines constitute a memory cell, and wherein memory cell comprises first 56 and second 58.And (cutting) that the ON block structure between two bit lines 21 is separated from each other and.

In another embodiment, one ONO storehouse 38 is formed in the substrate 36 (as shown in Figure 2), then on ONO storehouse 38, form a photoresist layer 40, in the substrate 36 that exposes, implant arsenic or phosphorus to form multiple bit lines 21 (as shown in Figure 3) with ionic-implantation afterwards.Continue it, please refer to Figure 14, carry out an etching step to remove part second oxide layer 34 and silicon nitride layer 32.In above-mentioned etching step, can utilize previous described PECVD on the surface of photoresist layer, forming a polymer material layer optionally, in the etching step afterwards this optionally polymer material layer can remove or stay.Continuing it, form a material layer on wafer, for example is a BARC layer.This material layer of planarization comes out up to photoresist layer 40 then.And remove photoresist layer 40 (and the selectivity polymer material layer that remains).Carry out a pecvd process afterwards, to form another polymer material layer at (and on the polymer material layer in any reservation) on the surface of material layer 45.Follow second oxide layer 34 and silicon nitride layer 32 that etch-back exposes, and remove material layer 45 and polymer material layer simultaneously, promptly form the ON structure of dual strip of the present invention, as shown in figure 15.At this, each single memory cell 54 (dotted line) comprises dual strip and catches layer, and this dual strip catch the layer be used for forming one first 56 and 1 second 58.

If the selectivity of use polymer material layer is arranged, formed dual strip ON structure is with extend through (overlapping) bit line 21, as shown in figure 15.

Figure 16 is the stereogram of NROM among Figure 15.ONO storehouse 38 can be divided into a plurality of dual strip ON structures 60.Each strip ON is with the direction configuration of parallel bit line 21.Please refer to Figure 17, to become many word line structures 62, wherein the direction of word line structure 62 extensions is perpendicular to bit line 21 with a polysilicon layer patternization.Second oxide layer 34 and the silicon nitride layer 32 that expose of etch-back afterwards is so that a plurality of dual strip ON layer 60 forms a plurality of ON block structures 65.And between bit line 21 and extend that the ON block structure of word-line direction is separated from each other.Each memory cell 54 (dotted line) comprises two ON block structures 65, and each ON block structure 65 is one, and it is between two bit lines and a word line.

In the present invention, the silicon nitride layer 32 in each memory cell 54 is separated or cuts next, therefore, and the problem that the present invention just can avoid interference with the silicon nitride of NROM technology making now memory component.

Claims (13)

1. the manufacture method of a nonvolatile memory is characterized in that, this method comprises:

One substrate is provided, has been formed with the photoresist layer of catching a layer and a patterning in this substrate;

With this photoresist layer is that an implantation mask is to form at least one bit line;

Between this photoresist layer, form a material layer;

Remove this photoresist layer;

On the surface of this material layer, form a polymer material layer; And

With this polymer material layer is that an etching mask is caught layer to define this.

2. the manufacture method of nonvolatile memory as claimed in claim 1 is characterized in that, provides this step of this substrate more to comprise:

In this substrate, form one first oxide layer, a silicon nitride layer and one second oxide layer, catch layer to form this; And

Catch this photoresist layer of formation on the layer at this.

3. the manufacture method of nonvolatile memory as claimed in claim 1 is characterized in that, this step that forms this material layer between this photoresist layer more comprises:

Catch at this photoresist layer and this on surface of layer and form a material layer; And

This material layer of planarization is to expose this photoresist layer.

4. the manufacture method of nonvolatile memory as claimed in claim 3 is characterized in that,

This is caught layer and comprises one first oxide layer, a silicon nitride layer and one second oxide layer, only defines this second oxide layer and this silicon nitride layer and utilize this polymer material layer to comprise as an etching mask; And

This method more comprises and removes this material layer and this polymer material layer, and catches at this and to form at least one word line on layer.

5. the manufacture method of nonvolatile memory as claimed in claim 4 is characterized in that,

This at least one bit line comprises multiple bit lines;

Defining this catches layer and comprises that this is caught layer is defined as a plurality of strips and catches layer;

This at least one word line comprises many word lines; And

This step that forms above-mentioned these word lines comprises that above-mentioned these strips are caught layer forms a plurality of block structures of catching.

6. the manufacture method of nonvolatile memory as claimed in claim 3 is characterized in that, this step of this material layer of planarization comprises carries out an etch back process.

7. the manufacture method of nonvolatile memory as claimed in claim 1 is characterized in that, this material layer comprises a bottom anti-reflection layer.

8. the manufacture method of nonvolatile memory as claimed in claim 1 is characterized in that, this polymer material layer is formed with a plasma enhanced chemical vapor deposition method.

9. the manufacture method of nonvolatile memory as claimed in claim 1 is characterized in that, after forming this at least one bit line, follows and above-mentioned these are caught layer pattern changes into a plurality of dual strips and catch layer.

10. one kind in the suprabasil nonvolatile memory of semiconductor, it is characterized in that, comprising:

(a) semiconductor substrate;

(b) multiple bit lines;

(c) a plurality of block structures of catching; And

(d) many word lines, above-mentioned these word line correspondences are configured in above-mentioned these and catch on the block structure, wherein between above-mentioned these bit lines and catch block structure at above-mentioned these of this word-line direction and separate each other.

11. nonvolatile memory as claimed in claim 10 is characterized in that, above-mentioned these are caught block structure and are comprised an oxide layer and a silicon nitride layer.

12. nonvolatile memory as claimed in claim 11 is characterized in that,

This oxide layer comprises one second oxide layer; And

One first oxide layer, its above-mentioned these that extend between above-mentioned these bit lines are caught between the block structure.

13. nonvolatile memory as claimed in claim 10 is characterized in that, each above-mentioned these is caught block structure corresponding to one in the memory cell single position.

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