CN1261945C - Reduced multiport register unit - Google Patents

Abstract

A multi-ported register cell that reduces the number of metal wires and/or transistors per write port. The cell includes a storage element that stores a bit. Each write port includes three transistors and two wires. The first transistor is coupled to a true input of the storage element. The second transistor is coupled to a complement input of the storage element. The first wire selectively turns on the first and second transistors of one of the ports. The second wire provides the update value. The third transistor selectively couples the second transistor to ground depending upon whether the second wire turns on the third transistor, thereby providing a complement of the update value to the second transistor. The cell also includes one or more read ports for reading the storage element bit. A multi-ported register file may be created from the cells.

Description

The multiport register unit that dwindles

Technical field

The invention relates to semi-conductive field, particularly relevant for multiport semiconductor register cell (multi-ported semiconductor register cell).

Background technology

Digital circuit generally can use register to come storage data.Especially, microprocessor can comprise one group of register (being commonly referred to as register file, register file) usually, in order to save command operand and result.One example of microprocessor registers file is floating-point (floating-point) register file, and it is the array of a register, in order to preserve the operand and the result of floating point unit.The flating point register file may be sizable.For example, be used for user's visible (user-visible) the flating point register file of the floating point unit of x86 structure, promptly comprise eight 80 register.

Usually, in microprocessor, there are a plurality of functional blocks (functional block) to need the access function resister file.One of reason is, the normally pipelining of modern microprocessor.That is processor comprises the multiple stage, when a dos command line DOS through wherein the time, each stage all can be carried out the some of this instruction.Therefore, processor can be carried out a plurality of instructions simultaneously.The result is may need reading of data from register file at the multi-functional piece of streamline in each stage, and data are write register file.For example, the high-speed cache in the processor may need data are write register file, or from register file reading of data.Similarly, arithmetic and logical block in the processor also need reading of data from register file, and data are write register file.Moreover, in the stage of between processor and internal memory, transmitting data, also need the access function resister file.

Usually, the various functional blocks in the processor can need simultaneously (that is, in the identical clock period) access function resister file.If register file design becomes once can only allow a functional block to come the access function resister file, then need other functional block of access just must wait for.So may influence usefulness, because each stage in the streamline can be suspended running, register file be carried out access, and can't bring into play the advantage of processor pipeline characteristic with the latency function piece.

In order to overcome this problem, processor can comprise multiport register file usually.Multiport register file has a plurality of inbound ports that read and write, and it can make register file be read simultaneously and write activity by a plurality of functional blocks.

For example, suppose that register file has at least four and writes inbound port and two read ports.So, data cache can write data first register in the register file, first ALU can write second register with an instruction results, second ALU can write another instruction results the 3rd register, the 3rd arithmetic logical block can write the 4th register with an instruction results again, one storage stage can read an instruction results from the 5th register, with write memory, and address generator (address generator) can read an address operand from the 6th register, more than all in the identical clock period, carry out.

Multiport register file is made up of the multiport register unit.Each multiport register unit stores a position.The multiport unit can be coupled in together, and forming register, and register can fit together and become register file.Each multiport register unit has a plurality of inbound port and a plurality of read ports write.These ports utilize the action of metal connection that data and control signal are sent to register cell, to read and writing unit.Data and control signal are the transistors that is coupled in the register cell, but these transistor stored bit value or be used for carrying out steering logic will read and writing unit to determine which port.

A problem that is used for producing the existing multiport register unit of multiport register file is, because considerable port is followed in considerable wiring meeting, so can cause in the register file metal connection congested to heavens.In register file, the congested problem that can produce wiring and space utilization.

For typical register cell, its size that includes transistorized semiconductor level has promptly determined the size of unit.Another problem of some existing multiport register unit is, a large amount of metal connections may promptly determine the size of unit, but not by the size of semiconductor level.Some existing register cell attempts to alleviate this problem and the congested problem of wiring by reducing metal connection, but this measure meeting increases number of transistors, and makes register cell become big.

Therefore, we are needed to be, a kind of size is less and reduce the register cell of metal connection.

Summary of the invention

The invention provides a kind of register cell, can reduce the metal connection in most of existing register cells, and can not increase transistorized quantity.Therefore, to achieve these goals, one object of the present invention provides a kind of register cell, and it comprises the memory element with true value input (true input) and complement code input (complement input).This register cell also comprises N write circuit, and wherein each all is coupled to this memory element.Each write circuit comprises that one writes bit line, and it transmits a binary value to write in this memory element.Each write circuit also comprises a first transistor, this is write bit line be coupled to the true value input.Each write circuit also comprises second and third transistor, and it is to be connected in series to complement code to import.This writes bit line and also is coupled to the 3rd transistor, optionally makes the 3rd transistor turns, with complement code that this binary value is provided to transistor seconds.Each write circuit comprises that also one writes word line, be to be coupled to this first transistor and transistor seconds by the grid of this first transistor and the grid of this transistor seconds respectively, be used for optionally making the first transistor and transistor seconds conducting, can writing memory element optionally to make this binary value.

On the other hand, another purpose of the present invention is, a kind of register cell is provided, and it comprises the memory element with true value input and complement code input.This register cell also comprises N write circuit, and wherein each is to be coupled to this memory element.Each write circuit is basically by writing bit line and writing word line and first, second and the 3rd transistor and formed.Write bit line and transmit a binary value to write this memory element.The first transistor will write bit line and be coupled to the true value input.Second is to be connected in series to complement code to import with the 3rd transistor.Write bit line and also be coupled to the 3rd transistor, be used for optionally making the 3rd transistor turns, with complement code that this binary value is provided to transistor seconds.Writing word line is to be coupled to first and second transistor, is used for optionally making first and second transistor turns, can writing memory element optionally to make this binary value.

On the other hand, another purpose of the present invention is, a kind of register cell is provided, and it is made up of following part basically: memory element, a N write circuit and M with true value input and complement code input reads circuit, and each all is coupled to this memory element.Each write circuit comprises that one writes bit line, is used for transmitting a binary value to write this memory element.Each write circuit also comprises a first transistor, this is write bit line be coupled to the true value input.Each write circuit also comprises the second and the 3rd transistor, and it is to be connected in series to complement code to import.Write bit line and also be coupled to the 3rd transistor, be used for optionally making the 3rd transistor turns, with complement code that this binary value is provided to transistor seconds.Each write circuit comprises that also one writes word line, is coupled to first and second transistor, is used for optionally making first and second transistor turns, can writing memory element optionally to make this binary value.

On the other hand, another purpose of the present invention is that a kind of register cell is provided.This register cell comprises one in order to store the memory element of a position.This register cell comprises that also N is write inbound port.Each is write inbound port and comprises one just and write bit line and and write word line.This register cell also comprises N write circuit.Each write circuit with its pairing one of them write inbound port and be coupled to this memory element.Each write circuit comprises three transistors just.

On the other hand, another purpose of the present invention is that a kind of multiport register unit is provided.This multiport register unit comprises one in order to store the memory element of a position.This multiport register unit also comprises the N group transistor, and every group only has three transistors, and it is in order to write this memory element with this position.Every group transistor is to be coupled to memory element.This multiport register unit also comprises N group metal connection, and every group only has one to write bit line and and write word line, and it is in order to this writing memory element.Every group of metal connection is to be coupled to one group corresponding in this N group transistor.

Advantage of the present invention is, can reduce significantly that each writes the required metal connection of inbound port on some existing register cell.For the register file of forming by many these kinds unit, has the congested benefit of the metal connection of reduction.In addition, the present invention can make on other existing register cell, and each writes the required transistor size of inbound port and related semiconductor layer significant spatial reduces.Therefore, register cell of the present invention is less than existing register cell.Metal connection is congested alleviates the size decreases that can make whole register file of dwindling with register cell, thereby whole crystal grain (die) size of the processor that comprises register cell of the present invention is dwindled.

Other purpose of the present invention and advantage behind the remainder and appended icon that cooperate this instructions, will more can highlight.

Description of drawings

Fig. 1 is the block diagram of multiport register of the present invention unit;

Fig. 2 is the block diagram of Fig. 1 memory element of the present invention;

Fig. 3 is the block diagram of the register cell of prior art to Fig. 6.

Embodiment

In this manual, when circuit unit is described as " coupling ", is that finger assembly is by as metal connection or semiconductor material, and directly links together.The another kind of connotation that " couples " is that assembly is to connect indirectly by another circuit unit.

Fig. 1 is the block diagram of multiport register of the present invention unit 100.The embodiment of register cell 100 shown in Figure 1 comprises that four are write inbound port and two read ports.Yet the transistor configuration of register cell 100 also can change the read port that comprises other varying number into and write inbound port, and still has advantage of the present invention.

Register cell 100 comprises a memory element 102, or storage transistor 102, and memory element 102 is that configuration is the data of the single position of storage register (as the register in the register file).Memory element 102 comprises the input/output line of a true value and the input/output line of a complement code, represents with mouth and DB respectively.A plurality of register cells 100 can be coupled in together, form one and can store a plurality of multiport register.A plurality of registers of being made up of register cell 100 can be coupled in together, to form a multiport register file.

Why register file is multiport, is because of there being a plurality of functional blocks can write and/or read register in the register file simultaneously.Particularly,, can allow four difference in functionality pieces in the microprocessor, simultaneously four different registers in the register file be made write activity by the multiport register file that the register cell among Fig. 1 embodiment is formed.Similarly, two difference in functionality pieces in the microprocessor can read two different registers in the register file simultaneously.Moreover, also can read and write the particular register in the register file simultaneously.

Fig. 2 is the block diagram of memory element 102 among Fig. 1.Memory element 102 comprises two N channel MOS assemblies (being denoted as N17 and N18), and two P channel MOS assemblies (being denoted as P1 and P2).The source electrode of N17 and N18 is coupled to V _SsOr ground connection.The source electrode of P1 and P2 is coupled to V _DdThe drain electrode of N18 is the drain electrode that is coupled to P2, and the two then all is couple to the grid of true value I/O D and P1 and N17.The drain electrode of N17 is the drain electrode that is coupled to P1, and the two then all is couple to the grid of complement code I/O DB and P2 and N18.Configuration according to this, N17, N18, P1 and P2 can operate together, and to store single place value, it can write by true value input D and/or complement code input DB, and reads by true value output D, as mentioned above.

Coupling of the grid of N17 and P1 and drain electrode can produce a phase inverter, and it is input as D, is output as DB.Similarly, also coupling of the grid of N18 and P2 and drain electrode can produce a phase inverter, and it is input as DB, is output as D.The output of each phase inverter can be coupled to the input of another phase inverter, so as to producing in order to store the circuit of a place value on node port.

Referring again to Fig. 1, register cell 100 also comprises that four write word line (write wordline, horizontal metal wiring WWL) is denoted as WWL1, WWL2, WWL3 and WWL4.WWL1～4 are control signal, in order to write the register of being made up of the unit of similar units 100.In typical register, WWL1～4 can be coupled to each unit 100.Processor wherein produces high value (high value) in a wiring in WWL1～4, writes register will newly being worth.

Register cell 100 comprises that also two are read word line (read wordline, horizontal metal wiring RWL) is denoted as RWL1 and RWL2.RWL1～2 are control signal, in order to read the register of being made up of the unit of similar units 100.In typical register, RWL1～2 can be coupled to each unit 100.Processor wherein produces high value in a wiring in RWL1～2, to read the value that is stored in the register.

Register cell 100 comprises that also four write bit line (write bitline, vertical metal wiring WBL) is denoted as WBL1, WBL2, WBL3 and WBL4.WBL1～4 are data-signal, in the memory element 102 that place value is write the register of being made up of the unit of similar units 100.Many groups WBL1～4 can fit together and become data bus, in order to data value (as 64 place values) is write register.For 64 groups of WBL1～4 of data bus, processor can produce 1 or 0 value, so that 64 place values are write register in wherein wiring of each group.

Register cell 100 comprises that also (read bitline, vertical metal wiring RBL) is denoted as RBL1 and RBL2 to two reading bit line.RBL1～2 are data-signal, in order to from the memory element 102 of the register be made up of the unit of similar units 100, read its place value.Many groups RBL1～2 can fit together and become data bus, with from the register read value of fetching data (as 64 place values).For 64 groups of RBL1～2 of data bus, processor can each group wherein read 1 or 0 value in one or two wiring, to read 64 place values from register.

On the whole, WWL1 and WBL1 formation writes port one.Similarly, WWL2 and WBL2 formation are write inbound port 2, and WWL3 and WBL3 formation are write inbound port 3, and WWL4 and WBL4 formation are write inbound port 4.On the whole, RWL1 and RBL1 constitute read port 1, and RWL2 and RBL2 constitute read port 2.

Register cell 100 also comprises four N channel MOS assemblies, is denoted as N5 to N8.N5 is the D I/O that is coupled to memory element 102 to the drain electrode of N8.N5 is coupled to WWL1 to WWL4 respectively to the grid of N8.N5 then is coupled to WBL1 to WBL4 respectively to the source electrode of N8.

Register cell 100 also comprises four N channel MOS assemblies, is denoted as N9 to N12.N9 is the DB I/O that is coupled to memory element 102 to the drain electrode of N12.N9 is to be coupled to WWL1 to WWL4 respectively to the grid of N12.

Register cell 100 also comprises four N channel MOS assemblies, is denoted as N13 to N16.N13 is to be coupled to the source electrode of N9 to N12 respectively to the drain electrode of N16.That is N9 is to be connected in series respectively to N13 to N16 to N12.N13 is coupled to WBL1 to WBL4 respectively to the grid of N16.N13 then is coupled to V to the source electrode of N16 _Ss

N5 constitutes four write circuits 108 altogether to N16.One of them write circuit 108 is made up of N5, N9 and N13.Another write circuit 108 is made up of N6, N10 and N14.Another is made up of N7, N11 and N15 write circuit 108.108 of last write circuits are made up of N8, N12 and N16.

N5 is to N16, and the aforementioned coupling mode of memory element 102, WBL1～4 and WWL1～4 can write memory element 102 by in four functional blocks any.For example, suppose to be coupled to the functional block of writing inbound port 3 and want to write a high value (being binary one) to memory element 102.Functional block can be set at high value with WWL3 and WBL3, that is functional block can be charged to WWL3 and WBL3 in fact near V _DdValue.High value on the WBL3 can make the N15 conducting, and the high value on the WWL3 can make the N11 conducting.Therefore, the discharge path of ground connection can offer the complement code DB I/O of memory element 102, causes a high value to deposit in the memory element 102.This is that and memory element 102 can store the value after anti-phase, that is the high value can be stored on the true value D I/O end because the N17 of Fig. 2 memory element 102 and low value that P1 can be received complement code DB I/O end give anti-phasely.In other words, because WBL3 is high, so N15 can provide low value in its drain electrode.High value on the WWL3 can make the N11 conducting, and N11 delivers to the complement code I/O DB of memory element 102 then with the low value of receiving from the drain electrode of N15 on its source electrode.

Otherwise, suppose to be coupled to the functional block of writing inbound port 3 and want a low value (being binary zero) writing memory element 102.Functional block can be set high value on the WWL3 and the low value on the WBL3, that is functional block is charged to WWL3 in fact near V _DdValue, and WBL3 discharged in fact near V _SsValue.High value on the WWL3 makes the N7 conducting.Therefore, N7 provides the true value D I/O of discharge path to memory element 102, and low value is deposited in the memory element 102.

Register cell 100 also comprises a phase inverter 106.The input of phase inverter 106 is coupled to the true value I/O D of memory element 102.

Register cell 100 also comprises two N channel MOS assemblies, is denoted as N1 and N2.The drain electrode of N1 is to be coupled to RBL1.The grid of N1 is to be coupled to RWL1.The source electrode of N1 is the drain electrode that is coupled to N2.The source electrode of N2 is to couple V _SsThe grid of N2 then is coupled to the output of phase inverter 106.

Register cell 100 also comprises two N channel MOS assemblies, is denoted as N3 and N4.The drain electrode of N3 is to be coupled to RBL2.The grid of N3 is to be coupled to RWL2.The source electrode of N3 is the drain electrode that is coupled to N4.The source electrode of N4 is to couple V _SsThe grid of N4 then is coupled to the output of phase inverter 106.

On the whole, N1 promptly is called to N4 and phase inverter 106 and reads circuit 104.One of them reads circuit 104 and is made up of phase inverter 106, N1 and N2.Another reads 104 in circuit and is made up of phase inverter 106, N3 and N4.

In one embodiment, register cell 100 is that clock according to two phase operates.In one embodiment, RBL1 and RBL2 can keep suspension joint (floating) during phase place 1, and during phase place 2, can the paramount value of pre-charge.Reading 104 in circuit allows memory element 102 to read by one or two in two functional blocks.

For example, suppose that the functional block that is coupled to read port 2 wants to read the value that is stored in the memory element 102.Suppose further that again the value that is stored in the memory element 102 is a low value.Functional block can be set the high value on the RWL2.106 of phase inverters receive these low values from memory element 102, and produce a high value in its output terminal, are received by the grid of N4.The high value of phase inverter 106 output terminals can make the N4 conducting, and the high value of RWL2 can make the N3 conducting; Thereby the discharge path of ground connection can offer node R BL2.Therefore, the high value of the last pre-charge during phase place 2 of RBL2 can be discharged into low value by the path by N3 and N4 during phase place 1.Therefore, on read port 2, functional block can read binary zero from memory element 102.

Otherwise the value of supposing to be stored in the memory element 102 is a high value.Functional block can be set the high value on the RWL2, to read the place value that is stored in the memory element 102.Phase inverter 106 receives its high value from memory element 102, and produces a low value in output terminal, is received by the grid of N4, and the low value of phase inverter 106 output terminals can make not conducting of N4.Therefore, though the high value on the RWL2 can make the N3 conducting, there is not discharge path can offer node R BL2.Therefore, the high value of the last pre-charge during phase place 2 of RBL2 can maintain high value during phase place 1.Therefore, on read port 2, functional block can read binary one from memory element 102.

In order more completely to understand advantage of the present invention, hereinafter will narrate four kinds of existing register cells in Fig. 3 to Fig. 6.Fig. 3 comprises four and writes inbound port and two read ports to each unit among Fig. 6, compare with unit 100 with Fig. 1, Fig. 3 is similar with the register cell 100 of Fig. 1 in some aspects to the register cell of Fig. 6, and similar assembly can use identical label, in the hope of simplifying with distinct.

Fig. 3 is the block diagram of an existing register cell 300.Register cell 300 comprises that a memory element 102, two read circuit 104, RWL1～2, RBL1～2, WWL1～4, WBL1～4 and N5～12, as the register cell 100 of Fig. 1.Yet register cell 300 does not comprise the N13～N16 in the register cell 100.The substitute is, register cell 300 has comprised four vertical metal wiring that oppositely write bit line (WBLX), is denoted as WBLX1, WBLX2, WBLX3 and WBLX4, and it is coupled to the source electrode of N9, N10, N11 and N12 respectively.WBLX1～4 provide the complement code of WBL1～4 to N9～N12 respectively.Complement code is to produce by unit 300 outer circuit.

Can be observed, each of unit 300 write inbound port and had 3 strip metal wiring; Yet each of Fig. 1 unit 100 write inbound port and had only 2 strip metal wiring.One of shortcoming of unit 300 is that it comprises considerable metal connection.Especially, unit 300 has more four in order to the metal connection with place value writing memory element 102 than unit 100, and this size that may make unit 300 is greater than unit 100, and the increase metal level is congested.

Fig. 4 is the block diagram of an existing register cell 400.Register cell 400 comprises that a memory element 102, two read circuit 104, RWL1～2, RBL1～2, WWL1～4 and WBL1～4, as the register cell 100 of Fig. 1.Yet register cell 400 does not comprise the N5～N16 in the register cell 100.The substitute is, register cell 400 comprises four conducting doors (passgate), or transmission gate (transmission gate), is denoted as PG1, PG2, PG3 and PG4.PG1～4th formed by a N channel transistor and a P channel transistor coupled in parallel, and wherein two transistorized source electrodes are coupled in together, and drain electrode also is coupled in together.The drain electrode of PG1～4 is the true value I/O D that are coupled to memory element 102.The source electrode of PG1～4 is to be coupled to WBL1～4 respectively.WWL1～4 item are coupled to the grid of the N channel transistor of PG1～4 respectively.

Register cell 400 also comprises four horizontal metal wiring that oppositely write word line (WWLX), is denoted as WWLX1, WWLX2, WWLX3 and WWLX4, and it is coupled to the grid of the P channel transistor of PG1～4 respectively.WBLX1～4 can be transmitted the complement code of WBL1～4 respectively.Complement code is to produce by unit 400 outer circuit.

Can be observed, each in the unit 400 write inbound port and had 3 strip metal wiring; Yet each of Fig. 1 unit 100 write inbound port and had only 2 strip metal wiring.One of shortcoming of unit 400 is that it comprises considerable metal connection.Especially, unit 400, similar with the unit 300 of Fig. 3, can have more four in order to metal connection than unit 100 with place value writing memory element 102, this size that may make unit 400 is greater than unit 100, and the increase metal level is congested.

Fig. 5 is the block diagram of an existing register cell 500.Register cell 500 comprises that a memory element 102, two read circuit 104, RWL1～2, RBL1～2, WWL1～4 and WBL1～4, as the register cell 100 of Fig. 1.Yet register cell 500 does not comprise the N5～N16 in the register cell 100.The substitute is, register cell 400 comprises four conducting doors, and is similar with the unit 400 of Fig. 4, is denoted as PG1, PG2, PG3 and PG4.Register cell 500 also comprises four phase inverters, is denoted as 512,514,516 and 518.Register cell 500 does not comprise metal connection WWLX1～4 in Fig. 4 unit 400.The substitute is, the grid of the P channel transistor of PG1～4 is the output that is coupled to phase inverter 512,514,516 and 518 respectively, and phase inverter 512,514,516 and 518 input then are coupled to WWL1～4 respectively.

Can be observed, one of shortcoming of unit 500 is, though it comprises the metal connection with Fig. 1 unit 100 equal numbers, comprises more transistor than unit 100.Especially, suppose that phase inverter 512 to 516 comprises two transistors at least, then unit 500 has more four in order to the transistor with place value writing memory element 102 to I haven't seen you for ages than unit 100, and this size that may make unit 500 is greater than unit 100.

Fig. 6 is the block diagram of an existing register cell 600.Register cell 600 comprises that a memory element 102, two read circuit 104, RWL1～2, RBL1～2, WWL1～4, WBL1～4 and N5～12, as the register cell 100 of Fig. 1.Yet register cell 600 does not comprise the N13～N16 in the register cell 100.The substitute is, register cell 600 comprises four phase inverters, is denoted as 612,614,616 and 618.The source electrode of N9～N12 is the output that is coupled to phase inverter 612,614,616 and 618 respectively, and phase inverter 612,614,616 and 618 input then are coupled to WBL1～4 respectively.

Can be observed, one of shortcoming of unit 600 is, though it comprises the metal connection with Fig. 1 unit 100 equal numbers, comprises more transistor than unit 100.Especially, suppose that phase inverter 612 to 616 comprises two transistors at least, unit 600 has more four in order to the transistor with place value writing memory element 102 to I haven't seen you for ages than unit 100, and this size that may make unit 600 is greater than unit 100.

Though the present invention and purpose thereof, feature and advantage are described in detail, other embodiment also can be within the scope of the present invention.For example, write inbound port and two read ports though embodiment of the present invention has four, the present invention also writes the register cell of inbound port and read port applicable to having different numbers.

It is obvious to those skilled in the art that and under the situation that does not break away from the spirit and scope of the present invention, to make various improvement and variation the present invention.Therefore, this means that if these improvement of the present invention and variation are dropped in the scope and equivalent scope thereof of claims, these improvement and variation have just been contained in the present invention.

Claims (11)

1. register cell is characterized in that it comprises:

A memory element has true value input and complement code input; And

N write circuit, each all is coupled to this memory element, and wherein N is the integer greater than 1, and each write circuit comprises:

One writes bit line, is used for transmitting a binary value to write this memory element;

A first transistor writes bit line with this and is coupled to this true value input;

Second and third transistor, serial connection is to this complement code input, and the wherein said bit line that writes also is coupled to the 3rd transistor, and optionally to make the 3rd transistor turns, the complement code that this binary value is provided is to this transistor seconds; And

One writes word line, be coupled to this first transistor and this transistor seconds by the grid of this first transistor and the grid of this transistor seconds respectively, be used for optionally making this first transistor and this transistor seconds conducting, can write this memory element optionally to make this binary value;

Wherein, describedly write bit line and write the only input wires of each write circuit that word line is a described N write circuit;

Wherein, described first, second and third transistor is only transistor in each write circuit of a described N write circuit;

Wherein, a drain electrode of described transistor seconds is coupled to this complement code input, and a source electrode is coupled to the 3rd a transistorized drain electrode; The described the 3rd a transistorized source ground, a grid connects this and writes bit line.

2. register cell as claimed in claim 1 is characterized in that described N is greater than 2.

3. register cell as claimed in claim 1 is characterized in that, also comprises:

M is read circuit, is coupled to this memory element, and in order to read this binary value from this memory element, wherein M is the integer greater than 1.

4. register cell as claimed in claim 3 is characterized in that individual each that reads circuit of described M reads circuit and comprises:

An output connection in order to reading this binary value from this memory element, and is coupled to this with this true value input and reads circuit.

5. register cell as claimed in claim 4 is characterized in that individual each that reads circuit of described M reads circuit and also comprises:

One is read word line, is coupled to this and reads circuit, is used for optionally making this to read a transistor turns of circuit, optionally to allow reading this binary value from this memory element.

6. register cell is characterized in that it comprises:

A memory element is in order to store a position;

N writes inbound port, and each comprises one and writes bit line and and write word line; And

N write circuit, each with its pairing one of them write inbound port and be coupled to this memory element, and each write circuit comprises three transistors, wherein, N is the integer greater than 1;

Wherein, the described word line that writes is coupled to first and second in these three transistors by its grid separately respectively, be used to transmit one first signal, optionally making first and second conducting in described three transistors, and optionally upgrade this position in this memory element;

Wherein, the described bit line that writes is coupled to the 3rd grid in three transistors, is used to transmit in order to optionally to upgrade this a value;

Wherein, describedly also optionally make the 3rd conducting in these three transistors, deliver to this second transistor in these three transistors with a complement code that will be worth in this this value that writes on the bit line to be transmitted;

Wherein, described memory element has one first input of this first transistor drain that is coupled in these three transistors, and one second input that is coupled to this second transistor drain in these three transistors, this second transistorized source electrode is coupled to the 3rd transistor drain, the 3rd transistorized source ground.

7. register cell as claimed in claim 6 is characterized in that this complement code that described transistor seconds optionally will be worth delivers to this memory element, in order to optionally to upgrade this position.

8. register cell as claimed in claim 6, this that it is characterized in that described N writes inbound port write bit line and determine that writing in the inbound port which for this N can upgrade this memory element.

9. register cell as claimed in claim 6 is characterized in that described N is greater than 2.

10. register cell as claimed in claim 6 is characterized in that described N is 4.

11. register cell as claimed in claim 9 is characterized in that, also comprises:

At least two are read circuit, are coupled to this memory element, in order to read this place value from this memory element.

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