TWI272618B - Reduced size multi-port register cell - Google Patents

Abstract

A multi-ported register cell that reduces the number of metal wires and/or transistors per write port. The cell includes a storage element that stores a bit. Each write port includes three transistors and two wires. The first transistor is coupled to a true input of the storage element. The second transistor is coupled to a complement input of the storage element. The first wire selectively turns on the first and second transistors of one of the ports. The second wire provides the update value. The third transistor selectively couples the second transistor to ground depending upon whether the second wire turns on the third transistor, thereby providing a complement of the update value to the second transistor. The cell also includes one or more read ports for reading the storage element bit. A multi-ported register file may be created from the cells.

Description

1272618 V. INSTRUCTIONS (1) ----- [ 0 0 0 1 ] This application claims the following U.S. application No. 1 0/279,209, the filing date is 2〇〇2 years, 1 month, 22 days. Innocent and tired [Technical field to which the invention pertains] 'Especially related to semiconductors [0 0 0 2 ] The present invention relates to the field of semiconductors in a multi-turn semiconductor register unit (fflulti_ported register cell) ° [Prior Art] [0 0 0 3 ] Digital circuits typically use a scratchpad to store data. In particular, microprocessors typically include a set of registers (generally referred to as register files) for storing instruction operands and results. An example of a microprocessor scratchpad file is a floating point (fl〇ating) p暂int register file, which is an array of scratchpads that holds the operands and results of the floating point unit. The floating point register file can be quite large. For example, a user-visible floating-point register for a floating-point unit of the x86 architecture, including eight 8-bit scratchpads. [0004] Typically, within a microprocessor, there are multiple functional blocks that require access to the scratchpad file. One reason for this is that modern microprocessors are usually pipelined. That is, the processor includes multiple stages. When an instruction passes through it, each stage executes a portion of the instruction. Therefore, the processor executes multiple instructions at the same time. The result is that multiple function blocks in various stages of the pipeline may need to read data from the scratchpad file and write the data to the scratchpad file. For example, at

1272618 V. Description of the invention (2) ---- The cache memory in the processor may need to write data to the scratchpad file, or 2 to store the data in the file. Similarly, the arithmetic and logic in the processor = early = also need to read data from the scratchpad file and write the data to the scratchpad file. Furthermore, the stage of transferring data between the processor and the memory also needs to access the scratchpad file. [00〇5] Typically, various functional blocks within the processor will need to access the scratchpad file at the same time, i.e., during the same clock cycle. If the scratchpad file is designed to allow only one function block to access the scratchpad file at a time, then other function blocks that need to be accessed must wait. This is likely to be effective because the various stages in the pipeline will be suspended and the access to the scratchpad slot will be accessed in two blocks, which will not take advantage of the processor. [0006] To overcome this problem, the processor usually has a scratchpad file. Multiple buffer files have multiple reads, and drought = causes the scratchpad file to be read and written simultaneously by multiple function blocks. [0007] For example, suppose the scratchpad file has at least four ίΓΓϋί . 'Data cache memory can write data into the temporary register of the temporary file, the first arithmetic logic unit writes the result to the second register, and the second arithmetic logic writes the first one: :Save 11, the third arithmetic logic unit can = (2) result, to write to the memory 'and the address generator Hss junction generator) can read the address operator from the sixth register, the above

I272618__ V. Inventions (3) are all performed in the same clock cycle. to make. The 暂 暂 暂 暂 暂 暂 器 器 器 器 器 器 器 器 器 器 器 元 元 元 元 元 元 元 元 元 元 元Each register will be configured together to become a temporary buffer. These 埠 埠 八 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀 兀The data and control signal values are used as control logic to the body 'these transistors can be used to store bits [〇〇〇9] for production, /, which will be read and written to the unit. One problem with the unit is that the temporary soil is stored as a multi-scratch register for the broadcast case, so it will cause the register to be broadcast. The ^ 2 wiring will be accompanied by a considerable number of memory files. The congestion will be extremely high. congestion. In the temporary [0010] for the typical temporary storage crying m between J1. The size of the semiconductor level is determined by the age of the transistor, and the size of the memory cell of the transistor is θ..., i 70 . Some of the more common use of the size of the temporary ' instead of the half-length i::ff wiring may determine the unit by reducing the metal wiring, try "U some use the scratchpad single question, but this will increase the power :jI This question is called and the wiring is congested [0 0U] This is the case, the number of the registers is larger, and the strict register unit is larger. The register unit with less metal wiring. According to the invention, the scratchpad unit can reduce most of the [0 0 1 2] provided by the present invention.

1272618 V. INSTRUCTIONS (4) I use:: store: metal wiring in the unit without increasing the number of transistors - 44: A feature of the present invention is to provide a complement in the °r, /, has a true input (true input) and _ j! complement lnput) one of the storage components. The temporary storage 3g includes N write circuits, each of which is coupled to a sub-piece. The parent write circuit includes a first input f 兀 2 for writing into the storage element. Each write circuit is also returned; two: = bracket: the first: input, connected to the true value input.丄 = 蛀1 and the second transistor, which are connected in series to the complement input. The complement of the first value is to the second transistor. Each of the channels includes a second input wiring coupled to the first transistor, and (4) selectively causes the first transistor and the second transistor to selectively enable the binary value Write to the storage component. [0013] In another aspect, a feature of the present invention is that the provisioning register unit 丨 includes a storage unit having a truth input and a complement input. The register unit also includes N write circuits, each of which is connected to the storage element. Each write circuit consists essentially of first and second private wheel connections and first, second and third transistors. The first input: = enters a carry value to write to the storage element. The first transistor couples the first-to-high pass wiring to the true value input. The second and third electro-crystalline systems are connected in series to the complement. The first input wiring is also coupled to the third transistor for selecting the third transistor to be turned on to provide the complement of the binary value to the second electrical actuator. The second input wiring is coupled to the first and second transistors for =, k

1272618 5 invention description (5) sexually make the first _ _ can write to the storage device to turn on the transistor to selectively make the binary value [0 0 1 4 ] another - register unit, complex I A feature of the present invention is that a storage and a second complement of the second round are composed of a column portion, a true value input - a _ to the storage G piece, each write circuit and M readings. Taking the circuit, each wiring, for transmitting ___ the solid write circuit includes a first input-in circuit and a first--to: into the storage element. Each write value is entered. The second input line is connected to the true input to the complement input. The first input wiring also consumes f; the second: the string selectively turns on the third transistor to provide the :::::, ' for the second transistor. Each write circuit further includes two ^, a complement to the first and the second (10), for the ground: wire, connect to 'to selectively enable the binary value can be written to the storage element two: A transistor [〇〇1 5 ], on the other hand, is a special register unit of the present invention. The 13⁄4 register unit includes a component provided by 'to'. The register unit it also includes N writers. Storage of 70 per seat = two metal connections. The register unit also includes _ == good mother write circuit writes one of its corresponding write 埠 write circuits. Mail. Each write circuit happens to contain three transistors. Connected to 忒 Storage [0016] In another aspect, a 牿矜9 multi-register register unit of the present invention. The multi-tap register unit includes two storage elements of the 'provided-type. The multi-slot register unit further includes N groups to store one-bit group only = one transistor, which is used to convert $yang-, 'transistor, each, one-electrode with μ The 3H position is written to the storage element. Every five, invention description (6) to storage components. The multi-tap register unit further includes n, and the Meng is wired, and the parent group has only two metal wires for using the bit: Each set of metal wiring is coupled to the N sets of transistors _ corresponding 'Cry' 00/1 The advantage of the present invention is that it can significantly reduce some of the conventional temporary storage: the second two: a metal wiring required for writing. For the group=scratch file, there is a reduced metal wiring. =; early profit: In addition, the present invention can make other conventional register units i, each writing η;:::;;,: semiconductor The layer space is significantly reduced. The smaller size of the case allows the entire register to be wtd, thus potentially reducing the size of the entire die containing the processor. The other features and advantages of the present invention will be more prominent, and the rest of the invention and the accompanying drawings will be more prominent. [Embodiment] [= 022] In this specification The t circuit components are depicted: the junction elements 2 are directly connected together by, for example, metal wiring or semiconductor material*. Another type of "coupling" is indirectly connected to another circuit component. Cattle

[0023] Figure 1 is a sneak peek of the present invention. Figure - shows the register unit 10. Example: The side of: and the two read 埠. However, the transistor group U 1272618 of the register unit 1〇〇

There is still the advantage that the present invention is changed to include other different numbers of read and write instructions. [0024] The transistor 1 0 2 < the temporary value of the file in the file and the DB to indicate that a plurality of registers can be stored [ 0025 ] can be the same as the block file, the file can be saved Two different temporary storage specific temporary storages in the middle controller: J device unit 100 includes a storage component 1〇2 storage component 102 is configured to store a single bit of a temporary storage device (such as a temporary storage device) data. The storage element 102 includes an input/output line and a complement input/round line, respectively, at zero. The plurality of register units 100 can be coupled together, and the plurality of registers of the group bits. A plurality of sets of register units 100 can be coupled together to form a multi-byte register file. The reason why the scratchpad slot is cumbersome is that there are multiple functions to write and/or read the scratchpad in the scratchpad file. In the embodiment, the buffer unit composed of the register unit has four different function blocks in the processor, and simultaneously writes to the four different registers. Similarly, a different function block can read two of the registers in the scratchpad file at the same time. Furthermore, the scratchpad file can be read and written simultaneously. 2 is a block diagram of the storage element 1〇2 of FIG. The memory component 102 includes two germanium channel MOS components (labeled as ^7 and ^8) and two germanium channel MOS components (labeled Ρ1 and P2). The source of the Ν18 and Ν18 is connected to Vss or ground. The sources of Ρ1 and Ρ2 are coupled to vdd. The drain of the Ν18 is connected to the drain of P2, both of which are coupled to the true input/output d and the gates of P1 and N1 7. The N1 7's drain is coupled to the pi's drain, both of which are coupled to the complement input/output DB and the gates of ρ 2 and N18. According to this group

1272618

'Storing a single bit into the DB to write, and by means of the state, N17, N18, P1 and P2 will work together with the value' which will be read by the true value input D and / or the complement value output value D, As mentioned above. „ [ 0027 ] The coupling of the gate and the drain of “7 and 1” will produce an inverter whose input is D and the output is DB. Similarly, the gate of N1^p2 will also generate an inverter with an input of (10) and an output of 〇. Each inverter 19 outputs an input to another inverter to generate a circuit for storing a one-bit value at node D. — [ 0028 ] Referring again to FIG. 1 , the register unit 1〇〇 also includes four horizontal metal lines of write word meaning (WWL), denoted as WWL1, WWL2, WWL3, and WWL4. WWL 1-4 is a control signal / a register used to write a unit of similar unit 1 。. In a typical staging, WWL1-4 is coupled to each unit. The processor generates a high value on one of the WWL blocks to write the value to the scratchpad. [0029] The register unit 1〇〇 also includes horizontal metal lines of two read word lines wordl ine ' RWL ), labeled as “!^ and RWL2. RWL1-2 is a control signal for reading by a similar unit. A single register consists of a temporary register. In a typical register, RWL1 - 2 is coupled to each unit 100. The processor KRWL1 - 2 generates a high value on one of the wires to read the storage. The value in the register. [0030] The register unit 1〇〇 also includes four vertical metal lines for writing bit lines (WBL), denoted as WBL1, WBL2, WBL3, and WBL4. WBL1 -4 Data signal to write the bit value

Page 13 1272618

^ The storage element of the register consisting of units like unit 1 〇 is in 〇2. Multiple sets of WBL1-4 will be configured together to become: *values) written to the scratchpad. For the data bus, ", and WBL1-4, the processor will generate a value of ! or 0 on one of each group's wiring to write the 64-bit value to the scratchpad. [003 1] The memory unit 100 also includes vertical metal lines of two read bit lines tMtlme, RBL), labeled as (10) and RBL2 °RBLl-2 as data signals for temporary storage from units of similar units The storage element 102 of the device reads its bit value. The multiple sets of RBL1 - 2 are configured together to become a data bus to read data values (such as 64 bit values) from the scratchpad. The 64 groups ^11_2, the processor will read the value of 丨 or 在 on one or two of each group to read the 6.4-bit value from the scratchpad. [ 0 032 ] Overall, WWL1 & WBU constitutes write 埠 1. Similarly, WWL2 and WBL2 constitute write 埠 2, WWL3 and WBL3 constitute write 埠 3, and WWL4 and WBL4 constitute write 埠 4. Overall, RWU & RBU constitutes read Take 埠1, and RWL2 and RBL2 form read 埠 2. [0033] The register unit 1 〇〇 also includes four n-channel M 〇 s components, labeled N5 to N8 The N5 to N8 gates are coupled to the D input/output of the storage device 丨〇 2. The gates of N5 to N8 are respectively coupled to WWL1 to 〇[4. The sources of N5 to (4) are respectively coupled to WBL1 to WBL 4. [0034] The register unit 1〇〇 also includes four n-channel M〇s elements, labeled N9 to N12. The N9 to N12 drains are coupled to the db" input/output of the storage element 1〇2 The gates of N9 to N1 2 are respectively coupled to WWL1 to 驿[4. 1272618 V. Description of the Invention (10) [0035] The register unit 1〇〇 also includes four n-channel M〇s elements, labeled as N1 3 to N1 6. The N1 3 to N1 6 gates are respectively coupled to the sources of n 9 to N1 2 . That is, N 9 to N 1 2 are respectively connected in series to N1 3 to N1 6. N1 3 to The gates of N1 6 are respectively coupled to WBL1 to WBL4. The sources of N1 3 to N1 6 are coupled to Vss 〇 [0036] N5 to N16 constitute a total of four write circuits 1 〇 8. One of the write circuits 108 It is composed of N5, N9 and N13. The other write circuit 108 is composed of N6, N10 and N14. Another write circuit is composed of N7, N11 and N15. The last write circuit is 1〇8. It consists of N8, N12 and N16. [ 0037 ] The foregoing splicing manners of N5 to N16, storage elements 1〇2, WBL1-4, and WWL1-4 enable the storage element 1 〇 2 to be written by any of the four functional blocks. For example, assume that the functional block coupled to write 想3 wants to write a high value (i.e., a binary one) to storage element 〇2. The function block will set WWL3 and WBL3 to a high value, that is, the function block will charge WWL3 and WBL3 to a value substantially close to Md. A high value on WBL3 will turn N15 on and a high value on WWL3 will turn Nl 1 on. Therefore, the grounded discharge path is supplied to the complement DB input/output of the storage element 1〇2, so that a high value is stored in the storage element 102. What is the N17 and the storage element 1〇2 of Figure 2? 1 will invert the low value received by the complement DB input/output, and the storage element 102 will store the inverted value, that is, the high value will be stored in the true value 〇 input / output f terminal. In other words, since WBL3 is high, the N15 will provide a low value on its drain. A high value on WWL3 turns Ni 1 on, while Ni 1 sends a low value on its source from the drain of N1 5 to the complement of storage element 丨〇 2

Page 15 1272618 V. Description of invention (π) Input/output DB. [0 038] Conversely, assume that the function block coupled to write 想要3 wants to write a low value (ie, binary 〇) to storage element 丨〇 2. The function block sets the high value on WWL3 and the low value on WBL3, that is, the function block charges WWL3 to a value substantially close to Vdd and discharges WBL3 to a value substantially close to Vss. A high value on WWL3 turns N7 on. Therefore, N7 provides a circuit path to the true value d input/output of the storage element 1 〇 2, and stores the low value in the storage element 102. [0039] The register early element also includes an inverter. The input of the inverter 106 is connected to the true value input/output of the storage element 1 [ 2 [0040] The register unit 1 〇〇 also includes two N-channel M 〇 s elements, denoted as N1 and N2. The drain of N1 is coupled to sRBL1. The gate of N1 is coupled to RWL1. The source of N1 is coupled to the drain of .... The gate of the N2 source coupled to Vss ° N2 is coupled to the output of the inverter 106. [0041] The register unit 丨〇〇 also includes two n-channel elements, designated N3 and N4. The N3's drain is coupled to RBl2. The gate of N3 is coupled to the drain of RWL2 ° N3 to the drain of .... Source connection of N4

Vss. The gate of N4 is coupled to the output of inverter 1〇6. [0 042] Overall, N]^, jN4 and inverter 1〇6 are called read circuits 104. One of the read circuits 104 is composed of inverters 106, N1 and N2. The other read circuit 104 is composed of inverters 106, N3 and N4. [0043] In one embodiment, the scratchpad unit 1 operates in accordance with the clock of the two phases. In a specific embodiment, RBL1 and RBL2 are

Page 16 1272618 V. INSTRUCTIONS (12) During phase 1, it will remain floating (f 1 0 a t i n g ), and during phase 2, it will be precharged to a high value. The read circuit 丨〇 4 enables the storage element 丨〇 2 to be read by one or two of the two functional blocks. [0 044] For example, assume that the functional block coupled to the read block 2 wants to read the value stored in the storage element 102. It is further assumed that the value stored in the storage element 102 is a low value. The function block sets the high value on RWL2. The inverse phase 1 0 6 receives the low value from storage element 1 〇 2 and produces a 咼 value at its output, which is received by the gate of N4. The high value of the output of inverter 1〇6 will turn N4 on, and the high value of RWL2 will turn N3 on; therefore, the grounded discharge path will be provided to node RBL2. Therefore, the high value pre-charged on phase R2 during phase 2 will be discharged to a low value via phase N3 and during the phase 1. Therefore, on reading 埠2, the function block will be from the device 1 0 2 Read the binary 0. [0045] Conversely, assume that the value stored in storage element 1Q2 is a high value. The function block sets the high value on RWL2 to read the bit value stored in storage element 102. The inverter 1 〇β receives its high value from the storage element 1〇2 and generates a low value at the output, which is received by the gate of N4. The low value of the output of the inverter 1〇6 makes N4 non-conductive. Therefore, although the value on RWL2 turns N3 on, no discharge path can be supplied to node RBL2. = This: The high value pre-charged during phase 2 on RBL2 is high at phase 1. Therefore, On reading 蟑2, the function block reads the binary one from the storage element (3). [0 046] To more fully understand the advantages of the present invention, Figures 3 through 6 describe four conventional register units. Figure 3 to Figure 6

1272618 V. INSTRUCTIONS (13) Each unit consists of four writes and two reads of 100 for comparison. The temporary storage item _ of Figure 3 to Figure 6 is simplified and clarified by the aspects of the register unit (10) of the unit of Figure 1 and the figure-number.彳 (4) The same standard will be used for the pieces. [0047] Figure 2 is a syllabus used in the syllabus of the mouth ^300 ^ # ^ ° ^ = single 1 〇. In the middle of the _ Ν ; ; ; ; ; ; ; ; : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : WBLX2, fBLX3 and WRT U, the source is not the source of the m, LX = two mention: two connected to N9, (four), [^048] can be observed, each write 单元 of the unit 3〇〇 3 gold records. (10) A 9 ΛΛμ ΰ 兀 100 母 埠 埠 之一 埠 埠 埠 埠 埠 埠 埠 埠 埠 之一 之一 之一 之一 之一 之一 之一 之一 之一 之一 之一 之一 之一 之一 之一 之一 之一 之一In particular, the single cell 00 is four more than the cell 100 for writing the bit value to the metal wiring of the memory device 102. This may cause the cell size to be larger than the cell 100 and increase the congestion of the metal layer. [, 9] Figure 4 is a block diagram of a conventional register unit 4〇〇. The temporary Q includes a storage element 1G2, two read circuits 1〇4, ML1-2, RBL1-2, L1-4, and WBL1-4, such as the temporary crying unit = 如图. However, the register unit 400 does not include N5_N16 in the register unit 1A. Instead, the register unit 4 includes four pass gates 1272618, a description (14) (passgate) or a transmissi (J1 gate), designated PG1, PG2, PG3, and PG4. The PG 4 is formed by parallel coupling of an N-channel transistor and a p-channel transistor, wherein the sources of the two transistors are coupled together, and the drains are also coupled together. The drain of PG 1-4 is coupled to the true value input/output D of the storage element 102. Source of pG1-4 WBLH. The tendons are respectively connected to the pG1_4 "channel crystal = connected to the pole [0050] register unit 4" also includes the horizontal metal wiring of the four reverse write word lines (WWLX), marked as release , wwlx2 and WWLX4, which are respectively connected to pG Bu 4? The gate of the channel transistor is dedicated to the complement of WBL1_4. Complement (4) ^, [ΓΓ; 3 " 3 ^ 口早疋1〇〇的母写There are only two wires in the port. One of the disadvantages of the unit 400 is the flat metal strip, especially the unit 400,;; one: the metal wiring. There are four more ones for writing the bit value. = like, will be more than unit _ may make unit 4. 〇 size is written large: single storage two pieces wide 2: metal wiring 'this congestion. Inch is greater than early 兀 100, and increase the metal layer [0 0 5 2 ] map The memory unit 500 includes a block diagram of the memory unit 500. Temporary-2, RBU_2, and 2 memory; "block 102, two read circuits..., and 100. However, temporary storage No. 2, WBU-4 'Scratchpad unit 如图5-Π6 as shown in Fig.. Instead, 疋I, the 疋 register unit 400 in the register unit 100 includes four pass gates.

Page 19 1272618 V. Description of the invention (15) Similar to the unit 4〇〇 of Figure 4, denoted as PG1, PG2, PG3 and PG4. The register unit 500 also includes four inverters, designated 512, 514, 516, and 518. The register unit 5 does not include the metal wiring WWLX1 - 4 in the unit 4 of Figure 4. Instead, the gates of the P-channel transistors of PG1-4 are coupled to the outputs of inverters 512, 514, 516, and 518, respectively, and the inputs of inverters 512, 514, 516, and 518 are coupled respectively. To WWL1-4. [0053] It can be observed that one of the disadvantages of cell 50 is that although it contains the same number of metal wires as cell 1 of Figure 1, it contains more transistors than cell 1 . In particular, assuming that the inverters 5丨2 to 5丨6 include at least two transistors, the cell 500 will have at least four more cells than the cell 1 to write the bit values to the storage element 102. Crystal, this may make the size of unit 5〇〇 larger than unit 1〇〇. [0054] Figure 6 is a block diagram of a conventional register unit 6〇〇. The temporary storage unit 600 includes a storage component 1〇2, two read circuits 1〇4, RWU-2, RBU-2, WWL1-4, WBU-4 and N5-12, such as the register unit 100 of FIG. . However, the register unit 6 does not include N13-N16 in the register unit 100. Instead, the register unit 6() includes four inverters, labeled 612, 614, 616, and 618. The sources of the N9-N12 are respectively coupled to the outputs of the inverters 6 1 2, 6 1 4, 6 16 and 61 18, and the inputs of the inverters 612, 614, 616 and 618 are respectively coupled to WBU-4. Port [0055] It can be observed that one of the disadvantages of cell 6〇〇 is that although it contains the same number of metal wires as cell 100 of Figure 1, it has more transistors than cell 丨'. In particular, it is assumed that the inverters 6丨2 to 6丨6 include at least two electro-crystals H, and the unit 600 has at least four more than the unit 1〇〇 for placing the bits.

1272618 V. INSTRUCTION DESCRIPTION (16) The element value is written to the transistor of the storage element 102, which may cause the cell 6〇〇 to be larger than the cell 100. [0056] While the invention and its objects, features and advantages have been described in detail, other embodiments may be included within the scope of the invention. For example, although the embodiment of the present invention has four write buffers and two read buffers, it can be applied to a temporary memory device having a different number of write buffers and read buffers. The above is only the preferred embodiment of the present invention, and the scope of the invention can be limited thereto. According to the invention, the equal changes and modifications made by the scope of the invention are still within the scope of profit = **, please be sure to review the committee, and pray for the right, is to find:

Page 21 1272618 Brief Description of the Drawings [Simple Description of the Drawings] [0 0 1 9] Figure 1 is a block diagram of a multi-turn register unit of the present invention. [0 0 2 0 ] Figure 2 is a block diagram of the storage element of Figure 1 of the present invention. [0 0 2 1 ] FIG. 3 to FIG. 6 are block diagrams of a conventional register unit of the prior art: 1 0 0 - register unit '104' - read circuit 108 - write circuit 400 - register unit 512, 514, 516, 518- counter 612, 614, 616, 618-reverse 102-storage component 1 0 6 - inverter 30 0-scratchpad unit 5 0 0 - register unit 6 0 0 - temporary Memory unit

Page 22

Claims (1)

%. Patent application scope 1 · A register unit, comprising: a storage unit having a true value input and a complement, an input; and: N write circuits, each coupled to the storage element, Each writer circuit includes: " a first input wiring for transmitting a binary value to nest into the ..... . . . . . . . . . . . . . . . ·· - .......................... In the storage element; - a first transistor that couples the first input connection to the true value Wheeling; the first transmission of two transistors; with the transistor through, to 2. First and line. 3. First, the transistor 4. The first, the first and third transistors of the transistor are serially connected to the complement input, wherein the input wiring is also coupled to the third transistor to selectively enable Talk about the first insult, provide one of the binary values to the Dijon. --- ' .............. and a second input wiring, the handle is connected to The first transistor and the second are configured to selectively cause the first transistor and the second transistor to selectively enable the binary value to be written to the storage element. [1] The register unit of claim 1, wherein the second input wiring system has only one input of each of the write circuits, such as the temporary register described in claim 2 a unit, wherein the second and third electro-crystal systems are each of the ones of the write circuits, such as the register unit of claim 1, wherein the first and third electro-crystal systems Only one of each of the N write circuits 0608-A40741TWFl.ptc Page 23 1272618 Case No. 921 (W (U1 a jEje VI. Patent Application No. 5) The register unit described in item i of the patent application scope is at 2 〇 6 · One of the second transistors of the register unit is coupled to the complement wheel winter.: :7 · The temporary storage unit of the sixth embodiment of the patent application scope One source is grounded. 丨8 · For example: please refer to the patent scope of item 7 ^^^^ One of the second transistor is coupled to one of the third transistors. Patent Application No. 1: The first, second and third transistors include gold oxide semiconductors (M〇s 10 • as claimed in the patent) First, second and third transistors comprise n-channel M〇s components ~ Included · 11 · The register unit described in the scope of the patent application section [7], the packaged circuit is 'lighted to the storage element for reading the binary value from the piece. 夂 4埽存元 is greater than j 2: as described in item n of the patent application, the temporary storage unit 13' as described in the scope of the patent application, the temporary crying single mother, one reading Take the circuit package, including: ;w early, which: where N big 'which should be: ': where 5 cML ll? eight γ and the pole. ΐ its 'call...the..:1 where Μ a read circuit, the true value wheel is coupled to the 14; as claimed in the patent range 13th, / γ output wiring, the register unit is returned 0608-A40741TWFl.ptc The 24th tributary, the scope of the patent application, each of the reading circuits further includes that you eat two f two input wirings' to the reading circuit, and select the two storage elements to read the two The carry value Γ is selectively enabled from the error Λ ^2 ^' ^ ^ ^ ^ 11 ®; ^ 11 31 ^ ^ ^ ^ ^ ^ ^ ^ ^ is greater than I6. · For example, 'Kiss ^' 17: ^ register unit ^ package 漱 N writes to the drought 'mother one just 咆 至 to the storage path' each one of which corresponds to one of them; 70 pieces 'and each writing circuit contains exactly three crystals. The second unit is a register unit according to item 17 of the patent scope, wherein the first one of the three parts of the electric S 传送 transmits a first signal, To selectively turn on the first one of the storage cells and the second one, and selectively to be 19 as the bit in ▲. Second... :I- The two Jin Yao \ read the register unit described in item 18 of the patent scope, its electricity; one of the values is the second transmission in the wiring to selectively update the bit. ΛΛ ';'',:;. ^· ^ ;' .ΛΪ;·.Γ: ”...·. 'i··.- -· -:v ::.,. ," ... :, 20 · If the singer is in the test case, the register unit mentioned in item 19 of the patent scope, wherein: the transfer value of the ground metal connection is also optional: The third choke in a transistor 0608-A40741TWFl.ptc Page 25 1272618 _ __ Case No. 921Q0941_P Year VI. Patent application scope to the second electro-crystalline ship in the three transistors. The register unit of claim 20, wherein the storage element has a first input that is stolen to the first one of the three transistors, and is connected to the first The second of the three transistors, ^. The 'one of the crystal:::: the second 'round I; . , * ..... · · ' . ,........ 22 · The temporary storage unit as described in item 21 of the patent application scope, which is used to selectively update the bit. f 23 ·For example, please refer to the temporary range mentioned in item 8 of the patent scope; the memory of the Tsui Yuan r r ^ ^ ^ ^ ^ The N writes of the two metal wiring and the first wiring will be jointly determined Talk about which fake meeting in N偃 is written ^ 2 4 · If you apply for the stunner military yuan mentioned in item 7 of the patent application, its application is greater than 2·. 10.25. The register unit as described in claim 17 of the patent application, wherein the two reading circuits of the 24th item of the patent application scope are coupled to the food storage device, The storage unit reads the bit value, 2 7 ·. 獐 埠 埠 埠 单元 , , , 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 卜 Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ni Ni Ni Ni Ni Ni Ni Ni Ni Ni Ni Ni Ni There are only three transistors in the group, and each group of electro-crystal systems: connected to the storage element v甩 to place the yielding bits in each group with only two metal wirings. The wire system is coupled to a corresponding one of the N sets of transistors for writing the bit to the storage element. • 2 8 · If the scope of the patent application is greater than 2'. : 卜29 ·If you apply for a special, the driving situation mentioned in item 27 of the profit range I ' 备 4 • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - ... 1 3 0 ·: For the ball, for each of the N sets of transistors, the only two of the ties are coupled to the storage element. 3 1 · As for the temporary storage unit of the third paragraph of the patent application scope, for each of the N sets of transistors, the only two: the first one of the transistors is coupled To the storage element one of the complement inputs 'to write one of the bits to the storage element. 32. The f register unit according to claim 31, wherein for each of the N sets of transistors, a third of the only two transistors is coupled to the only one The second of the three transistors is used to send the bit; the complement of the element to the second of the only three transistors > a: 33 · as claimed in the patent scope 32. The register unit of claim 32, wherein for each of the N sets of transistors and the corresponding one of the N sets of metal wires, the first one of the only two metal wires is Pass the bit ' to write to the storage element. 34·如: Reference to each of the N sets of transistors and the N sets of metal wiring 27th buy 0608-A40741TWFl.ptc 1272618 ^ . /, __ case number 92100941 S month 曰 amendment _ 6. In the scope of patent application, the first of the only two metal wires is coupled to the The third one of the three transistors, wherein the first strip of the only two metal wires selectively turns the third of the only three dummy transistors on, To selectively send the number of the bits to the three '-: ::: 1 '-. The register unit described in item 27 of the patent scope is further packaged to: less than two access circuits, coupled: branch - · , . _ ( · memory component reads the bit value.: 3 6 The register unit according to claim 35, wherein the at least two read circuits comprise two read circuits A 0608-A40741TWFl.ptc第28页