CN1261864C

CN1261864C - Multiple sources of instruction decoding

Info

Publication number: CN1261864C
Application number: CNB018164633A
Authority: CN
Inventors: R·P·辛格; G·A·奥弗坎普; C·P·洛斯
Original assignee: Analog Devices Inc; Intel Corp
Priority date: 2000-09-28
Filing date: 2001-09-25
Publication date: 2006-06-28
Anticipated expiration: 2021-09-25
Also published as: KR20030036844A; TWI237787B; JP3704519B2; WO2002027482A2; JP2004510247A; WO2002027482A3; KR100688139B1; CN1466717A

Abstract

In one embodiment, the processor includes multiple instruction sources and selects the appropriate source to provide an instruction to the decoder. Each of these instruction sources may provide instructions to a multiplexer. These instruction sources also provide signals representing the instruction size to a second multiplexer.

Description

The multiple source of instruction decoding

Technical field

The present invention relates to digital signal processor, relate in particular to and have the multiple source that instruction is provided to demoder.

Background

Digital signal processing relates to the signal performance of adopting digital form, and uses digital computation to change or handle this numeral performance.In fields such as radio communication, networking and multimedia, digital signal processing is the core technology of current many high-tech products.The reason that Digital Signal Processing is popular is to have developed the low and powerful digital signal processor (DSP) of cost always, and digital signal processor is also realized these products for the slip-stick artist provides reliable computing power effectively with cheapness.Since having developed first kind of DSP, the structure of DSP and design have developed into the degree that can carry out the real-time processing of very complicated precision to the video rate sequence.

DSP is through being usually used in the various multimedia application such as digital video, imaging and audio frequency.DSP can operate digital signal, to create and to open this class multimedia file.

MPEG-1 (Motion Picture Experts Group), MPEG-2, MPEG-4 and H.263 be compression of digital video standard and file layout.These standards pass through mainly to store the variation from a frame of video to another frame of video, rather than store each complete frame, realize the high compression ratio of digital video signal.Then, can use many different technology to come further compressing video information.

Between compression period, can use DSP to come video information is carried out various operations.These operations can comprise motion search and spatial interpolation algorithm.Fundamental purpose is the distortion between the piece of measuring in the consecutive frame.These operations are computation-intensive, may demanding data throughout.

Mpeg standard family is constantly development, to catch up with the bandwidth requirement that increases day by day to multimedia application and file.Each redaction of this standard all shows complicated algorithm more, and these algorithms propose more processing requirements to used DSP in the video processing equipment that is fit to MPEG.

Video processing equipment manufacturer often relies on the special IC (ASIC) for MPEG and the customization of H.263 substandard video coding.But the design complexity of ASIC involves great expense, and its application is flexible not as general dsp.

Summary of the invention

An aspect of of the present present invention is a kind of instruction to be offered the method for the demoder in the processor, and may further comprise the steps: in first multiplexer, a command source from a plurality of command source is collected a selected instruction; In second multiplexer, the described command source from described a plurality of command source is collected a width signal, and described width signal defines the size of described selected instruction; And described selected instruction and described width signal offered described demoder.

Another aspect of the present invention is the method that a kind of demoder place in processor obtains instruction, comprising: in first multiplexer, collect from many instructions of a plurality of command source; In second multiplexer, collect a plurality of width bits corresponding to described many instructions; Determine will be processed in described many instructions an instruction; And instruction chosen described in described many instructions and corresponding width bits transferred to demoder.

Another aspect of the present invention is a kind of processor, comprising: a plurality of command source are used to provide many instructions; First multiplexer is used to receive many instructions from described a plurality of command source, and article one that wherein said first multiplexer is selected to be performed from described many instructions is instructed; And demoder, be used to receive described selected article one instruction from described first multiplexer; With second multiplexer, be used to receive a plurality of signals from size described a plurality of command source, the described instruction of expression, wherein said second multiplexer offers described demoder with that signal that instructs corresponding to described selected article one in described a plurality of signals.

Of the present invention is a kind of demoder feeder system more on the one hand, it is characterized in that, comprising: first multiplexer is used for collecting a selected instruction and described selected instruction being offered a demoder from a command source of a plurality of command source; And second multiplexer, being used for collecting a width signal and described width signal being offered described demoder from a described command source of described a plurality of command source, wherein said width signal defines the size of described selected instruction.

Description of drawings

By reading following detailed description and with reference to the accompanying drawings, these and other feature and advantage of the present invention will be more very clear.

Fig. 1 is a kind of block diagram that utilizes the mobile video equipment of processor according to an embodiment of the invention.

Fig. 2 is the block diagram according to the signal processing system of one embodiment of the invention.

Fig. 3 is the block diagram according to a kind of alternative signal processing system of one embodiment of the invention.

Fig. 4 has illustrated the demonstration pipeline stage according to the processor among Fig. 1 of one embodiment of the invention.

Fig. 5 is the block diagram of a kind of multi-source demoder feeder system according to an embodiment of the invention.

Fig. 6 has illustrated and provides the process of selected instruction according to one embodiment of the invention for demoder from multi-source.

Describe in detail

Fig. 1 has illustrated a kind of mobile video equipment 100 that comprises processor according to one embodiment of the invention.Mobile video equipment 100 can be a kind of handheld device, and it shows the video image that results from from the encoded video signal of antenna 105 or digital video storage medium 120 (for example, Digital video disc (DVD) or memory card) reception.Processor 110 with can communicate for the cache memory 115 of processor operations storage instruction and data.Processor 110 can be microprocessor, digital signal processor (DSP), control subordinate DSP microprocessor or have the processor of hybrid microprocessor/DSP framework.For purposes of this application, processor 110 will be known as DSP 110 hereinafter.

DSP 110 can carry out various operations to the vision signal of coding, for example comprises, analog-digital conversion, demodulation, filtering, data are recovered and decoding.DSP 110 can be according to the next decoded digital video signal to compression of one of various compression of digital video standards (for example, mpeg standard family and H.263 standard).Then, the vision signal of decoding can be input to display driver 130, so that generate video image on display 125.

The power supply of handheld device is supplied with limited usually.In addition, to operate in the calculating be intensive to video decode.Therefore, be used for that the best speed of processor of this equipment is higher, power is lower.

DSP 110 can have a kind of dark streamline, load/store framework.By adopting pipelining, for nonpipeline DSP, can strengthen the performance of DSP.Streamline DSP obtains article one instruction, carries out this article one instruction, obtains the second instruction then, but the execution of instructing with article one of obtaining of second instruction is taken place simultaneously, thereby has improved instruction throughput.In addition, the clock period of comparable nonpipeline DSP of the clock period of streamline DSP is short, must obtain in the same clock period and execute instruction in nonpipeline DSP.

This DSP 110 can be used for video camcorder, teleconference, PC video card and high-definition television (HDTV).In addition, DSP 110 also can should be used for being used in conjunction with the other technologies of utilizing digital signal processing (for example, used speech processes in mobile phone technology, the speech recognition) and other.

With reference now to Fig. 2,, shows block diagram according to a kind of signal processing system 200 that comprises DSP 110 of an embodiment.One or more simulating signals can offer signal conditioner 202 by external source (for example, antenna 105).Signal conditioner 202 can be carried out some preprocessing function to these simulating signals.The preprocessing function of demonstration can comprise with the several simulating signals in these simulating signals mix, filtering, amplification etc.As mentioned above, analog to digital converter (ADC) 204 can be coupled, so that receive the digital signal of also pretreated analog signal conversion being served as reasons and sampling and form through pretreated simulating signal from signal conditioner 202.Can sample according to the determined sampling rate of characteristic of the simulating signal that is received by signal conditioner 202.DSP 110 can be coupled so that receive digital signal on the output terminal of ADC 204.DSP 110 can carry out required conversion of signals to received digital signal, produces one or more output digital signals.Digital-analog convertor (DAC) 206 can be coupled, so that receive the output digital signal from DSP 110.DAC 206 will export digital signal and be converted to the output simulating signal.Then, the output simulating signal can be passed to another signal conditioner 208.208 pairs of output of this signal conditioner simulating signal is carried out post-processing function.The post-processing function of demonstration is similar to above listed preprocessing function.Notice that the various replacement methods of

signal conditioner

202 and 208, ADC 204 and DAC 206 are well-known.Any suitable arrangement of these equipment can be coupled in the signal processing system 200 with DSP 110.

Next with reference to figure 3, show a kind of signal processing system 300 according to another embodiment.In this embodiment, can arrange digit receiver 302 to receive one or more digital signals, and received digital signal is passed to DSP 110.The same with the embodiment shown in Fig. 2, DSP 110 can carry out required conversion of signals to received digital signal, to produce one or more output digital signals.Digital signal transmitter 304 is coupled to receive the output digital signal.In a Demonstration Application, signal processing system 300 is a kind of digital audio-frequency apparatus, and wherein digit receiver 302 is given DSP 110 with the digital signal transfers that expression is stored in the data on the digital storage equipment 120.Then, DSP 110 processing digital signal, and give digit emitter 304 with the output digital signal transfers that produced.Digit emitter 304 makes the value of these output digital signals be sent to display driver 130 subsequently, so that generate video image on display 125.

Streamline shown in Figure 4 comprises 8 stations, and they can comprise that instruction obtains 402-403, decoding 404, address computation 405, carries out 406-408 and retrography 409 these stations.Instruction i can be acquired in a clock period, is carried out operation and execution then in the clock period subsequently in streamline, meanwhile, obtains new instruction (for example, i+1 and i+2).

Pipelining may be introduced extra coordination problem and impair performance of processors.Redirect in the program circuit may produce space or " bubble " in streamline.Cause and to take conditional transfer maybe will produce the sequential flow that situation unusual or that interrupt may change instruction.After this class incident takes place, can outside continuous program flow, obtain a new instruction, make remaining instruction in the streamline uncorrelated mutually.Can adopt data transmission, branch prediction and, handle these complex situations the method that significance bit is associated with instruction address in the streamline and so on.

Fig. 5 is the block diagram of a kind of multi-source demoder feeder system 500 according to an embodiment of the invention.Demoder feeder system 500 can comprise multiple source, for example, I high-speed cache/aligned units 505, loop impact damper 510, emulator command register 515 and other sources 520,64 bit multiplexed devices (MUX), 525,2 bit multiplexed devices (MUX) 530 with an order register 507, and demoder 535.Demoder feeder system 500 can allow demoder 535 directly to be presented by one of multiple source, and data need not be transferred to order register 507.Owing in this specific embodiment, will data not transfer to order register 507, therefore may reduce the performance of instructing the stand-by period and improving DSP 110.In addition, this multiple source can provide and have the same format instruction of (comprising width bits).By guaranteeing that multiple source provides the instruction of similar structureization, design that can decoder simplification 535, thus improve cycling time.

I high-speed cache/aligned units 505, loop impact damper 510, emulator command register 515 or any other source 520 can be connected to 64 MUX 525 and 2 MUX 530 both.Each source in these sources may be able to provide the instruction (for example, 16 bit instructions, 32 bit instructions or 64 bit instructions) of multiple width.These instructions are provided for 64 MUX 525.Certainly, under the premise of without departing from the spirit of the present invention, can use other big or small MUX of the instruction that to handle other size.Each source in these sources also provides a signal for 2 MUX 530, and expression is provided for the width of the instruction of 64 MUX 525.Utilize 2 signals, 4 kinds of possible values are arranged for the signal of 2 bit widths.For example, 00 width bits presentation directives is invalid, and 01 width bits is indicated one 16 bit instructions, and 10 width bits is indicated one 32 bit instructions, and 11 width bits is indicated one 64 bit instructions.In case select some specific command source, just can will transfer to demoder 535 from that source, for handling from the instruction of 64 MUX 525 with from the width bits of 2 MUX 530.

Though two multiplexers 525 and 530 are shown,, be appreciated that and can use any amount of multiplexer, so that allow to select extra information.For example, extra multiplexer can receive predecode information in the every source from the 505-520 of source, and suitable predecode information is sent to demoder.

Fig. 6 shows the process 600 that instruction is offered demoder 535.Process 600 starts from initial block 605.Advance to frame 610, one or more sources will be instructed and corresponding width bits offers MUX 525,530.As mentioned above, these instructions can be all sizes, comprise 16,32 or 64.Instruction can only be provided by one of source, and still, instruction and corresponding width bits also can be provided by the two or more sources in the source.

Advance to frame 615, select to provide the source of instruction.DSP 110 can determine that next instruction is provided by I high-speed cache/aligned units 505, loop impact damper 510, emulator command register 515 or another source 520.Determine instruction with after sending to demoder 535 at DSP 110, MUX 525 and 530 offers demoder 535 with suitable instruction and width bits.

Advance to frame 620, selected instruction and width bits are directly transferred to demoder 535, rather than are stored in the order register 507.By directly demoder 535 being transferred in these instructions, can reduce the instruction stand-by period, and can improve performance.Then, demoder 535 executable instructions.This process stops in end block 630 subsequently.

Multiplexer of the present invention 525,530 offers demoder 535 according to selected command source 505-520 with suitable information.Yet if select multiple source 505-520, multiplexer 525,530 can comprise the right of priority logic that is used to control to the information distribution of demoder 535.For example, multiplexer 525,530 can comprise the right of priority logic, regulation has highest priority from the information of emulator command register 515, and will be carried out processing before the information of coming self-loop impact damper 510 from the information of I high-speed cache/aligned units 505.In the entire process process, can pre-determine or upgrade priority scheduling.Those skilled in the art will understand many variations of the present invention and modification easily.Therefore, under the prerequisite that does not break away from spirit of the present invention or essential characteristic, can implement the present invention with other concrete forms.

Claims

1. one kind offers the method for the demoder in the processor with instruction, it is characterized in that, may further comprise the steps:

In first multiplexer, a command source from a plurality of command source is collected a selected instruction;

In second multiplexer, the described command source from described a plurality of command source is collected a width signal, and described width signal defines the size of described selected instruction; And

Described selected instruction and described width signal are offered described demoder.

2. the method for claim 1 is characterized in that, also comprises from described a plurality of command source collecting many instructions.

3. method as claimed in claim 2 is characterized in that, also comprises collecting a plurality of width bits, and described width bits is corresponding to the size from described a plurality of instructions of described a plurality of command source.

4. the method for claim 1 is characterized in that, also comprises sending the width bits corresponding to the size of described selected instruction to described demoder.

5. the method for claim 1 is characterized in that, also is included in and collects described a plurality of width bits in described second multiplexer.

6. the method for claim 1 is characterized in that, also comprises according to a priority scheduling, determines described selected instruction.

7. the method for claim 1 is characterized in that, the instruction that provides in the digital signal processor also is provided.

8. the method for the demoder place acquisition instruction in processor is characterized in that, comprising:

In first multiplexer, collect from many instructions of a plurality of command source;

In second multiplexer, collect a plurality of width bits corresponding to described many instructions;

Determine will be processed in described many instructions an instruction; And

Demoder is transferred in instruction chosen described in described many instructions and corresponding width bits.

9. method as claimed in claim 8 is characterized in that, also comprises the instruction of collecting from I high-speed cache/aligned units.

10. method as claimed in claim 8 is characterized in that, also comprises the instruction of the self-loop impact damper of collecting.

11. method as claimed in claim 8 is characterized in that, also comprises the instruction of collecting from the emulator command register.

12. method as claimed in claim 8 is characterized in that, also comprises the instruction that obtains in the digital signal processor.

13. method as claimed in claim 8 is characterized in that, also comprises collecting described many instructions with same format.

14. method as claimed in claim 8 is characterized in that, also comprises according to a priority scheduling, definite instruction that will be processed.

15. a processor is characterized in that, comprising:

A plurality of command source are used to provide many instructions;

First multiplexer is used to receive many instructions from described a plurality of command source, and article one that wherein said first multiplexer is selected to be performed from described many instructions is instructed; And,

Demoder is used to receive the described selected article one instruction from described first multiplexer; With

Second multiplexer, be used to receive a plurality of signals from size described a plurality of command source, the described instruction of expression, wherein said second multiplexer offers described demoder with that signal that instructs corresponding to described selected article one in described a plurality of signals.

16. processor as claimed in claim 15 is characterized in that, identical form is all taked in every instruction in described many instructions.

17. processor as claimed in claim 15 is characterized in that, described demoder directly receives described selected article one instruction from described multiplexer.

18. processor as claimed in claim 15 is characterized in that, described first multiplexer is selected article one instruction that will be performed according to a priority scheduling from described many instructions.

19. processor as claimed in claim 15 is characterized in that, described processor is a digital signal processor.

20. a demoder feeder system is characterized in that, comprising:

First multiplexer is used for collecting a selected instruction and described selected instruction being offered a demoder from a command source of a plurality of command source; And

Second multiplexer is used for collecting a width signal and described width signal being offered described demoder from a described command source of described a plurality of command source, and wherein said width signal defines the size of described selected instruction.

21. demoder feeder system as claimed in claim 20 is characterized in that, many instructions from described a plurality of command source that are configured to collect of described first multiplexer.

22. demoder feeder system as claimed in claim 20 is characterized in that, described second multiplexer is configured to from a plurality of width bits of described a plurality of command source collections corresponding to the size of described instruction.

23. processor as claimed in claim 15, it is characterized in that, each command source in described first multiplexer and the described a plurality of command source is coupled, described second multiplexer separates with described first multiplexer and is coupled with each command source in described a plurality of command source, and described first multiplexer and described second multiplexer are coupled in parallel described demoder.