CN1261863C - Microcontroller of data stored in storage by multi appliance access - Google Patents
Microcontroller of data stored in storage by multi appliance access Download PDFInfo
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- CN1261863C CN1261863C CN 03110479 CN03110479A CN1261863C CN 1261863 C CN1261863 C CN 1261863C CN 03110479 CN03110479 CN 03110479 CN 03110479 A CN03110479 A CN 03110479A CN 1261863 C CN1261863 C CN 1261863C
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- microprocessor
- memory bank
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- service routine
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Abstract
The present invention relates to a microcontroller that can expand memory banks, which comprises a microprocessor, a plurality of memory banks, a memory bank controlling circuit and a multiplexer, wherein the capacities of the memory banks are larger than addressable space of a single instruction of the microcontroller, and an interrupt service routine is stored in the memory banks in the present invention; a finish signal is executed by the memory bank controlling circuit according to an interrupt generating routine and the interrupt service routine of the microprocessor so as to generate a selection signal; the multiplexer comprises a first input end, a second input end, a selection end and an output end. A page selection signal which is received by the first input end and is sent by the microprocessor is output according to the selection signal input from the input end by the memory bank controlling circuit, or data can be accessed at the memory banks which store the interrupt service routine by the microprocessor when interrupt occurs by the prearranged page selection signal received by the second input end.
Description
Technical field
The present invention relates to a kind of method of memory management, particularly relate to a kind of method of microprocessor management external memory storage.
Background technology
MCS (Micro Computer System) is the general name of Intel Company to microprocessor, and the microprocessor of the MCS-51/52 series that it is developed is applied in the industry member especially at large.Generally speaking, microprocessor only contains a spot of storer and input and output point, microprocessor with MCS-51 series is an example, it has the program storage of 4K byte, data-carrier store and 32 input and output points of 128 bytes, the microprocessor of MCS-52 series then is that program storage is increased to the 8K byte, and data-carrier store increased to 256 bytes, and the microprocessor of MCS-52 and MCS-51 series is to use one 8 CPU (central processing unit) equally.Program storage is used for depositing the program that the user writes, belong to ROM (read-only memory) (ROM), data-carrier store then is a random-access memory (ram), can the time read or write data for the CPU (central processing unit) running, normally is used for the working storage of when program is carried out temporary transient store data.The microprocessor of MCS-51/52 series can be by outside extended storage, and maximum can expand to the 64K byte.
Yet among some were used, the user may need to write very big procedure code or use very big array table, and the outside expanding program storer of 64K byte still uses inadequately thus.It is a kind of method that storer significantly can be expanded that memory bank switches (bank switch), use the pin that has more on the microprocessor to do addressing to surpassing 64K bytes of memory device as decoding line, if external memory storage is a jumbo storage arrangement, the pin that then has more can be directly as address wire, if external memory storage is the storage arrangement of several low capacities, the pin that then has more can be used to the selection memory chip.Because the outside extended storage of microprocessor maximum is the 64K byte, so available 64K byte is called a page or leaf (Page) as the base unit that memory bank switches.Memory bank switches the address that maximum problem is interrupt vector table (interrupt vector table) configuration; because interrupt vector table can be placed on certain specific address in the storer usually; though program can be switched at each page or leaf when running; when but central broken hair is given birth to; the program particular address in the page or leaf of place at once removes to seek interrupt vector table; and program also can't be done the memory bank switching at this moment, when program can not find interrupt vector table, just can produce mistake.The method that generally addresses this problem, be in each memory bank, all to keep a common area (common area), store interrupt vector table, Interrupt Service Routine (interrupt servicerouine in the common area, ISR), general letter formula storehouse and memory bank switch required data, so no matter procedure operation is at that page or leaf, when program took place to interrupt, program can find interrupt vector table to continue program implementation in the page or leaf at place.
Please refer to Fig. 1, Fig. 1 is the synoptic diagram of known external program memory 12 configurations.Suppose to have the microprocessor of a MCS-51/52 series to use the mode of memory bank switching externally to expand the storer 12 of 512K position, be divided into 8 pages or leaves, each page or leaf is the 64K position, and the common area of reservation 10K position is used for depositing interrupt vector table, Interrupt Service Routine, general letter formula storehouse and the required data of memory bank switching.For instance, when when first page program need be called out second page program, can skip to immediately and read memory bank setting routine in the common area, memory bank is set the page number that routine can be set required memory bank earlier, because for microprocessor, changing the page number in common area can't influence the address of any data, and then microprocessor just can be according to required program in second page of the page number access of setting.After second page routine processes finished, program can be got back to earlier in the common area, sets routine by memory bank the page number is switched back original memory bank, and executive routine is continued in the address that returns original program in first page.In addition, when central broken hair was given birth to, processor can skip to the vector table address of its internal preset, and the content of putting down in writing according to this address skips to Interrupt Service Routine and carries out again, and then got back to the address continuation executive routine of original program.Because of known mode, interrupt vector table, Interrupt Service Routine are positioned at common area, so each page all has identical program, so do not need to do the switching of page or leaf.
From the above, the program storage that microprocessor provided of known MCS-51/52 series, maximum can only be utilized and expand external program memory to the 64K byte, but skill by the memory bank switching, use the pin that has more on the microprocessor, can again external program memory be done significantly to expand, but memory bank switches individual shortcoming is arranged, be exactly all must keep the space of a part among each memory bank as common area, be used for depositing interrupt vector table, Interrupt Service Routine, general letter formula storehouse and memory bank switch required data, and these data can be duplicated and be stored among the common area of each memory bank, thus, the space of storer just can't effectively be utilized.
Summary of the invention
Therefore fundamental purpose of the present invention provides a kind of method of microprocessor management external memory storage, to address the above problem.
A kind of microcontroller of extendible memory bank, it comprises a microprocessor, but a plurality of memory banks (memory bank) greater than the single instruction addressing space of microcontroller, be connected in this microprocessor, be used for storage data and program, also storing Interrupt Service Routine (interrupt serviceroutine) in these a plurality of memory banks; And a memory bank control circuit and a multiplexer, be connected between this microprocessor and these a plurality of memory banks.This multiplexer comprises: a first input end, be connected in first output terminal of this microprocessor, and be used for receiving the page that sends by this microprocessor and select signal, it is to be used for selecting memory bank that this page is selected signal; One second input end is connected in second output terminal of this microprocessor, is used for receiving a predetermined page and selects signal, and it is corresponding to the memory bank with this Interrupt Service Routine; And a selecting side, be used for receiving and produce one by this memory bank control circuit and select signal.This memory bank control circuit produces this selection signal according to the interruption generation source signal and the Interrupt Service Routine execution end signal of this microprocessor, this multiplexer switches the predetermined page that the page that output sent by first output terminal of this microprocessor selects second output terminal of signal or this microprocessor to send according to this selection signal selects signal, makes this microprocessor when interrupting taking place can store the memory bank access data of Interrupt Service Routine to this.
Description of drawings
Fig. 1 is the synoptic diagram of known external program memory configuration.
Fig. 2 is the synoptic diagram of its bank configuration of external memory storage of microprocessor of the present invention.
The synoptic diagram that Fig. 3 is connected with external memory storage for microprocessor of the present invention.
The drawing reference numeral explanation
12 external program memories
20 microprocessors
22 external memory storages
23 memory bank control circuits
24 multiplexers
Embodiment
Please refer to Fig. 2, Fig. 2 is the synoptic diagram of external memory storage 22 its bank configuration of microprocessor of the present invention.The external memory storage 22 of microprocessor (figure does not show) is when using the memory configurations mode of memory bank exchange, the data that need in each memory bank, all need to duplicate a common area, quite expend storage space, if can reduce the size of store data in the common area, just can significantly save the space of storer.The present invention takes out the Interrupt Service Routine that the common area 24 of each memory bank of external memory storage 22 is comprised, just the common area 24 of memory bank does not comprise Interrupt Service Routine, and only externally store a Interrupt Service Routine 26 among one of them memory bank of storer, when interrupting taking place, switch to reading of data in the memory bank that stores Interrupt Service Routine 26 again, so the common area of each memory bank has just all dwindled, each relative memory bank just has more free space, also can reduce the probability that memory bank switches.For instance, the size of case of external storer 22 is the 512K byte, be divided into 8 memory banks, the size of each memory bank is the 64K byte, and each memory bank needs 10K bytes of memory device space to store the common area data, and wherein Interrupt Service Routine has just accounted for the 4K byte, so the taking-up of the Interrupt Service Routine in each common area is only stored a Interrupt Service Routine 26 the 0th page in memory bank, except the 0th page of memory bank, the free space of each database increases to the 58K byte by original 54K byte, has increased 4K* (8-1)=28K bytes of memory device space altogether.Because there be the 0th page of memory bank in 26 of Interrupt Service Routines, when so central broken hair is given birth to, microprocessor needs that the database in the work is switched to the 0th page of memory bank and makes Interrupt Process, the present invention uses a memory bank control circuit and multiplexer to cooperate the interruption generation of microprocessor and Interrupt Service Routine to carry out the end signal, when interrupt taking place, microprocessor switched in the 0th page of memory bank and carry out Interrupt Service Routine, so just can will shift out in the common area of Interrupt Service Routine by each memory bank of external memory storage as mentioned above, and only store a Interrupt Service Routine among one of them memory bank of external memory storage, detailed is described as follows.
Please refer to Fig. 3, the synoptic diagram that Fig. 3 is connected with external memory storage 22 for microprocessor 20 of the present invention.The port 0 (P0) and the port 2 (P2) of microprocessor 20 are directly connected in external memory storage 22, be used for the memory bank of addressing and access external memory storage 22, the port one of microprocessor 20 (P1) is connected in external memory storage 22 via a multiplexer 24, and multiplexer 24 comprises a first input end, one second input end, an output terminal and a selecting side.The first input end of multiplexer 24 is connected in the port one of microprocessor, and when microprocessor 20 connected external memory storage 22, as page selector, just microprocessor 20 was exported the memory bank page number of external memory storage 22 by port one with port one.Second input end of multiplexer 24 is connected in a default memory bank page number signal (Set), and wherein the Yu She memory bank page number is for storing the memory bank page number of Interrupt Service Routine.The output terminal of multiplexer 24 is connected in external memory storage 22, and output terminal is sent to the memory bank page number that the signal of external memory storage 22 is used for selecting external memory storage 22.The selecting side of multiplexer 24 is connected in the output terminal (Sel) of a memory bank control circuit 23.This memory bank control circuit 23 when usual and Interrupt Service Routine carry out the state that can deliver to electronegative potential after finishing.The memory bank page number signal that multiplexer 24 is imported by first input end according to the signal output of this electronegative potential is so microprocessor 20 can switch normally and the memory bank of access external memory storage 22.But when microprocessor 20 is received interrupt request during at executive routine, memory bank control circuit 23 will be drawn high the current potential of output, representative is interrupted, the default memory bank page number signal that this moment, multiplexer 24 meetings were imported by second input end according to the noble potential signal output of memory bank control circuit 23, then the memory bank of external memory storage 22 is switched to the memory bank that stores Interrupt Service Routine, and microprocessor 20 just can read Interrupt Service Routine and make Interrupt Process.Yet, memory bank control circuit 23 interrupt taking place carrying out to Interrupt Service Routine finish before, its output can maintain the state of noble potential always, so multiplexer 24 also can be exported the default memory bank page number signal of being imported by second input end always, just can only be in storing the memory bank of Interrupt Service Routine executive routine, when just interrupting taking place, microprocessor 20 cannot switch memory bank arbitrarily, thus, the user just must be in advance be stored in the letter formula of the required calling of Interrupt Service Routine and Interrupt Service Routine among the same memory bank.
From the above, microprocessor 20 of the present invention is when connecting the external memory storage 22 that uses the memory bank exchange, the Interrupt Service Routine of the common area of each memory bank of external memory storage 22 is taken out, and only store a Interrupt Service Routine in one of them memory bank, in addition and connect multiplexer 24 between the pin and external memory storage 22 of microprocessor 20 as page selector, memory bank control circuit 23 is carried out the end signal according to the interruption generation signal and the Interrupt Service Routine of microprocessor 20, to provide multiplexer 24 to select to export to the memory bank page number signal of external memory storage 22, memory bank control circuit 23 is when the state of electronegative potential, the memory bank page number signal that multiplexer 24 output microprocessors 20 are selected, but when interrupting taking place before Interrupt Service Routine is carried out end, memory bank control circuit 23 can be exported noble potential, this moment, multiplexer 24 just can be exported default memory bank page number signal, microprocessor 20 is switched in the memory bank that stores Interrupt Service Routine make Interrupt Process.
Compared to known technology, microprocessor provided by the present invention is when taking place to interrupt, utilize multiplexer to switch memory bank, so the Interrupt Service Routine that is present among the common area of each memory bank can be shifted out, reduce the common area occupation space, increased the free space of each memory bank on the one hand, also reduced the chance of switching memory bank on the other hand, the efficient of microprocessor access external memory storage is provided.When known technology expands external memory storage in the mode of using the memory bank exchange, must in each memory bank, all duplicate the common area data that portion contains Interrupt Service Routine, and Interrupt Service Routine has accounted for the very big part of common area, the suitable space of waste storer, the space that the present invention then can the more efficient use storer.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claims of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (10)
1. the microcontroller of an extendible memory bank, it comprises:
One microprocessor;
A plurality of memory banks are connected in this microprocessor, are used for storage data and program, are also storing Interrupt Service Routine in these a plurality of memory banks;
One memory bank control circuit is connected in this microprocessor, is used for according to the interruption of microprocessor source and Interrupt Service Routine taking place and carries out and finish signal or producing one according to the interruption dependent instruction of this microprocessor institute access selects signal; And
One multiplexer is connected between this microprocessor and these a plurality of memory banks, and it comprises:
One first input end is connected in first output terminal of this microprocessor, is used for receiving the page that is sent by this microprocessor and selects signal, and it is to be used for selecting memory bank that this page is selected signal;
One second input end is connected in second output terminal of this microprocessor, is used for receiving one and can be adjusted or the predetermined page is selected signal, and it is corresponding to the memory bank with this Interrupt Service Routine;
Input end more than the 3rd is used for receiving different being adjusted or predetermined page selection signal, and it is corresponding to the memory bank with different Interrupt Service Routines; And
One selecting side, be connected in the output terminal of this memory bank control circuit, the page that is sent by first output terminal of this microprocessor according to the output of this selection signal selects that second output terminal of signal or this microprocessor sends is adjusted or the predetermined page is selected signal, makes that this microprocessor can be to the memory bank access data that stores this Interrupt Service Routine when interrupting taking place.
2. microcontroller as claimed in claim 1, wherein this microprocessor is the microprocessor of MCS series.
3. microcontroller as claimed in claim 1, wherein these a plurality of memory banks have extendibility, but and the capacity of a plurality of memory banks greater than the space of the single instruction addressing of this microcontroller.
4. microcontroller as claimed in claim 1, wherein source and Interrupt Service Routine can take place according to the multiple interruption of this microprocessor and carry out the signal that finishes or produce multiple selection signal according to the interruption dependent instruction of this microprocessor institute access in this memory bank control circuit.
5. microcontroller as claimed in claim 1 wherein all contains a common area in each memory bank, does not comprise Interrupt Service Routine in this common area.
6. microcontroller as claimed in claim 1, wherein this Interrupt Service Routine letter formula of calling out is to be stored among the same memory bank with this Interrupt Service Routine.
7. an access is connected in the method for the storer of a microprocessor, and this storer comprises a plurality of memory banks, and this method comprises:
(a) provide a multiplexer, be connected between this microprocessor and these a plurality of memory banks;
(b) Interrupt Service Routine is stored in one of them memory bank of these a plurality of memory banks;
(c) when this microprocessor interrupts, the page that uses this multiplexer to send according to first output terminal of this microprocessor selects signal to select the memory bank of access;
(d) when this microprocessor takes place to interrupt, use this multiplexer according to being adjusted of sending of second output terminal of this microprocessor or the predetermined page selects signal to select the memory bank of this storage Interrupt Service Routine of access.
8. method as claimed in claim 7, wherein this microprocessor is the microprocessor of MCS series.
9. method as claimed in claim 7, it also comprises a common area that does not comprise Interrupt Service Routine is stored in each memory bank.
10. method as claimed in claim 7, it comprises the letter formula that this Interrupt Service Routine is called out in addition and is stored among the same memory bank.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03110479 CN1261863C (en) | 2003-04-16 | 2003-04-16 | Microcontroller of data stored in storage by multi appliance access |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 03110479 CN1261863C (en) | 2003-04-16 | 2003-04-16 | Microcontroller of data stored in storage by multi appliance access |
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| CN1538289A CN1538289A (en) | 2004-10-20 |
| CN1261863C true CN1261863C (en) | 2006-06-28 |
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| CN 03110479 Expired - Fee Related CN1261863C (en) | 2003-04-16 | 2003-04-16 | Microcontroller of data stored in storage by multi appliance access |
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