CN115705298A - Storage device - Google Patents

Abstract

The application relates to the technical field of storage equipment and discloses storage equipment. The storage device comprises a processor and a memory, wherein the memory is connected with the processor and comprises a plurality of storage arrays, the memory is configured into a plurality of intervals, each interval comprises a preset number of storage arrays, and the preset number is less than or equal to the maximum number of the storage arrays which can be covered by a physical address; the memory stores a mapping table, and the physical address information in the mapping table is stored in a mode of setting bit size. By the mode, the whole capacity of the storage device can be increased, the storage device has good read-write performance, the occupation of physical address information on the storage space is not increased, and the design difficulty of the storage device is reduced.

Description

Storage device

Technical Field

The present application relates to the field of storage device technologies, and in particular, to a storage device.

Background

With the advancement of technology, a storage device with larger and larger capacity is a future development trend, which means that a physical address stored in a fixed bit manner often cannot cover all storage arrays in the storage device, thereby restricting the development of the storage device.

Disclosure of Invention

The technical problem that this application mainly solved provides a storage device, can make storage device's whole capacity increase, and storage device has good read-write performance, and need not increase the occupation of physical address information to storage space, reduces the design degree of difficulty to storage device.

In order to solve the above problem, a technical solution adopted by the present application is to provide a storage device, including: a processor; the memory is connected with the processor and comprises a plurality of storage arrays, the memory is configured into a plurality of intervals, each interval comprises a preset number of storage arrays, and the preset number is smaller than or equal to the maximum number of the storage arrays which can be covered by the physical address; the memory stores a mapping table, and the physical address information in the mapping table is stored in a mode of setting bit size.

The processor is used for receiving a data reading request of the external control equipment; determining a target interval according to the logic address information in the data reading request; determining physical address information corresponding to the logical address information from the target interval; and reading corresponding data according to the physical address information.

The processor is further configured to obtain a target interval by using the logical address information and the number of the storage arrays corresponding to each interval.

The processor is further used for determining a target mapping table from the target interval; physical address information corresponding to the logical address information is determined from the target mapping table.

The processor is used for receiving a data writing request of the external control equipment; determining a target interval according to the data writing request; generating target physical address information corresponding to data to be written; writing data to be written into a storage array corresponding to the target physical address information; and generating a mapping relation between the logical address information corresponding to the data to be written and the target physical address information.

The processor is further used for acquiring a first capacity of data to be written; acquiring a free storage array in each interval; and when the second capacity of any free storage array is larger than or equal to the first capacity, determining the interval corresponding to the free storage array as a target interval.

Wherein the processor is further configured to determine a target storage array in the target interval according to the first capacity; target physical address information is generated from the target storage array.

The processor is further configured to obtain the number of target storage arrays and generate a number of pieces of target physical address information.

Wherein the set bit size is 32 bits.

The capacity of the storage array corresponding to each physical address is 4kB or 8kB or 16kB.

The beneficial effect of this application is: different from the prior art, the storage device provided by the application comprises a processor and a memory, wherein the memory is connected with the processor and comprises a plurality of storage arrays, the memory is configured into a plurality of intervals, each interval comprises a preset number of storage arrays, and the preset number is less than or equal to the maximum number of the storage arrays which can be covered by a physical address; the memory stores a mapping table, and the physical address information in the mapping table is stored in a mode of setting bit size. The storage device divides the storage array into sections, and under the premise of not changing the capacity of each storage array, the physical address information stored in the set bit size can represent the storage array according to each section, so that the whole capacity of the storage device can be increased, the storage device has good read-write performance, the occupation of the physical address information on the storage space is not increased, and the design difficulty of the storage device is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:

FIG. 1 is a schematic structural diagram of an embodiment of a memory device provided herein;

FIG. 2 is a schematic flow chart diagram illustrating one embodiment of a data read from a storage device provided herein;

FIG. 3 is a schematic flow chart diagram illustrating one embodiment of a data write for a storage device provided herein;

fig. 4 is a schematic structural diagram of another embodiment of a storage device provided in the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

With the advance of technology, a storage device with larger capacity is a future development trend, that is, a physical address is stored in a fixed bit manner, and the physical address cannot always cover a storage array in the whole storage device. Based on this, the following technical solutions are proposed in the present application.

First, the physical address can cover more storage arrays by increasing the capacity of each storage array, for example, changing the current capacity of each storage array from 4kB (kilobyte) to 8kB. 1kb =1024b (bytes).

And secondly, changing the storage mode of the physical address information to enable the storage device to cover a wider storage array of the storage device, wherein the storage array is changed into 64 bits if the storage array is 32 bits originally.

Thirdly, the present application also proposes the following solution.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a memory device provided in the present application. The storage device 100 includes a processor 10 and a memory 20.

The memory 20 is connected to the processor 10.

The memory 20 of the memory device 100 includes a plurality of memory arrays 211. The memory 20 is configured as a plurality of partitions 21, each partition 21 including a predetermined number of memory arrays 211, the predetermined number being less than or equal to a maximum number of memory arrays that can be covered by a physical address. The physical address is used to represent each memory array. For example, each storage array has a capacity of 4kB, and one physical address may represent a 4kB storage array.

The memory 20 of the storage device 100 stores a mapping table, and the physical address information in the mapping table is stored in a manner of setting a bit size. For example, the bit can be 32bit and 64bit.

For example, the capacity of the storage device 100 is 16TB (Terabyte), 1tb =2 ⁴⁰ B. The capacity of each memory array 211 is 4kB, the number of memory arrays 211 is 2 ³² . I.e. need 2 ³² A physical address. Since the numbers are expressed in the storage device 100 by machine language, each piece of physical address information can be expressed by 32 bits and stored in the storage device 100.

At this time, if the capacity of the memory device 100 exceeds 16TB, the current physical address cannot cover all of the memory array 211. Therefore, according to the above scheme, the memory 20 of the memory device 100 is configured into a plurality of sections 21, each section 21 includes a preset number of memory arrays 211, that is, the capacity corresponding to each section 21 can be 16TB at maximum.

Compared with the method of increasing the capacity of each storage array 211, the method of directly increasing the capacity of the storage array 211 can greatly reduce the original read-write performance, such as 4K read-write performance, between the host side and the storage device 100. On the premise of not changing the capacity of the storage array 211, the scheme proposed in this embodiment performs partition management on the storage array 211 to use the physical address information with a set bit size to represent the storage array 211 in each partition 21, so that the large-capacity storage device 100 can still maintain the original read-write performance, such as 4K read-write performance, with the host.

For example, the following steps are carried out:

the capacity of each storage array 211 in the storage device 100 is 4kB, which enables the storage device 100 to have good 4K read-write performance with the host side. If the capacity of the memory device 100 increases, the capacity of each memory array 211 is changed to 8kB in order to allow more memory arrays 211 to be covered by physical addresses. When the storage device 100 interacts with the host, the data read and written each time is read and written by using 8kB as a read and write unit, and the 4K read and write performance is directly lost.

However, according to the scheme provided by this embodiment, when the capacity of the storage device 100 is increased, in order to enable the physical address to cover more storage arrays 211, the storage arrays 211 are partitioned so that the storage arrays 211 in each partition 21 can be covered by the physical address, and the capacity of each storage array 211 is still kept to be 4kB. When the storage device 100 interacts with a host, data read and written each time is read and written by taking 4kB as a read and write unit, and still has good 4K read and write performance.

Compared with the storage manner of changing the physical address information, this manner enables the physical address to cover more storage arrays 211, but the storage manner of higher bit width enables the physical address information to occupy larger storage, which reduces the availability of the storage space of the storage apparatus 100. In the scheme proposed in this embodiment, the storage array 211 is subjected to partition management, and the physical address information with a set bit size is used to represent the storage array in each partition without changing the storage manner of the physical address information, so that the utilization rate of the storage space is not reduced.

For example, the following steps are carried out:

the capacity of each storage array 211 in the storage device 100 is 4kB, which enables the storage device 100 to have good 4K read-write performance with the host side. When the capacity of the storage apparatus 100 increases, the storage method of the physical address information is changed so that the physical address can cover more storage arrays 211, in order to cover more storage arrays 211. For example, change 32bit to 64bit. Physical address standing horse can cover 2 ³² The memory array 211 becomes overlay 2 ⁶⁴ And a memory array 211. However, the storage manner of the physical address information with a higher bit width occupies more storage space, that is, occupies more storage array 211. Further, less storage space is available for the storage device 100.

However, according to the solution provided in this embodiment, when the capacity of the storage device 100 is increased, in order to enable a physical address to cover more storage arrays 211, the storage arrays 211 are partitioned, and the storage arrays 211 of each partition can be covered by the physical address without changing the storage manner of the physical address information.

With the above-mentioned storage device 100 comprising 2 ⁶⁴ The individual memory arrays 211 are illustrated, and all of the memory arrays 211 can be represented by 64-bit memory physical addresses. In the embodiment, 32-bit storage physical addresses are adopted to represent the storage array 211 in the partition mode, and 2 can be represented in the same way ⁶⁴ And a memory array 211. The difference lies in that the physical address information is stored in a 32-bit manner, and occupies less storage space compared with the physical address information stored in a 64-bit manner, so that the space utilization rate of the storage device 100 can be improved.

In summary, in order to solve the problem that the physical address of the mass storage device 100 cannot cover all the storage arrays 211, the present embodiment divides the storage arrays 211 of the storage device 100 such that the physical address represents the storage arrays 211 according to the division. On the premise of not changing the capacity of each storage array 211, the physical address information stored in a set bit size can represent the storage array 211 according to each section 21, so that the overall capacity of the storage device can be increased, the storage device 100 has good read-write performance, the occupation of the physical address information on the storage space is not increased, and the design difficulty of the storage device 100 is reduced.

Based on the storage device 100, the following scheme is proposed in the present application to solve the problem of data read/write corresponding to the storage device 100.

Data reading is explained in connection with fig. 2:

the storage device 100 is connected with an external control device for data interaction.

The external control apparatus generates a data read request and transmits the data read request to the storage apparatus 100. After receiving a data request sent by an external control device, the processor 10 of the storage device 100 determines a target interval according to the logical address information in the data read request, then determines physical address information corresponding to the logical address information from the target interval, and then reads corresponding data according to the physical address information.

After the memory array of the memory device 100 is partitioned into the memory array 211 according to the above-mentioned technical solution, the physical address information is also distributed according to the partitions. Therefore, when data is read, after a specific section 21 needs to be determined, the corresponding physical address information can be determined from the mapping table of the section 21, then the storage array 211 is determined according to the physical address information, and then the data on the storage array 211 is read.

In some embodiments, the target interval 21 may be obtained by the processor 10 using the number of the storage arrays 211 corresponding to each interval 21 and the logical address information to obtain the target interval 21. In this application, the memory device 100 is divided into sections according to a fixed capacity, that is, the capacity is fixed, and the number of the memory arrays 211 is also fixed. If the capacity of the storage device 100 is 100TB, 10 sections 21 are obtained by dividing the sections by 10 TBs. After the logical address information is obtained, the logical address information may be processed to determine the section to which the logical address information corresponds. And if the logic address information is determined to be in the 5 th interval, storing the logic address information in the storage array corresponding to the 5 th interval.

In some embodiments, the processor 10 is further configured to determine a target mapping table from the target interval 21; physical address information corresponding to the logical address information is determined from the target mapping table.

In the above manner, the data reading method of the mass storage device 100 after the division of the storage array 211 is described.

Data writing is explained with reference to fig. 3:

the external control apparatus generates a data write request and transmits the data write request to the storage apparatus 100. After receiving a data write request from an external control device, the processor 10 of the storage device 100 determines a target interval according to the data write request, then generates target physical address information corresponding to data to be written, then writes the data to be written into a storage array corresponding to the target physical address information, and then generates a mapping relationship between logical address information corresponding to the data to be written and the target physical address information.

After the storage array of the storage device 100 is partitioned according to the above technical solution, the physical address information is also distributed according to the partitions. Therefore, when data is written, it is necessary to specify a specific section 21, and then the memory array 211 is specified from the section 21 to write data. Generating target physical address information corresponding to the data to be written, writing the data to be written into the storage array 211 corresponding to the target physical address information, generating a mapping relation between the logical address information corresponding to the data to be written and the target physical address information, and storing the mapping relation in a mapping table.

In some embodiments, the processor 10 is further configured to obtain a first capacity of data to be written; acquiring a free storage array 211 in each interval 21; when the second capacity of any free storage array 211 is greater than or equal to the first capacity, the section 21 corresponding to the free storage array 211 is determined as the target section.

Specifically, the number of storage arrays 211 required by it may be determined according to the first capacity of data to be written. If the capacity of the storage array 211 is 4kB and the data to be written is 20kB, 5 storage arrays 211 are needed to store the data to be written.

In an application scenario, the logical address information and the write length of the data to be written may be determined, and which interval 21 specifically belongs to is calculated according to the interval length of each interval 21. After the interval 21 is determined, the free memory array 211 in the interval 21 is searched. And after the data to be written is written into the acquired idle storage array 211, updating the corresponding address mapping table information.

In some embodiments, processor 10 is further configured to determine a target storage array 211 in target interval 21 based on the first capacity; target physical address information is generated from target storage array 211.

The target storage array 211 is determined from the free storage arrays 211.

For example, it is determined that 5 storage arrays 211 are required according to the first capacity, and 10 free storage arrays 211 are also required. The first 5 free storage arrays 211 are determined to be the target storage arrays 211. The target physical address information is then generated from the target storage array 211.

In some embodiments, processor 10 is further configured to obtain a number of target storage arrays 211 and generate a corresponding number of target physical address information. And then mapping the target physical address information and the logic address information of the data to be written correspondingly and storing the mapping table. Wherein the physical address information is stored in a set bit size.

In some embodiments, the bit size is set to 32 bits. The capacity of the storage array 211 corresponding to each physical address information may be 4kB, or 8kB, or 16kB. Specifically, the capacity of the memory array 211 is determined according to the actual memory device 100.

In an application scenario, as the capacity of the storage device 100 is larger, the divided sections 21 are more and more, and at this time, a large number of sections 21 are not managed well, and the following solution is proposed in the present application.

Each interval 21 is divided into segments, if 100 intervals 21 exist, 10 intervals are divided into one segment, and corresponding segment numbers are set. There would be segment numbers 1-10. Each segment number stores a mapping table of each interval, i.e. one segment number corresponds to 10 mapping tables.

When data is read, the corresponding segment number is determined according to the logical address information, and after the segment number is determined, the corresponding mapping table is determined. The corresponding physical address information is then determined from the mapping table, and the data on the corresponding storage array 211 is then read based on the physical address information.

When data is written, a section 21 having the capacity storage capability is determined based on the capacity of the write data, and the number of the section is determined. The memory array 211 on the extent 21 is then determined and data is then written onto the memory array 211. The logical address information and the physical address information are mapped and stored in a mapping table corresponding to the section 21.

In the above manner, the data writing method of the mass storage device 100 after the division of the storage array 211 section is described.

In another application scenario, referring to fig. 4, the storage device 100 is an SSD (Solid State Disk) in fig. 4. The SSD is configured with a storage array in the form of a flash memory. As shown in fig. 4, the SSD, after being manufactured according to the above technical solution, has a segment number 1, a segment number 2, and a segment number 3, up to a segment number n, where n is an integer and is greater than 3. There are several Mapping tabs for each segment number, and there are several PPAs (Physical Page addresses) in each Mapping Tab, and then each PPA points to a storage array, such as DIE0 shown in fig. 4. The capacity of the storage array may be 4kB or 8kB or 16kB.

In summary, according to any of the above technical solutions provided in the present application, under the condition that the capacity of the storage device 100 is increasingly larger, the physical address information stored in a set bit size can represent the storage array 211 according to each interval 21 without changing the capacity of each storage array 211, so that the overall capacity of the storage device 100 can be increased, the storage device has good read-write performance, and the design difficulty of the storage device is reduced without increasing the occupation of the physical address information on the storage space.

The above description is only an embodiment of the present application, and is not intended to limit the scope of the present application, and all equivalent structures or equivalent processes performed by the present application and the contents of the attached drawings, which are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims (10)

1. A storage device, comprising:

a processor;

a memory connected to the processor, the memory including a plurality of storage arrays, the memory being configured into a plurality of intervals, each interval including a preset number of storage arrays, the preset number being less than or equal to a maximum number of the storage arrays that can be covered by a physical address; the memory is stored with a mapping table, and the physical address information in the mapping table is stored in a mode of setting bit size.

2. The storage device of claim 1,

the processor is used for receiving a data reading request of the external control equipment; determining a target interval according to the logic address information in the data reading request; determining physical address information corresponding to the logical address information from the target interval; and reading corresponding data according to the physical address information.

3. The storage device of claim 2,

the processor is further configured to obtain the target interval by using the logical address information and the number of storage arrays corresponding to each interval.

4. The storage device of claim 3,

the processor is further configured to determine a target mapping table from the target interval; determining the physical address information corresponding to the logical address information from the target mapping table.

5. The storage device of claim 1,

the processor is used for receiving a data writing request of the external control equipment; determining a target interval according to the data writing request; generating target physical address information corresponding to data to be written; writing the data to be written into a storage array corresponding to the target physical address information; and generating a mapping relation between the logical address information corresponding to the data to be written and the target physical address information.

6. The storage device of claim 5,

the processor is further configured to obtain a first capacity of the data to be written; acquiring a free storage array in each interval; and when the second capacity of any idle storage array is greater than or equal to the first capacity, determining the interval corresponding to the idle storage array as the target interval.

7. The storage device of claim 6,

the processor is further configured to determine a target storage array in the target interval according to the first capacity; and generating the target physical address information according to the target storage array.

8. The storage device of claim 7,

the processor is further configured to obtain the number of the target storage arrays, and generate the number of the target physical address information.

9. The storage device of claim 1,

the set bit size is 32 bits.

10. The storage device of claim 1,

the capacity of the storage array corresponding to each physical address is 4kB or 8kB or 16kB.

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