CN1259720C - Separate-gate flash memory unit and its making process - Google Patents
Separate-gate flash memory unit and its making process Download PDFInfo
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- CN1259720C CN1259720C CN02103511.3A CN02103511A CN1259720C CN 1259720 C CN1259720 C CN 1259720C CN 02103511 A CN02103511 A CN 02103511A CN 1259720 C CN1259720 C CN 1259720C
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- memory device
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- 238000000034 method Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000000725 suspension Substances 0.000 claims abstract description 36
- 238000002347 injection Methods 0.000 claims abstract description 21
- 239000007924 injection Substances 0.000 claims abstract description 21
- 239000002784 hot electron Substances 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 230000009471 action Effects 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 239000012212 insulator Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 230000000694 effects Effects 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 230000005684 electric field Effects 0.000 description 11
- 230000004888 barrier function Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- GWFXMCXJFOEMNQ-UHFFFAOYSA-N [O].O=[N] Chemical compound [O].O=[N] GWFXMCXJFOEMNQ-UHFFFAOYSA-N 0.000 description 1
- WDBZLBMLUXGRIQ-UHFFFAOYSA-N [O].[N].[Si]=O Chemical compound [O].[N].[Si]=O WDBZLBMLUXGRIQ-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
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Abstract
The present invention relates to a separate-gate quick-flashing memory device and a manufacturing method thereof. The device comprises a substrate, a suspension joint gate electrode, a control gate electrode and an injection nib nozzle, wherein the suspension joint gate electrode is positioned above the substrate and is insulated with the substrate, the control gate electrode is positioned above the suspension joint gate electrode and is insulated with the suspension joint gate electrode, the injection tip nozzle is connected with the substrate and is close to the control gate electrode, and hot electrons and the substrate are formed into the inclined direction to be injected in the suspension joint gate electrode by the injection tip nozzle during writing action.
Description
Technical field
The present invention relates to the manufacturing technology of integrated circuit, especially a kind of the reduction writes bias voltage and quickening writes and the split-gate flash memory device and the manufacture method thereof of the speed of erasing.
Background technology
Fig. 1 has shown the profile of a traditional split-gate flash memory device.Comprising a silicon base 11, be stacked over suspension joint grid 13 on the silicon base 11, control grid 15 and select grid 19.Between each grid, have insulating barrier 12,14,16,18 and clearance wall 17 respectively.Insulating barrier 12,18 and clearance wall 17 are silicon oxide layer, and insulating barrier 14 then is oxygen-nitrogen-silicon oxide layer (ONO), and insulating barrier 16 is a silicon nitride layer.In addition, have source/drain doping region 111 in the silicon base 11, it is connected to carry out the action that memory contents reads with a connector 20.
Above-mentioned traditional split-gate flash memory device is when carrying out write activity, system utilizes the electric field that voltage causes between a among Fig. 1, b, c at 3, in substrate 11, produce hot electron (hot electron), and collect, and make the suspension joint grid have different current potentials with the store digital data by the suspension joint grid.Wherein, the voltage of a, b point-to-point transmission system is in order to the generation hot electron, and the voltage of a, c point-to-point transmission system is in order to become to making those hot electrons to enter the suspension joint grid.In addition, when erasing, also utilize the voltage between a, c to become to making the electronics that before has been stored in the suspension joint grid to flow in the substrate 11.
Yet, because higher writing speed need possess high hot electron output capacity simultaneously and collection rate just can be reached, and in above-mentioned traditional split-gate flash memory device, (b → a and a → c) are vertical mutually to influence the direction of an electric field of hot electron output capacity and collection rate, the voltage difference that therefore must increase simultaneously between c, a just can be reached with the voltage difference between a, b, and meaning promptly needs add a high voltage controlling on the grid 15.So high voltage needs more electric charge circuit (charge pump circuit) of heap of stone, and causes circuit area to increase.Therefore, when making traditional split-gate flash memory device, must between writing speed and bias value, circuit area, make trade-offs, can't get both.
Summary of the invention
In order to address the above problem, the invention provides a kind of split-gate flash memory device, the electric field of its decision hot electron generation rate can produce a component on decision hot electron collection rate direction of an electric field, under same writing speed condition, the bias value that its control grid needs is lower.
A purpose of the present invention is to provide a kind of split-gate flash memory device, comprises a substrate, a suspension joint grid, a control grid and an injection sharp nozzle.Wherein, the suspension joint grid is positioned at this substrate top and insulate with this substrate.The control grid be positioned at this suspension joint grid top and with this suspension joint gate insulator.Injection sharp nozzle then is connected with this substrate and contiguous this suspension joint grid, and when carrying out write activity, hot electron becomes an oblique angle direction to inject this suspension joint grid via this injection sharp nozzle with this substrate.
Another object of the present invention is to provide a kind of manufacture method of split-gate flash memory device, may further comprise the steps: a substrate is provided.The suspension joint grid of formation one and this substrate insulation in this substrate.The control grid of formation one and this suspension joint gate insulator on this suspension joint grid.In this substrate, form an injection sharp nozzle that is connected and is close to this suspension joint grid with this substrate.
By this, in the present invention, form oblique injection sharp nozzle in substrate, hot electron is produced with the direction of substrate bevel with one in sharp mouth, this produces thermionic electric field will produce component on the direction of collecting the hot electron electric field, help thermionic collection, therefore, reduced the bias value that the control grid needs.
Below, with regard to the embodiment of graphic explanation a kind of split-gate flash memory device of the present invention and manufacture method thereof.
Description of drawings
Fig. 1 has shown the profile of a traditional split-gate flash memory device;
Fig. 2 A to Fig. 2 G ' has shown the manufacturing process of split-gate flash memory device in one embodiment of the invention.
Symbol description:
11,21-silicon base; 12,22-gate oxidation silicon layer;
13,23-suspension joint grid; 14,24-oxygen-nitrogen-silicon oxide layer;
15,25-control grid; 16,26-silicon nitride layer;
17,28-clearance wall; 271,272-groove;
19,32-selects grid; 20,29-connector;
The 291-injection sharp nozzle; The 30-photoresist layer;
311,312,313-oxide layer.
Embodiment
Fig. 2 A to Fig. 2 G has shown the manufacturing process of split-gate flash memory device in the present embodiment.
At first, shown in Fig. 2 A, provide a silicon base 21.
Then, shown in Fig. 2 B, on silicon base 21, deposit a grid oxic horizon 22, a polysilicon layer 23 as the suspension joint grid, one oxygen-nitrogen-oxide layer 24, a polysilicon layer 25 and a silicon nitride layer 26 as the control grid in regular turn.
Then, shown in Fig. 2 C, etching is stacked over the sedimentary deposit 22,23,24,25 and 26 on the silicon base 21, forms the groove 271 and 272 that exposes silicon base 21 to the open air, and implants the usefulness of dopant ion as source/drain doping region 211 in the silicon base below groove 271 21.
Come again,, utilize again and eat-back and form the clearance wall 28 that is attached to groove 271,272 sidewalls as deposition one oxide layer in Fig. 2 groove that D is shown in 271,272.Then, in groove 271,272, deposit a polysilicon layer 29 again.
Then, shown in Fig. 2 E, depositing a photoresist layer 30, and utilize exposure and step display that the photoresist layer 30 of groove 272 tops is removed, is shielding with photoresist layer 30, polysilicon layer in the groove 272 29 is carried out etching, because groove 272 is high wide-dark than, make the residual polysilicon layer 291 that a sharp mouth shape is arranged in the groove 272, as the usefulness of injection sharp nozzle, when writing or erase, hot electron is incited somebody to action injection sharp nozzle 291 injections thus or is left suspension joint grid 23.29 usefulness of polysilicon layer in the groove 271 as the connector of connection source/drain electrode 211.
Come again, shown in Fig. 2 F, deposit an oxide layer and forming oxide layer 311,312 and 313 on the connector 29 and above groove 272 intermediate gap walls 28 and injection sharp nozzle 291 sides and the silicon base 21.
At last, shown in Fig. 2 G, deposition one is the polysilicon layer 32 of grid alternatively.
Fig. 2 G ' shows the partial enlarged drawing of injection sharp nozzle 291 in the present embodiment.Shown in Fig. 2 G, because the existence of injection sharp nozzle 291, make the position change of in traditional split-gate flash memory device a, b, c.In order to produce 21 one-tenth one oblique angles of thermionic direction of an electric field b → a and substrate, then parallel with substrate 21 in order to collect thermionic direction of an electric field a → c.So, produce thermionic electric field and can on the hot electron collecting direction, produce a component, make that thermionic collection is not the electric field that only depends on c, a point-to-point transmission voltage difference to be produced, and be attended by the subsidy of b, a point-to-point transmission electric field.Therefore, under identical writing speed condition, the required just more traditional split-gate flash memory device of current potential of c point comes lowly, and meaning is that the needed bias value of its control grid is lower.
In addition, when erasing, because substrate 21 and injection sharp nozzle 291 common jiaos of surrounding suspension joint grids 23, make to be stored in that electronics in the suspension joint grid 23 is easier to be left suspension joint grid 23 and enter in the substrate 21.So, also improved the speed of erasing.
Comprehensively above-mentioned, in the present invention, because an injection sharp nozzle that is connected with substrate is provided, has changed hot electron and injected and the direction of leaving the suspension joint grid, make to help thermionic collection efficiency, so just reduced the needed bias value of control grid in order to produce thermionic bias voltage.Therefore, under identical bias value condition, the present invention can provide the speed that writes faster and erase; And identical write and the velocity conditions of erasing under, the present invention can use lower bias value.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (11)
1. a split-gate flash memory device is characterized in that, comprising:
One substrate;
One suspension joint grid is positioned at above this substrate and with this substrate and insulate;
One control grid, be positioned at this suspension joint grid top and with this suspension joint gate insulator;
One source/drain region is arranged in this substrate; And
One injection sharp nozzle is connected and contiguous this control grid with this substrate, and when carrying out write activity, hot electron becomes an oblique angle direction to inject this control grid via this injection sharp nozzle with this substrate.
2. split-gate flash memory device as claimed in claim 1 is characterized in that, also comprises:
One connector, be connected with this source/drain electrode and with this control grid and suspension joint gate insulator.
3. split-gate flash memory device as claimed in claim 1 is characterized in that: comprise that also one selects grid, be positioned at above this control grid and with this control gate insulator.
4. split-gate flash memory device as claimed in claim 1 is characterized in that: this substrate is a silicon base.
5. split-gate flash memory device as claimed in claim 1 is characterized in that: it is polysilicon layer that this suspension joint grid layer, this control grid layer and this inject sharp mouth.
6. split-gate flash memory device as claimed in claim 1 is characterized in that: when erasing action, the electronics in this control grid also injects this substrate via this injection sharp nozzle.
7. the manufacture method of a split-gate flash memory device is characterized in that, may further comprise the steps:
One substrate is provided;
The suspension joint grid of formation one and this substrate insulation in this substrate;
The control grid of formation one and this suspension joint gate insulator on this suspension joint grid;
In this substrate, form one source/drain doping region; And
In this substrate, form an injection sharp nozzle that is connected and is close to this control grid with this substrate.
8. the manufacture method of split-gate flash memory device as claimed in claim 7 is characterized in that, and is further comprising the steps of:
On this source/drain doping region, form a connector that is connected with this source/drain doping region.
9. the manufacture method of split-gate flash memory device as claimed in claim 7 is characterized in that, and is further comprising the steps of:
Formation one is controlled the selection grid of gate insulator with this on this control grid.
10. the manufacture method of split-gate flash memory device as claimed in claim 7, it is characterized in that: this substrate is a silicon base.
11. the manufacture method of split-gate flash memory device as claimed in claim 7 is characterized in that: it is polysilicon layer that this suspension joint grid layer, this control grid layer and this inject sharp mouth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02103511.3A CN1259720C (en) | 2002-02-05 | 2002-02-05 | Separate-gate flash memory unit and its making process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02103511.3A CN1259720C (en) | 2002-02-05 | 2002-02-05 | Separate-gate flash memory unit and its making process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1437260A CN1437260A (en) | 2003-08-20 |
| CN1259720C true CN1259720C (en) | 2006-06-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN02103511.3A Expired - Lifetime CN1259720C (en) | 2002-02-05 | 2002-02-05 | Separate-gate flash memory unit and its making process |
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| Country | Link |
|---|---|
| CN (1) | CN1259720C (en) |
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2002
- 2002-02-05 CN CN02103511.3A patent/CN1259720C/en not_active Expired - Lifetime
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| Publication number | Publication date |
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| CN1437260A (en) | 2003-08-20 |
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Granted publication date: 20060614 |