CN1254989A - Scannable latch circuit for providing scan output from it and its method - Google Patents
Scannable latch circuit for providing scan output from it and its method Download PDFInfo
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Abstract
A latch circuit (10) includes a feedback path which is isolated from a circuit critical path (12). A scan input component (22) is coupled to the feedback path for providing scan test data to the latch circuit (10). A scan output component (23) may also be coupled to the feedback path for providing a separate scan out signal.
Description
The application relates to and is numbered 08/790,259 U.S. Patent application, it applies on January 27th, 1997, name be called be the ripple domino logic latch structure (LATCH STRUCTURE FORRIPPLE DOMINO LOGIC), its disclosure is incorporated herein with for referencial use.Interests of this application early are claimed 35U.S.C.Section 120 times.
The present invention relates to semiconductor integrated circuit, relate in particular to the latch cicuit that can be subjected to sweep test.
Conductor integrated circuit device can be used to provide the failure diagnosis test of simplification.Provide a kind of designing technique of this test to be called scan path design (scan path design).In the scan path design, circuit element is set to comprise a series of coupling (linked) shift registers that are used for the diagnostic test purpose.Bit transition route through these coupling shift registers is called scan path.The bit transition operation is used for providing the diagnostic test data continuously to each coupling circuit element.
Each circuit element comprises the routine data input and the data output end of one scan input and circuit element in the scan path.In the sweep test operating process of circuit element, the operate as normal of inhibit circuit element.Along with can carrying out sweep test, but the signal that imposes on common scanning circuit element scan input produces a corresponding scanning output signal at the data output end of circuit element.Also the scanning output end that can open at one minute provides the scanning output signal.The signal unanimity that should participant produces by the scanning output signal that scanning produced of circuit element response signal form by the circuit normal running.The circuit element fault that produces prediction scanning output signal demonstrates the fault of circuit element.
Although the performance of scan test circuit element has been simplified diagnostic test in the integrated circuit, the scan path design has some shortcomings.A shortcoming is that the additional scanning test circuit is influential to the circuit element performance of operate as normal.The scan test circuit relevant with a special circuit element can increase sizable electric capacity to the crucial path of circuit element.The electric capacity of this increase causes the decline significantly of circuit element performance in the operate as normal.
An object of the present invention is to provide a kind of latch cicuit that scans, wherein in operate as normal, the additional scanning circuit can not reduce the performance of this circuit basically.Another object of the present invention provides the method that is used for providing from a latch cicuit scanning output, and this method can not cause the performance under the latch cicuit operate as normal to reduce basically.
Latch cicuit according to the present invention applies scanning input data by a feedback network, and the crucial path of this feedback network and latch cicuit is isolated.The meaning of " isolation " is in this case, and feedback network directly is not connected to the crucial path of circuit.Signal on the feedback network is not applied directly on the crucial path of circuit, but can be used to the signal on the crucial path of control circuit.The one scanning output signal of separating is also preferably derived by the signal in the latch cicuit feedback network.By the sweep test through the isolated feedback path, scanning circuit does not increase the electric capacity of the crucial path of latch cicuit basically.
This latch cicuit comprises latch data input node, and this latch data input node latchs input element through one and is connected to the data output node.This latch data output node comprises the crucial path of circuit.The feedback network that is connected to output node is preferably isolated by phase inverter and data output node by first and second isolated components.Can comprise that the scanning by gating element (pass gatearrangement) allows (enable) element responds to allow signal in a scanning, selectivity disconnects feedback network so that sweep test thus with the decoupling zero from second feedback node of first feedback node in feedback network.In operate as normal, scanning allows element first and second feedback nodes that are coupled, and makes the latch cicuit operate as normal.
When scanning allowed signal to put on scanning to allow on the element thus de first and second feedback nodes, the scanning input element that is connected to second feedback node applied the one scan input signal and latchs signal on the circuit data output node with control.That is, the scanning input element applies scanning by second feedback node in test data, and second feedback node is and the isolated point of the crucial path of latch cicuit.And preferred form of the present invention comprises the one scan output element, when carrying out sweep test, utilizes the signal on the feedback network to produce a scanning output signal of separating.Preferred scanning output element keeps scanning output signal separately by the one scan clock control with the signal that is independent of data output node place.
By applying scanning through the isolated feedback path in test data, scanning circuit does not increase electric capacity to the crucial path of latch cicuit.And, because the scanning output element has used the signal in the feedback network to produce the scanning output signal, so scan output circuit does not increase electric capacity to the crucial path of latch cicuit yet.In addition, the preferred scan clock device relevant with scanning circuit provides additional functional output when circuit does not work in scan testing mode.
Together with accompanying drawing, these and other purpose of the present invention, advantage and characteristic will become clear according to following description of preferred embodiments.
Fig. 1 is the scanned latch cicuit schematic diagram that the principle of the invention is specialized.
Fig. 2 is the sequential chart that shows by the various signals of utilization of circuit shown in Fig. 1 and generation.
With reference to Fig. 1, can scan latch cicuit 10 and comprise data input node 11, it is connected to data output node 12 by latching input element 13.Data output node 12 comprises the crucial path of the circuit of this form of the present invention.Latch cicuit 10 also comprises a feedback network, and this feedback network contains first feedback node 16 and second feedback node 17.This feedback network is isolated with data output node 12 by first isolated component 18 and second isolated component 19.For making things convenient for sweep test, latch cicuit 10 contains scanning and allows element 21 and scanning input element 22.Preferred form of the present invention also comprises one fen scanning output element of opening 23.
Latch cicuit 10 is suitable for being chosen in a kind of latch mode or scan testing mode operation down.Under latch mode, what circuit 10 will be latching to data output node 12 from the data " d " of data input node 11 latchs output " q ".Under scan testing mode, latch cicuit 10 receives scan test data through scanning input element 22, and preferably with an isolation scanning output signal " so " of coming the self-scanning output element, produces one scan test output at output node 12.Data-signal " d " and relation and other signals relevant with latch cicuit 10 of latching between the output " q " are presented in the sequential chart of Fig. 2.
Under latch mode, latch input element 13 and utilize the signal " d " of data input node 11 on data output node 12, to produce signal " q ".Diagram latchs input element 13 and comprises one by gating element, should have first p type field effect transistor (FET) and a N type FET by gating element.The leakage of N type device 27-source guiding path is connected to data output node 12 with data input node 11, and the interface unit grid is to receive latch input signal c1 simultaneously.The source of P type device 26-leakage conductance path and N type device 27 are connected in parallel between data input node 11 and the data output node 12.The grid that connects P type device 26 is with received signal c1_b, and signal c1_b is the complementary signal of latch input signal c1.Comprise that any complementary signal of describing in the present disclosure of latch input signal c1 complementary signal (c1_b) can be produced by any appropriate device, these devices comprise suitable phase inverter (not shown).
For the disclosure and following claims, transistor will be called " device "." device " speech is intended to comprise any suitable switching device, comprises diagram FETs.What those those having ordinary skill in the art will appreciate that is, utilizes FETs although the present invention is disclosed as in Fig. 1, also can realize the present invention with other transistor technologies.
Under latch mode, scanning allows element 21 that first feedback node 16 is coupled on second feedback node 17, has closed feedback network thus.Diagram scanning allows element 21 also to comprise one by gating element, and this device contains a N type device 29 and a P type device 30.P type device 30 its source-leakage conductance paths connect first and second feedback nodes 16 and 17 respectively, and its grid is subjected to connecting with received signal scanc1.N type device 29 its leakage-source guiding paths are connected between first and second feedback nodes 16 and 17, and its grid is subjected to connecting with received signal scanc1_b, and this signal is the complementary signal of signal scanc1." low " signal scanc1 and " height " signal scanc1_b place device 29 and 30 and feedback node 16 and 17 conducting states that are coupled.This signal condition can be called scanning inhibit signal state.
For present disclosure, " height " level signal comprises basically at system power supply voltage V
DdOn signal, represent first logic state." low " level signal is meant at the signal on system reference voltage or ground, represents relative logic state.
First isolated component 18 comprises a phase inverter, and this phase inverter has one to be coupled to the inverting terminal 33 of data output node 12 and to be coupled to the paraphase output 34 of first feedback node 16.Although preferred latch cicuit 10 shown in Figure 1 comprises a phase inverter, be that feedback network can be isolated with data output node 12, and does not need the signal from the data output node is carried out paraphase but those those having ordinary skill in the art will appreciate that.This noninvert device is considered to be equal to paraphase spacer assembly shown in Figure 1.
Second isolated component 19 comprises a clock phase inverter, and this circuit is made clock by latch input signal c1 and complementary signal c1_b thereof.Diagram clock phase inverter comprises the first and second P type devices, is respectively 37 and 38, and their source-leakage conductance path is connected in series in system voltage source V
DdAnd be coupled between the output node 39 of data output node 12.The gate coupled of the one P type device 37 is to second feedback node 17, and the grid of the 2nd P type device 38 is received latch input signal c1.Preferred second isolated component 19 also comprises the first and second N type devices 40 and 41 respectively, and their leakage-source guiding path is connected in series between circuit output node 39 and system reference voltage or the ground.The gate coupled of the one N type device 40 is to second feedback node 17, and the grid that connects the 2nd N type device 41 is with received signal c1_b.
Referring now to Fig. 1 and 2 the operation of circuit 10d latch mode is described.Under the latch mode, the signal of data input node 11 " d " is used at data output node 12 places generation signal " q ".In graphic form of the present invention, the device 26 and 27 that " height " level latch input signal c1 and complementary signal c1_b thereof will latch input element 13 places conducting state, allows the signal " d " at data input node 11 places to arrive on the data output node 12.Thereby latch output signal " q " is followed latch input signal " d ".What those those having ordinary skill in the art will appreciate that is, although illustrated among Fig. 1 two devices by gating element to be used for data passes with node 11 places to output node 12, also can adopt many other devices.Fall as, can use the individual signals device to come Data transmission.On the other hand, can produce signal " q " with the paraphase device, signal " q " is with respect to data-signal " d " paraphase.Utilize the signal " d " at data input node 11 places to be considered to be equal to by gating element 13 with shown in Figure 1 in these replacement device of data output node 12 places generation data output signals " q ".
Signal paraphase in the phase inverter that contains first isolated component 18 at data output node 12 places, this reversed phase signal finally puts on second feedback node 17 along from the feedback network of first feedback node 16 through scanning permission element 21.In diagram preferred form of the present invention, " height " latch input signal c1 and complementary signal c1_b thereof forbid containing the clock phase inverter work of second isolated component 19, so that phase inverter can't stop (fight) data output node 12 to handle the formation of thinking data-signal " q ".Yet in case latch input signal c1 becomes " low ", its complementary signal c1_b becomes " height ", and second buffer circuit 19 is worked, and with the signal paraphase at second feedback node, 17 places, and this reversed phase signal is put on data output node 12 conversely.For latch mode, its complementary signal c1_b keeps " height " as long as latch input signal c1 keeps " low ", and circuit 10 just keeps desirable latch output signal " q " at data output node 12 places.
Under scan testing mode, latch input signal c1 continues maintenance " low " and its complementary signal c1_b maintenance " height ".Like this, comprise that the clock phase inverter of second isolated component 19 keeps operating state, so that the signal at second feedback node, 17 places is in data output node 12 places controls " q ".And under the situation of c1 " low " and c1_b " height ", the signal " d " at data input node 11 places is to the not influence of signal at data output node 12 places.
For carrying out sweep test, at first make scanning allow element 21 work, with first and second feedback nodes 16 and 17 decoupling zeros, disconnect feedback network thus respectively.In graphic form of the present invention, signal scanc1 becomes " height " and its complementary signal scanc1_b becomes " low ", so that device 29 and 30 is all placed nonconducting state,, prevent the signal at effect of signals second feedback node 17 places at first feedback node, 16 places with node 16 and 17 decoupling zeros.The combination of being somebody's turn to do " height " signal scanc1 and " low " signal scanc1_b can be called scanning and allow signal condition.What those those having ordinary skill in the art will appreciate that is that many other devices---paraphase and noninvert---all can be used to disconnect selectively the feedback network between two feedback nodes 16 and 17.These other device is considered to be equal to structure shown in Fig. 1.
For second feedback node 17 from 16 decoupling zeros of first feedback node, scanning input element 22 utilizes sweep signal " si " by second feedback node control output signal " q ".In the graphic form of the present invention, scanning input element 22 comprises the clock phase inverter, and this clock phase inverter is by signal scanc1 and complementary signal scanc1_b control thereof.When 22 work of scanning input element, scan input signal " si " paraphase, this reversed phase signal puts on second feedback node 17.This signal causes the signal " q " at data output node 12 places to follow sweep signal " si " in the paraphase once more of second isolated component, 19 places.In case produce ideal signal " q " at data output node 12 places, scanning allows signal scanc1 to can be changed into " low " (and its complementary signal scanc1_b can be changed into " height ") so that scanning allows element 21 be coupled once more first and second feedback nodes 16 and 17, because in this case, node will carry a shared signal (reversed phase signals of node 12 place's signals " q ").
Number " q " can illustrate scanning input element 22 and comprise the first and second N type devices, is respectively 44 and 45, and their leakage-source guiding path is connected in series between clock phase inverter output node 46 and the system reference voltage.Phase inverter output node 46 is coupled on second feedback node 17.The grid that connects a N type device 44 to be receiving sweep signal " si ", and the grid that connects the 2nd N type device 45 allows signal scanc1 to receive scanning.Diagram scanning input element 22 also comprises the first and second P type devices, is respectively 47 and 48, and their source-leakage conductance path is connected in series in supply voltage V
DdAnd between the circuit output node 46.The grid that connects a P type device 47 to be receiving sweep signal " si ", and the grid that connects the 2nd P type device 48 is with received signal scanc1_b (complementary signal of scanc1).
Although the output at data output node 12 places letter is as the scanning output signal when circuit 10 runs on scan testing mode, preferred form of the present invention shown in Figure 1 provides a scanning output signal " so " of separating by scanning output element 23.Scanning output element 23 comprises the paraphase device, and this paraphase device scans output signal " so " with the signal paraphase that first feedback node, 16 places produce to provide.Preferred paraphase scanning output element 23 shown in Figure 1 is made clock to keep scanning output signal " so " and signal " q " irrelevant by one scan clock signal c2.
Preferred scanning output element 23 comprises a clock phase inverter 51, and the phase inverter input node 52 of this clock phase inverter 51 is coupled to the latch cicuit feedback network, preferably at first feedback node, 16 places.The output node 53 of clock phase inverter 51 is coupled to first intermediate node 55.Clock phase inverter 51 comprises the first and second N type devices, is respectively 56 and 57, and their leakage-source guiding path is connected in series between clock phase inverter output node 53 and the system reference voltage.The gate coupled of the one N type device 56 is to phase inverter input node 52, and the grid of the 2nd N type device 57 is connected reception scan clock signal c2.Preferred clock phase inverter 51 also comprises the first and second P type devices, is respectively 58 and 59, and their source-leakage conductance path is connected in series in supply voltage V
DdAnd between the clock phase inverter output node 53.The gate coupled of the one P type device 58 is to circuit input node 52, and the grid that connects the 2nd P type device 59 is with received signal c2_b, and it is the complementary signal of scan clock signal c2.
First intermediate node 55 is coupled on the input node 61 of phase inverter 62 in the middle of, and the output node 63 of this centre phase inverter 62 is coupled on second intermediate node 65.Second intermediate node 65 provides input to a final stage (final) phase inverter 67, and this final stage phase inverter 67 provides its output to scanning output node 70, with as scanning output signal " so ".
Diagram scanning output element 23 comprises a feedback device, and it has the first and second P type devices, is respectively 72 and 73, and their source-leakage conductance path is connected in series in system power supply voltage V
DdAnd first between the intermediate node 55.The grid that connects a P type device 72 passes to the signal that receives second intermediate node, 65 places, and the grid that connects the 2nd P type device 73 is to receive scan clock signal c2.This feedback device also comprises the first and second N type devices, is respectively 74 and 75, and their leakage-source guiding path is connected in series between the system reference voltage and first intermediate node 55.The grid that connects a N type device 74 to be receiving the signal at second intermediate node, 65 places, and the grid that connects the 2nd N type device 75 is with received signal c2_b.
Diagram scanning output element 23 in service, the signal at first feedback node, 16 places is in the 51 places paraphase of clock phase inverter, and only when scan clock signal c2 became " height " and its complementary signal c2 and becomes " low ", reversed phase signal just put on first intermediate node 55.The signal at first intermediate node, 55 places is by the paraphase once more of middle phase inverter 62, and by the 67 last paraphase of final stage phase inverter, to provide scanning output signal " so " at scanning output node 70 places.In this case, " height " c2 signal and " low " c2_b signal make feedback device 73 and 75 end respectively, so that feedback device can't stop the entering signal from the latch feedback path.Yet, its complementary signal c2_b becomes " height " in case scan clock signal c2 becomes " low ", the signal that the feedback device of scanning output element 23 just keeps first intermediate node, 55 places to produce, like this, as long as scan clock signal c2 keeps " low ", just keep the scanning output signal " so " at scanning output node 70 places.Therefore, when circuit 10 moved under scan testing mode, 23 operations of diagram scanning output element were to provide scanning output signal " so " separately.When circuit 10 moves under latch mode, the function output that diagram scanning output element 23 can provide open in one fen at scanning output node 70 places.The functional output that can be independent of the signal " q " at data output node 12 places and keep this to separate.
Above preferred embodiment is intended to illustrate principle of the present invention, but does not limit the scope of the invention.Under the situation of the scope that does not break away from following claims, those those of ordinary skill in the art can finish various other embodiment and to the improvement of these preferred embodiments.For example, although in graphic form of the present invention, propose pass through door and the clock phase inverter has utilized two signals (for example c1 and c1_b), other forms of the present invention can only be worked with individual signals.Various clock apparatus can be used to control the scanned latch cicuit that the principle of the invention is specialized.And, although diagram latch cicuit 10 comprises a static latch, can apply scan test data by the isolated feedback path relevant according to the present invention with the timing latch cicuit.
Claims (26)
1. latch cicuit comprises:
(a) one latch input element, it is connected between a data input node and the data output node, this latchs input element and receive data when data entry mode, and the signal condition of the Data Control data output node when utilizing data entry mode in response to latch input signal;
(b) first isolated component has input that is coupled to the data output node and the output that is coupled to first feedback node, and first isolated component utilizes the signal condition of data output node to produce first feedback signal at the first feedback node place;
(c) second isolated component, have input that is coupled to second feedback node and the output that is coupled to the data output node, second isolated component utilizes the signal condition at the signal condition control data output node place at the second feedback node place, and first isolated component and second isolated component make feedback network and data output node isolated;
(d) one scan allows element, it is connected between first feedback node and second feedback node, scanning allows element responds to allow signal with the decoupling zero on second feedback node of first feedback node in one scan, and in response to scanning inhibit signal be coupled first feedback node and second feedback node;
(e) one scan input element, it is connected between the one scan input node and second feedback node, this scanning input element self-scanning input node receives sweep signal, and allows signal in response to scanning, utilizes sweep signal to control the second feedback node place signal condition; With
(f) one scan output element, it is connected between first feedback node and the one scan output node, and this scanning output element utilizes the first feedback network signal at the first feedback node place to produce the scanning output signal at scanning output node place.
2. the latch cicuit of claim 1, wherein:
(a) latching input element comprises and passes through gating element, should comprise a N type device and a P type device by gating element, the leakage of this N type device-source guiding path coupling data input node and data output node, and the source of this P type device-leakage conductance path coupling data input node and data output node; With
(b) latch input signal puts on the grid of N type device, and the complementary signal of this latch input signal puts on the grid of P type device.
3. the latch cicuit of claim 1, wherein second isolated component comprises a phase inverter, this phase inverter has the phase inverter input that is coupled to second feedback node and is coupled to the phase inverter output of data output node.
4. the latch cicuit of claim 2, wherein second isolated component comprises a clock phase inverter, this clock phase inverter comprises:
(a) a P type device and the 2nd P type device, the source of the source of the one P type device-leakage conductance path and the 2nd P type device-leakage conductance path is connected in series, so that a voltage source is coupled to the data output node, the gate coupled of the one P type device is to second feedback node, and the grid that connects the 2nd P type device is to receive latch input signal; With
(b) a N type device and the 2nd N type device, the leakage of the leakage of the one N type device-source guiding path and the 2nd N type device-source guiding path is connected in series, reference voltage source is coupled to the data output node, the gate coupled of the one N type device is to second feedback node, and the grid that connects the 2nd N type device is to receive the complementary signal of latch input signal.
5. the latch cicuit of claim 1, wherein:
(a) scanning allows element to comprise to pass through gating element, this is crossed gating element and has a P type device and a N type device, the source of P type device-leakage conductance path is coupled to second feedback node with first feedback node, and the leakage of N type device-source guiding path is coupled to second feedback node with first feedback node; With
(b) scanning permission signal is applied to the grid of P type device, and this scanning allows the complementary signal of signal to be applied to the grid of N type device.
6. the latch cicuit of claim 5 wherein scans input element and comprises a clock phase inverter, and this clock phase inverter comprises:
(a) a P type device and the 2nd P type device, the source of the source of the one P type device-leakage conductance path and the 2nd P type device-leakage conductance path is connected in series, so that a voltage source is coupled to second feedback node, the gate coupled of the one P type device is to scanning input node, and the grid that connects the 2nd P type device is received the complementary signal that scanning allows signal; With
(b) a N type device and the 2nd N type device, the leakage of the leakage of the one N type device-source guiding path and the 2nd N type device-source guiding path is connected in series, so that a reference voltage source is coupled to second feedback node, the gate coupled of the one N type device is to scanning input node, and the grid that connects the 2nd N type device allows signal to receive scanning.
7. the latch cicuit of claim 1, wherein:
(a) first isolated component comprises a phase inverter, and this phase inverter has the phase inverter input that is coupled to the data output node and is coupled to the phase inverter output of first feedback node; With
(b) the scanning output element comprises a phase inverter.
8. the latch cicuit of claim 1 wherein scans input element and comprises a clock phase inverter, and this clock phase inverter comprises:
(a) a P type device and the 2nd P type device, the source of the source of the one P type device-leakage conductance path and the 2nd P type device-leakage conductance path is connected in series, so that a voltage source is coupled to first interior nodes, the gate coupled of the one P type device is to first feedback node, and the grid that connects the 2nd P type device is to receive the one scan clock signal; With
(b) a N type device and the 2nd N type device, the leakage of the leakage of the one N type device-source guiding path and the 2nd N type device-source guiding path is connected in series, so that a reference voltage is coupled to first interior nodes, the gate coupled of the one N type device is to first feedback node, and the grid that connects the 2nd N type device is to receive the complementary signal of scan clock signal.
9. the latch cicuit of claim 1, wherein first isolated component comprises a phase inverter, and the scanning output element comprises:
(a) a clock phase inverter, it has the output that the input and that is coupled to first feedback node is coupled to first interior nodes;
(b) an interior nodes feedback circuit, it is coupled to interior nodes and is connected to receive the signal at the second interior nodes place;
(c) a middle phase inverter, it has the input that is coupled to first interior nodes and is coupled to the output of second interior nodes; With
(d) a final stage phase inverter, its input is coupled to second interior nodes and output is coupled to the scanning output node.
10. the latch cicuit of claim 9, wherein:
(a) the clock phase inverter comprises:
(i) a P type device and the 2nd P type device, the source of the source of the one P type device-leakage conductance path and the 2nd P type device-leakage conductance path is connected in series, so that a voltage source is coupled to first interior nodes, the gate coupled of the one P type device is to first feedback node, and the grid of the 2nd P type device is connected to receive the complementary signal of one scan clock signal; With
(ii) a N type device and the 2nd N type device, the leakage of the leakage of the one N type device-source guiding path and the 2nd N type device-source guiding path is connected in series, so that a reference voltage source is coupled to first interior nodes, the gate coupled of the one N type device is to first feedback node, and the grid of the 2nd N type device is connected to receive scan clock signal; With
(b) the interior nodes feedback circuit comprises:
(i) a P type device and the 2nd P type device, the source of the source of the one P type device-leakage conductance path and the 2nd P type device-leakage conductance path is connected in series, so that a voltage source is coupled to first interior nodes, the gate coupled of the one P type device is to second interior nodes, and the grid that connects the 2nd P type device is to receive the one scan clock signal; With
(ii) a N type device and the 2nd N type device, the leakage of the leakage of the one N type device-source guiding path and the 2nd N type device-source guiding path is connected in series, so that a reference voltage source is coupled to first interior nodes, the gate coupled of the one N type device is to second interior nodes, and the grid that connects the 2nd N type device is to receive the complementary signal of scan clock signal.
11. a latch cicuit that is used for latching the data that provide by a data input node, this latch cicuit comprises:
(a) the crucial path of a circuit;
(b) be connected to the feedback network of the crucial path of this circuit, this feedback network is with the crucial path isolation of circuit and comprise first feedback node and second feedback node;
(c) relevant with feedback network scanning allows element, and this scanning allows element responds to allow signal that first feedback node and second feedback node are isolated in one scan, and the signal condition at the first feedback node place is by the signal condition control at the crucial path of circuit place;
(d) one scan input element, by the signal condition of the crucial path of the second feedback node control circuit, second feedback node and first feedback node are isolated simultaneously.
12. the latch cicuit of claim 11 also comprises:
(e) one scan output element is used for utilizing the signal condition at feedback network place so that the one scan output signal to be provided.
13. the latch cicuit of claim 11 also comprises:
(a) first isolated component, it is connected between the crucial path of circuit and first feedback node, is used for the crucial path of circuit and first feedback node are isolated; With
(b) second isolated component, it is connected between second feedback node and the crucial path of circuit, is used for the crucial path of circuit and second feedback node are isolated.
14. the latch cicuit of claim 13, wherein second isolated component comprises a clock phase inverter, and this clock phase inverter comprises:
(a) a P type device and the 2nd P type device, the source of the source of the one P type device-leakage conductance path and the 2nd P type device-leakage conductance path is connected in series, a voltage source is coupled to the crucial path of circuit, the gate coupled of the one P type device is to second feedback node, and the grid of the 2nd P type device is by to receive a latch input signal; With
(b) a N type device and the 2nd N type device, the leakage of the leakage of the one N type device-source guiding path and the 2nd N type device-source guiding path is connected in series, a reference voltage source is coupled to the crucial path of circuit, the gate coupled of the one N type device is to second feedback node, and the grid of the 2nd N type device is connected to receive the complementary signal of latch input signal.
15. the latch cicuit of claim 13, wherein:
(a) first isolated component comprises a phase inverter, and this phase inverter has phase inverter input that is coupled to the crucial path of circuit and the phase inverter output that is coupled to first feedback node; With
(b) the scanning output element comprises a phase inverter.
16. the latch cicuit of claim 13, wherein first isolated component comprises a phase inverter, and the scanning output element comprises:
(a) a clock phase inverter, this circuit have the input that is coupled to first feedback node and are coupled to the output of first interior nodes;
(b) an interior nodes feedback circuit, it is coupled to interior nodes and is subjected to connecting to receive the signal at the second interior nodes place;
(c) a middle phase inverter, it has the input that is coupled to first interior nodes and is coupled to the output of second interior nodes; With
(d) a final stage phase inverter, its input is coupled to second interior nodes and its output is coupled to the scanning output node.
17. the latch cicuit of claim 16, wherein:
(a) the clock phase inverter comprises:
(i) a P type device and the 2nd P type device, the source of the source of the one P type device-leakage conductance path and the 2nd P type device-leakage conductance path is connected in series, so that a voltage source is coupled to first interior nodes, the gate coupled of the one P type device is to first feedback node, and the grid that connects the 2nd P type device is to receive the complementary signal of one scan clock signal; With
(ii) a N type device and the 2nd N type device, the leakage of the leakage of the one N type device-source guiding path and the 2nd N type device-source guiding path is connected in series, so that a reference voltage source is coupled to first interior nodes, the gate coupled of the one N type device is to first feedback node, and the grid that connects the 2nd N type device is to receive scan clock signal; With
(b) the interior nodes feedback circuit comprises:
(i) a P type device and the 2nd P type device, the source of the source of the one P type device-leakage conductance path and the 2nd P type device-leakage conductance path is connected in series, so that a voltage source is coupled to first interior nodes, the gate coupled of the one P type device is to second interior nodes, and the grid that connects the 2nd P type device is to receive the one scan clock signal; With
(ii) a N type device and the 2nd N type device, the leakage of the leakage of the one N type device-source guiding path and the 2nd N type device-source guiding path is connected in series, so that a reference voltage source is coupled to first interior nodes, the gate coupled of the one N type device is to second interior nodes, and the grid that connects the 2nd N type device is to receive the complementary signal of scan clock signal.
18. a method that is used for providing from latch cicuit one scan output, this method may further comprise the steps:
(a) feedback network and the crucial path of a latch cicuit are isolated, this feedback network comprises first feedback node and second feedback node;
(b) utilize the signal at the signal controlling first feedback node place at the crucial path of circuit place;
(c) allow signal in response to one scan, with the decoupling zero from second feedback node of first feedback node; With
(d) from second feedback node, during decoupling zero, apply the one scan input signal at first feedback node with signal by the crucial path of second feedback node control circuit place.
19. the method for claim 18 is further comprising the steps of:
(a) utilize the signal on the feedback network that the one scan output signal is provided.
20. the method for claim 18, wherein the step with feedback network and the crucial path isolation of circuit comprises:
(a) make the signal paraphase at the crucial path of circuit place and apply described reversed phase signal to first feedback node; With
(b) make the signal paraphase at the second feedback node place and apply described reversed phase signal to the crucial path of circuit.
21. the method for claim 18, wherein the step with first feedback node and the isolation of second feedback node comprises:
(a) grid to the first transistor applies scanning permission signal, the first transistor is connected between first feedback node and second feedback node, and apply the complementary signal that scanning allows signal to transistor seconds, transistor seconds and the first transistor are connected in parallel between first feedback node and second feedback node.
22. the method for claim 18, the step that wherein applies scan input signal comprises:
(a) apply described reversed phase signal with the scan input signal paraphase and to second feedback node.
23. the method for claim 22 is further comprising the steps of:
(a) allow signal to make the work of input phase inverter with scanning.
24. the method for claim 18 wherein utilizes the step of the signal generation scanning output signal at the first feedback node place to comprise:
(a) to the signal paraphase at the first feedback node place.
25. the method for claim 24 wherein utilizes the step of the signal generation scanning output signal at the first feedback node place may further comprise the steps:
(a) apply described reversed phase signal in response to the signal paraphase of scan clock signal, and to first intermediate node to the first feedback node place;
(b) apply described reversed phase signal to the signal paraphase at the first intermediate node place, and to second intermediate node;
(c), and apply described reversed phase signal to the scanning output node to the signal paraphase at the second intermediate node place;
(d) apply the signal at the second intermediate node place to a feedback device, this feedback device is connected to become first intermediate node.
26. the method for claim 25 also comprises with scan clock signal making the step of feedback device work with the signal that keeps the first intermediate node place.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/197,751 US6240536B1 (en) | 1997-01-27 | 1998-11-23 | Scanable latch circuit and method for providing a scan output from a latch circuit |
| US09/197,751 | 1998-11-23 | ||
| US09/197751 | 1998-11-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1254989A true CN1254989A (en) | 2000-05-31 |
| CN1187898C CN1187898C (en) | 2005-02-02 |
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ID=22730621
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991232496A Expired - Fee Related CN1187898C (en) | 1998-11-23 | 1999-10-28 | Scannable latch circuit for providing scan output from it and its method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN1187898C (en) |
| TW (1) | TW423221B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100340060C (en) * | 2003-08-20 | 2007-09-26 | 松下电器产业株式会社 | Semiconductor integrated circuit |
-
1999
- 1999-10-04 TW TW88117088A patent/TW423221B/en not_active IP Right Cessation
- 1999-10-28 CN CNB991232496A patent/CN1187898C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100340060C (en) * | 2003-08-20 | 2007-09-26 | 松下电器产业株式会社 | Semiconductor integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| TW423221B (en) | 2001-02-21 |
| CN1187898C (en) | 2005-02-02 |
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