CN1253768C - Method for preventing multitask selecting signal from producing unexpected output signal and its equipment - Google Patents
Method for preventing multitask selecting signal from producing unexpected output signal and its equipment Download PDFInfo
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- CN1253768C CN1253768C CN 02147058 CN02147058A CN1253768C CN 1253768 C CN1253768 C CN 1253768C CN 02147058 CN02147058 CN 02147058 CN 02147058 A CN02147058 A CN 02147058A CN 1253768 C CN1253768 C CN 1253768C
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Abstract
The present invention relates to a method for preventing a multitask selection signal from generating a non-prospective output signal in the selective state conversion. The method comprises the following steps that many signal sources are provided; the signal sources are arranged into at least two sets of signal source groups; a multitask selection signal is responded, and a multitask output signal is selected and generated in one specific set of the two sets of signal source groups. When the multitask selection signal lies in the selective state conversion mode, all signal sources in the specific signal source group all lie in an output disable mode, so that the non-prospective multitask output signal is prevented from generating. Simultaneously, the present invention also provides a device for preventing the multitask selection signal from generating the non-prospective output signal in the selective state conversion.
Description
Technical field
The present invention relates to a kind ofly select signal to select and produce the method and apparatus of output signal, refer to a kind ofly in the high-frequency work environment especially, prevent that multitask from selecting signal to produce the method and the device of unexpected output signal when carrying out the selection mode conversion with multitask.
Background technology
Along with the operating rate of microprocessor is more and more faster, they are also more and more in the problem that design aspect brought; Wherein, how avoiding selecting the state exchange action of signal because of multitask and have influence on the correctness of output signal, promptly is present important problem to be solved.
Cooperate multitask to select the working condition of signal for clearly demonstrating existing multiplexer, be example now with the existing multiplexer of 4*1 (signal end and an output signal end are selected in the multitask that include four input signal ends, can import two), do one illustrate as after.Shown in Figure 1A, Figure 1B, be respectively the work functions figure and the inner structure synoptic diagram of existing 4*1 multiplexer.In Figure 1A, the multiplexer M of one 4*1 is in order to import one first to fourth signal source P1～P4, and respond a multitask and select signal E, to select a signal source among this first to fourth signal source P1～P4 certainly, as the multitask output signal O shown in output Figure 1A.Wherein, this first to fourth signal source P1～P4 can serve as reasons and import phase-locked loop (the Phase-Locked Loop of a high-frequency signal, PLL) device is (because of it is a prior art, so figure does not go out) a plurality of phase-locked loops signal of being produced, and, the signal waveform of this first to fourth signal source P1～P4 is promptly as in as shown in Fig. 2, and in this wantonly two adjacent signal source, previous signal source takes the lead adjacent clock period an of signal source afterwards.
Shown in Figure 1B, promptly this multiplexer M usually by a code translator M0, one first to fourth with door M1～M4 with one or M5 formed.This code translator M0 can produce four decoded signals after signal E is selected in this multitask of input: one first to fourth decoded signal E1～E4, and exported to respectively this first to fourth with a door M1～M4 place.Owing to only can allow a decoded signal among this first to fourth decoded signal E1～E4 to be in a permission output state (with Figure 1B is example, is a high level state), select a signal source output certainly among this first to fourth signal source P1～P4 at every turn; As for remaining three decoded signal, then all be in an output prohibited state (with Figure 1B is example, is a low level state), to forbid other three signal sources output.Afterwards, and by this or door M5 with this first to fourth with door M1～M4 carry out with the gate logic computing after operation result, carried out one or the gate logic computing again, produce this multitask output signal O.Base this, in case signal E is selected in this multitask of the different bit combinations of input tool, can in this first to fourth signal source P1～P4, select different signal sources to export.
Directly in this multiplexer M, select the way of varying input signal source output in the prior art, its defective is: in case signal E is selected in this multitask of input continuously, and the signal source that preceding once desire is selected output with after desire when to select the signal source of output be inequality once, in the process that this multitask selects signal E to carry out the state exchange action, promptly can have influence on this multitask output signal O and produce wrong or unexpected waveform signal.
In more detail, as shown in Figure 2, be when signal E is selected in this multitask of the different bit combinations of input, and the waveform between its coherent signal compare synoptic diagram.In Fig. 2, (also please cooperate and consult shown in Figure 1B), this multitask selects the bit combination of signal E to select this first signal source P1 output as desiring between time t1～t6, obviously between time t1～t6, among Figure 1B this first decoded signal E1 also must be in high level state, and this second to the 4th decoded signal E2～E4 must be in low level state, O is between time t1～t6 for this multitask output signal, can export the waveform of this first signal source P1.Just, in case this multitask selects signal E to enter a state exchange pattern and desire to change into when selecting the 3rd signal source P3 output at time t6, in theory, this multitask output signal O should begin from time t6, promptly exports the waveform (high level state) of the 3rd signal source P3.Also promptly, in this a period of time, select signal E,, be only correct output so this multitask output signal O also should be in high level state between time t1～t11 always because of this multitask of importing the different bit combinations of tool continuously in time t1～t11.But existing actual selection mode switching motion, often non-as the expection as work, promptly, this first decoded signal E1 might be ahead of time at time t6, just change into low level state by high level state, and the 3rd decoded signal E3 just changes into high level state by low level state to time t7 late, these nonsynchronous phenomenons, to cause this multitask output signal O to occur changing into low level state, and begin just to rotate back into again the level variation of normal high level state until time t7 by high level state in time t6.So the wave form varies that sign X1 (between time t6～t7) locates in this multitask output signal O among Fig. 2 promptly belongs to unexpected waveform, and makes desire utilize device or the circuit generation misoperation of this multitask output signal O most probably.
For improving the above-mentioned existing law limitation of doing, this case inventor thinks that it is example that the state exchange action change that this multitask if can be selected signal E all is in an output prohibited state (with Figure 1B) to this first to fourth signal source P1～P4, being a low level state) time just carries out, and then would not have influence on the wave form varies at this multitask output signal O place.For example, selecting signal E to enter another state exchange pattern and desire at time t14 as this multitask changes into when selecting this secondary signal source P2 output from the 3rd signal source P3 that selects originally, though in actual implementation process, the 3rd decoded signal E3 also might appear ahead of time at time t14, just change into low level state by high level state, and this second decoded signal E2 is just changed into the situation of high level state late by low level state to time t15, so, therefore this first to fourth signal source P1～P4 all is in low level state the time, so this first to fourth all will thereby be fallen by forbidden energy with door M1～M4, so no matter how the level of this first to fourth decoded signal E1～E4 changes at this moment, all can not have influence on the wave form varies at this multitask output signal O place, and, this multitask output signal O is in time t19 place, and the side begins to export this secondary signal source P2.So, indicating X2 those shown (between time t14～t15) among Fig. 2, the unexpected or wrong signal waveform shown in the prior art does not as described above promptly appear.
Summary of the invention
The fundamental purpose of this case provides a kind ofly in the working environment of high frequency, can prevent that multitask from selecting signal to produce the method for unexpected output signal when carrying out the selection mode conversion.
Another purpose of this case provides a kind ofly in the working environment of high frequency, can prevent that multitask from selecting signal to produce the device of unexpected output signal when carrying out the selection mode conversion.
This case is to produce the method for unexpected output signal about a kind of multitask selection signal that prevents when carrying out the selection mode conversion, comprises the following steps: to provide a plurality of signal sources; Arrange these a plurality of signal sources to become at least two group signal source groups; And respond a multitask and select signal, in one group of particular signal source group in this at least two groups signal source group certainly, select and produce a multitask output signal; Wherein, when this multitask selected signal to be in a selection mode translative mode, all signal sources in this particular signal source group all had been in and have forbidden output mode, to prevent to produce unexpected this multitask output signal.
According to the above-mentioned conception of this case, wherein these a plurality of signal sources can be produced by a high-frequency signal.
According to the above-mentioned conception of this case, wherein these a plurality of signal sources refer to phase-locked loop (Phase-Locked Loop, PLL) a plurality of phase-locked loops signal that produced of device by this high-frequency signal of input.
According to the above-mentioned conception of this case, wherein differ clock (clock) cycle between wantonly two adjacent signal sources in these a plurality of signal sources.
According to the above-mentioned conception of this case, wherein in this wantonly two adjacent signal source, previous signal source is leading adjacent clock period an of signal source afterwards.
According to the above-mentioned conception of this case, wherein in this wantonly two adjacent signal source, previous signal source falls behind adjacent clock period an of signal source afterwards.
According to the above-mentioned conception of this case, wherein the signal source quantity of these a plurality of signal sources is the integral multiple of the signal source quantity of arbitrary group of signal source group in this at least two groups signal source group that it is distinguished.
According to the above-mentioned conception of this case, wherein the signal source quantity of these a plurality of signal sources is 4 times of signal source quantity of arbitrary group of signal source group in this at least two groups signal source group that it is distinguished.
According to the above-mentioned conception of this case, wherein this multitask is selected the selection mode translative mode of signal to respond all to be in all signal sources in this this particular signal source group that forbids output mode and is produced.
According to the above-mentioned conception of this case, wherein this forbids that output mode can be a low level state.
This case produces the device of unexpected output signal about a kind of multitask selection signal that prevents when carrying out the selection mode conversion, comprising: a multiple signal source generating device can respond a high-frequency signal, to produce a plurality of signal sources of output; One signal source output selection device, having at least two group multitasks selects circuit and is electrically connected on this multiple signal source generating device, this signal source output selection device can be selected circuit by this at least two groups multitask, should a plurality of signal sources import wherein respectively, and this signal source output selection device can adapt to a multitask and select signal, select one group of specific multitask in circuit to select circuit with this at least two groups multitask certainly, select and produce a multitask output signal; Wherein, when this multitask selected signal to be in a selection mode translative mode, this organized the signal source that all inputs in the circuit are selected in specific multitask, all has been in and has forbidden output mode, to prevent to produce unexpected this multitask output signal; And one multitask select signal generation device, be electrically connected on this multiple signal source generating device and this signal source output selection device, it is in order to import a clock signal and these a plurality of signal sources, to select signal to produce this multitask of output that signal generation device is selected in this multitask.
According to the above-mentioned conception of this case, wherein this multiple signal source generating device can be a phase-locked loop (Phase-Locked Loop, PLL) device.
According to the above-mentioned conception of this case, wherein differ clock (clock) cycle between wantonly two adjacent signal sources in these a plurality of signal sources.
According to the above-mentioned conception of this case, wherein this clock signal is a clock count value of presetting.
According to the above-mentioned conception of this case, wherein this signal source output selection device is can include one first to fourth multitask to select circuit, and arbitrary multitask selects circuit in order to import 1/4th signal sources that adhere to different piece in these a plurality of signal sources separately respectively.
According to the above-mentioned conception of this case, wherein this multitask selection signal is to include one first to fourth multitask to select signal, select circuit to carry out multitask selection action separately to control these four multitasks respectively, and produce one first to fourth multitask output signal.
According to the above-mentioned conception of this case, wherein this signal source output selection device can comprise that also a multi-task signal synthesizes output circuit, be electrically connected on this first to fourth multitask and select circuit, importing this first to fourth multitask output signal, and synthesize this multitask output signal of generation.
According to the above-mentioned conception of this case, wherein the synthetic output circuit of this multi-task signal can comprise one or door (ORgate), so that this first to fourth multitask output signal carries out one or the gate logic computing.
According to the above-mentioned conception of this case, wherein this multitask selects signal generation device to comprise: the signal interpretation circuit is selected in a multitask, can import and in response to this clock signal, to produce one first to fourth decoded signal; One first to fourth computing circuit, be electrically connected on this multitask and select the signal interpretation circuit, importing this first to fourth decoded signal respectively and to import 1/4th signal sources that adhere to different piece in these a plurality of signal sources separately separately, and corresponding generation one first to fourth output control signal; And one first to fourth output circuit, all being electrically connected on this multitask selects the signal interpretation circuit and is electrically connected on this first to fourth computing circuit respectively, this first to fourth output circuit can be imported respectively and in response to this clock signal, this first to fourth decoded signal and this first to fourth output control signal, select signal output to produce this first to fourth multitask respectively.
According to the above-mentioned conception of this case, wherein this first to fourth computing circuit all can be one or door (ORgate), is carried out one or the gate logic computing will import wherein 1/4th signal sources separately, and obtains this respectively and first to fourth export control signal.
According to the above-mentioned conception of this case, wherein this first to fourth output circuit all can be a saturating logical type electricity door bolt (Transparent Latch).
According to the above-mentioned conception of this case, wherein this multitask select that the selection mode translative mode of signal can correspondingly be in all that this forbids output mode this organize specific multitask and select the signal source of all inputs in the circuit and produce.
According to the above-mentioned conception of this case, wherein this forbids that output mode is to can be a low level state.
The beneficial effect of this case is, when this multitask selects signal to be in a selection mode translative mode, this organizes the signal source that all inputs in the circuit are selected in specific multitask, all be in and forbidden that output mode (for example, all be in identical low level state), effectively prevent to produce unexpected this multitask output signal.
The invention will be further described below in conjunction with the drawings and specific embodiments.
Description of drawings
Figure 1A, Figure 1B are work functions figure and the inner structure synoptic diagram that is respectively existing 4*1 multiplexer;
Fig. 2 be multiplexer among Figure 1A when signal is selected in the multitask of the different bit combinations of input, and the synoptic diagram relatively of the waveform between its coherent signal;
Fig. 3 is the flow example figure of a preferable implementation method of this case;
Fig. 4 is the topology example figure of a preferable device for carrying out said of this case;
Fig. 5 is the inner structure exemplary plot of the signal source output selection device in the preferable device for carrying out said of this case;
Fig. 6 is the inner structure exemplary plot that signal generation device is selected in the multitask in this signal source output selection device.
Embodiment
For further disclosing the implementation method of this case, as shown in Figure 3, be the flow example figure of a preferable implementation method of this case.Its detailed step is as described below:
Step 100: beginning.
Step 200: a plurality of signal sources that produced by a high-frequency signal are provided; Wherein, differ clock (clock) cycle between wantonly two adjacent signal sources, and in wantonly two adjacent signal sources, previous signal source takes the lead adjacent back clock period an of signal source.Certainly, in two adjacent signal sources in office, previous signal source also can fall behind adjacent back clock period an of signal source.In addition, these a plurality of signal sources can refer to that (Phase-Locked Loop PLL) installs a plurality of phase-locked loops signal that is produced by the phase-locked loop of this high-frequency signal of input.
Step 300: arrange these a plurality of signal sources to become at least two group signal source groups; Wherein, for ease of selecting signal source when output, avoid selecting to move the selection mode conversion that is produced, can have influence on a multitask output signal level, one preferable way is distinguished into the signal source group that has at least more than two groups respectively with these a plurality of signal sources, for example, be distinguished into four groups of signal source groups, and the signal source quantity of these a plurality of signal sources is 4 times for the signal source quantity of arbitrary group of signal source group in this at least two groups signal source group of distinguishing from it.
Step 400: respond a multitask and select signal, in one group of particular signal source group in this at least two groups signal source group certainly, select and produce this multitask output signal; Wherein, when this multitask selected signal to be in a selection mode translative mode, all signal sources in this particular signal source group all had been in and have forbidden that output mode (for example, all be in identical low level state), to prevent to produce unexpected this multitask output signal.Thus, when selecting the selection action of signal source output, can guarantee that the selection mode of avoiding this selections action to be produced changes, and can have influence on this multitask output signal level in this particular signal source group.
Step 500: finish.
Certainly, for understand the enforcement notion of this case with another angle, as shown in Figure 4, be the topology example figure of the preferable device for carrying out said of this case.In Fig. 4, this case prevents that the device 40 that multitask selects signal to produce unexpected output signal when carrying out the selection mode conversion from can comprise: a multiple signal source generating device 41, has at least two group multitasks and selects the signal source output selection device 42 of circuit and a multitask to select signal generation device 43.Wherein, this multiple signal source generating device 41 can respond a high-frequency signal 45, with produce a plurality of signal sources of output (for example, include the 1st to the 32nd signal source S0～S31), and, differ clock (clock) cycle between wantonly two adjacent signal sources.One preferable way, this multiple signal source generating device 41 can be a phase-locked loop, and (Phase-Locked Loop PLL) install, and these 32 signal source S0～S31 responds 32 phase-locked loop signals that this high-frequency signal produces for this lock loop device.
In addition, this has the signal source output selection device 42 that circuit is selected at least two group multitasks, be electrically connected on this multiple signal source generating device 41, to import this 32 signal source S0～S31, this signal source output selection device 42 then can adapt to a multitask of being imported and select signal 47, select one group of specific multitask in circuit to select circuit with this at least two groups multitask certainly, select and produce a multitask output signal 48; Wherein, when this multitask selects signal 47 to be in a selection mode translative mode, this organizes the signal source that all inputs in the circuit are selected in specific multitask, all be in and forbidden that output mode (for example, all be in identical low level state), to prevent to produce unexpected this multitask output signal 48.
Moreover, select signal generation device 43 about this multitask that is electrically connected on this multiple signal source generating device 41 and this signal source output selection device 42, import a clock signal 46 and this a plurality of signal source S0～S31, select signal 47 in order to produce this multitask of output; Certainly, this clock signal can be a default clock count value.
Selecting the appropriate signals source owing to consider this signal source output selection device 42, when moving for the selection of the usefulness that produces this multitask output signal, the incorrect state exchange that this multitask output signal 48 is produced as the prior art as described above changes, therefore, the inner structure of this signal source output selection device 42 is necessary to design especially.Below, a kind of embodiment is proposed with explanation.
As shown in Figure 5, be the inner structure exemplary plot of this signal source output selection device 42 in the preferable device for carrying out said 40 of this case.In Fig. 5, this signal source output selection device 42 can comprise: circuit 421～424 and the synthetic output circuit 425 of a multi-task signal are selected in one first to fourth multitask.
With embodiment shown in Figure 5, wherein the arbitrary multitask selection circuit in this first to fourth multitask selection circuit 421～424 is in order to import 1/4th signal sources among these 32 signal source S0～S31 respectively.For example, this first multitask selects circuit 421 to select circuit 422 to select circuit 423 to select 424 in circuit in order to import 8 signal source S11～S4 in order to import 8 signal source S19～S12, the 4th multitask in order to import 8 signal source S27～S20, the 3rd multitask in order to import 8 signal source S3～S28, this second multitask.Further discuss, this first to fourth multitask is selected circuit 421～424 to select signal generation device 43 to produce this multitask in order to response from this multitask and is selected signal 471,472,473,474, only allow one of them multitask to select circuit to produce output signal at one time, be with, this first to fourth multitask is selected circuit 421～424 can respond this multitask respectively and is selected signal 47, and produces this first to fourth multitask output signal 481,482,483,484.
As for the synthetic output circuit 425 of this multi-task signal, it then selects circuit 421～424 in order to be electrically connected on this first to fourth multitask, importing this first to fourth multitask output signal 481,482,483,484 respectively, and synthesized and produced this multitask output signal 48.One preferable way, the synthetic output circuit 425 of this multi-task signal can comprise one or door (OR gate), making this first to fourth multitask output signal 481,482,483,484 directly carry out one or the gate logic computing respectively, and obtain this multitask output signal 48 respectively.
Below further selecting the internal implementation structure of signal generation device 43 with regard to this multitask again is a detailed description.As shown in Figure 6, select the inside examples of favorable configurations figure of signal generation device 43 for this multitask.In Fig. 6, this multitask selects signal generation device 43 to include: signal interpretation circuit 431, one first to fourth computing circuit 432～435 and one first to fourth output circuit 436～439 are selected in a multitask.Wherein, this multitask selects signal interpretation circuit 431 can import and respond this clock signal 46, to produce one first to fourth decoded signal 65,66,67 and 68.
Further, this first to fourth computing circuit 432～435th all is electrically connected on this multitask and selects signal interpretation circuit 431, importing this first to fourth decoded signal 65,66,67 and 68 and import mutually different 1/4th signal sources among these 32 signal source S0～S31 separately respectively, and corresponding generation one first to fourth output control signal 61,62,63 and 64.And then, this first to fourth output circuit 436～439 also all is electrically connected on this multitask and selects signal interpretation circuit 431 and be electrically connected on this first to fourth computing circuit 432～435 respectively, so that this clock signal 46 can be imported and respond to this first to fourth output circuit 436～439 respectively, this first to fourth decoded signal 65,66,67 and 68 and this first to fourth output control signal 61,62,63 and 64, select signal 471 and produce one first to fourth multitask respectively, 472,473,474, and export to respectively in this first to fourth multitask selection circuit 421～424 shown in Figure 5.Certainly, this first to fourth multitask is selected signal 471,472,473,474 also can be merged in the present embodiment and is considered as this multitask selection signal E.
Wherein preferable way, this first to fourth computing circuit 432～435 all can be one or the door (ORgate), carried out one or the gate logic computing will import wherein 1/4th signal sources separately, and obtained this first to fourth output control signal 61,62,63 and 64 respectively; As for this first to fourth output circuit 436～439, then all can be a saturating logical type electricity door bolt (Transparent Latch).
In sum, this case can prevent that this multitask selection signal from when carrying out the selection mode conversion, making this multitask output signal produce unexpected signal waveform really in the working environment of a high frequency, address the deficiencies of the prior art.
This case can be made various equivalent transformations by those skilled in the art, all in the protection domain of this patent.
Claims (9)
1. one kind prevents that multitask selection signal from producing the method for unexpected output signal when carrying out the selection mode conversion, it is characterized in that, comprises the following steps:
A plurality of signal sources are provided;
Arrange these a plurality of signal sources to become at least two group signal source groups; And
Respond a multitask and select signal, in one group of particular signal source group in this at least two groups signal source group certainly, select and produce a multitask output signal; And
When this multitask selects signal to be in a selection mode translative mode, signal source to this particular signal source group is carried out computing, and all signal sources that respond in this particular signal source group all have been in the operation result of forbidding gained under the output mode, signal is selected in the multitask of exporting after this selection mode is changed, and produces follow-up multitask output signal with further selection.
2. the multitask selection signal that prevents as claimed in claim 1 produces the method for unexpected output signal when carrying out the selection mode conversion, it is characterized in that these a plurality of signal sources are meant a plurality of phase-locked loops signal that PLL device produced by this high-frequency signal of input.
3. one kind prevents that multitask selection signal from producing the device of unexpected output signal when carrying out the selection mode conversion, it is characterized in that, comprising:
One multiple signal source generating device can respond a high-frequency signal, to produce a plurality of signal sources of output;
One signal source output selection device, having at least two group multitasks selects circuit and is electrically connected on this multiple signal source generating device, this signal source output selection device can be selected circuit by this at least two groups multitask, should a plurality of signal sources import wherein respectively, and this signal source output selection device can respond a multitask and select signal, select one group of specific multitask in circuit to select circuit with this at least two groups multitask certainly, select and produce a multitask output signal; Wherein, when this multitask selected signal to be in a selection mode translative mode, this organized the signal source that all inputs in the circuit are selected in specific multitask, all has been in and has forbidden output mode; And
Signal generation device is selected in one multitask, be electrically connected on this multiple signal source generating device and this signal source output selection device, this multitask selects signal generation device to comprise computing circuit and output circuit, import a clock signal and these a plurality of signal sources, respond this clock signal these a plurality of signal sources are carried out computing, select signal to produce this multitask of output.
The 4 multitask selection signals that prevent as claimed in claim 3 produce unexpected output signal device when carrying out the selection mode conversion, it is characterized in that, this multitask is selected signal to include one first to fourth multitask and is selected signal, select circuit to carry out multitask selection action separately to control these four multitasks respectively, and produce one first to fourth multitask output signal.
5. the multitask selection signal that prevents as claimed in claim 4 produces the device of unexpected output signal when carrying out the selection mode conversion, it is characterized in that this multitask selects signal generation device to comprise:
The signal interpretation circuit is selected in one multitask, can import and respond this clock signal, to produce one first to fourth decoded signal;
One first to fourth computing circuit, be electrically connected on this multitask and select the signal interpretation circuit, importing this first to fourth decoded signal respectively and to import 1/4th signal sources that adhere to different piece in these a plurality of signal sources separately separately, and corresponding generation one first to fourth output control signal; And
One first to fourth output circuit, all being electrically connected on this multitask selects the signal interpretation circuit and is electrically connected on this first to fourth computing circuit respectively, this clock signal, this first to fourth decoded signal and this first to fourth output control signal can be imported and respond to this first to fourth output circuit respectively, selects signal output to produce this first to fourth multitask respectively.
6. the multitask selection signal that prevents as claimed in claim 5 produces the device of unexpected output signal when carrying out the selection mode conversion, it is characterized in that, this first to fourth computing circuit all can be one or the door, carried out one or the gate logic computing will import wherein 1/4th signal sources separately, and obtained this first to fourth output control signal respectively.
7. the multitask selection signal that prevents as claimed in claim 5 produces the device of unexpected output signal when carrying out the selection mode conversion, it is characterized in that, this first to fourth output circuit all can be a saturating logical type electricity and fastens with a bolt or latch.
8. the multitask selection signal that prevents as claimed in claim 3 produces the device of unexpected output signal when carrying out the selection mode conversion, it is characterized in that this multitask selects the selection mode translative mode of signal to respond all to be in that this forbids output mode that this is organized specific multitask and selects the signal source of all inputs in the circuit and produce.
9. the multitask selection signal that prevents as claimed in claim 3 produces the device of unexpected output signal when carrying out the selection mode conversion, it is characterized in that this forbids that output mode can be a low level state.
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| CN 02147058 CN1253768C (en) | 2002-10-24 | 2002-10-24 | Method for preventing multitask selecting signal from producing unexpected output signal and its equipment |
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| CN 02147058 CN1253768C (en) | 2002-10-24 | 2002-10-24 | Method for preventing multitask selecting signal from producing unexpected output signal and its equipment |
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