CN1250311A - External synchronous system and camera chain using the same system - Google Patents
External synchronous system and camera chain using the same system Download PDFInfo
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- CN1250311A CN1250311A CN99118807A CN99118807A CN1250311A CN 1250311 A CN1250311 A CN 1250311A CN 99118807 A CN99118807 A CN 99118807A CN 99118807 A CN99118807 A CN 99118807A CN 1250311 A CN1250311 A CN 1250311A
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- synchronizing signal
- pulse
- circuit
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- vertical synchronizing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
- H04N5/10—Separation of line synchronising signal from frame synchronising signal or vice versa
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- Synchronizing For Television (AREA)
Abstract
When a field is determined by using a counter, a number of gates are needed in fabricating the counter and accordingly, the circuit scale is magnified and high cost formation is resulted. According to the invention, in a timing control circuit for separating a horizontal synchronizing signal and a vertical synchronizing signal included in a compound synchronizing signal CSYNC by a synchronizing separator circuit and forming an internal horizontal synchronizing signal and an internal vertical synchronizing signal based on a horizontal synchronizing signal Sep-HD and a vertical synchronizing signal Sep-VD after the separation, pulses P2 and P3 formed in a procedure of synchronizing separation at the synchronizing separator circuit, are utilized for determining a field in a field determining circuit and when the compound synchronizing signal CSYNC is inputted as an external synchronizing signal, whether the field is an odd number field or an even number field is determined.
Description
The present invention relates to a kind of outer synchro system and a kind of camera chain of using this outer synchro system, this camera chain is used for operating this system according to the synchronizing signal based on television system that provides from the outside, be particularly related to a kind of outer synchro system and a kind of camera chain of using this outer synchro system, this camera chain is used and is comprised the composite synchronizing signal of horizontal-drive signal and vertical synchronizing signal as external synchronization signal.
In monitoring camera system, usually, the synchronizing signal by using main camera (horizontal-drive signal, vertical synchronizing signal comprise the composite synchronizing signal of these signals), from video camera (slavecamera), set up synchronous.This known technology is called as synchronously outer.Carry out a kind of processing synchronously according to outer, make from the phase place of the synchronizing signal of the phase place of the synchronizing signal of video camera and main camera to be complementary.In this case, finally, vision signal is input to a monitor from a plurality of video cameras.
Yet, according to the position of placing, because the difference of the retardation of transmission line makes the synchronizing signal of main camera arrive each time cycle difference from video camera from video camera.When from video camera when locked, the image of generation has caused the synchronism deviation on monitor.
For this reason, from video camera,, eliminated the synchronism deviation on monitor, thereby eliminated the synchronism deviation amount that on monitor, causes by the synchronizing signal that provides from main camera is carried out phase adjusted at each.In addition, by phase-adjusted synchronizing signal, formed the synchronizing signal of using from camera side, based on such as horizontal-drive signal or vertical synchronizing signal.
Especially, being included in must be through separated in synchronization by horizontal-drive signal the composite synchronizing signal that provides from main camera and vertical synchronizing signal, the horizontal-drive signal of passing through separated in synchronization is carried out phase adjusted, after phase adjusted, phase place and external horizontal synchronization in the inner horizontal synchronizing signal that forms from camera side are synchronous, simultaneously, (H: cycle cycle horizontal scanning interval) is resetted by the vertical synchronizing signal through separated in synchronization the vertical counter that is used to carry out counting operation at 1H, based on the count value of the loading value (reset values) when the reset operation, form vertical synchronizing signal from camera side.
Yet, being used for carrying out interleaved television system, a screen (frame) comprises two fields of odd number (ODD) field and even number (EVEN) field, as shown in Figure 6, and according to odd field and even field, the form difference of synchronizing signal.When according to aforesaid and form synchronizing signal is different and from camera side notice (inform) vertical synchronizing signal the time, being loaded into vertical counter reset values in reset operation need be according to odd field with even field and different.
Thereby the field when needing to determine the input external composite sync signal is odd field or even field.Traditionally, by determining this in vertical synchronizing signal after the separated in synchronization and the phase relation between the horizontal-drive signal.Especially, make use determine circuit, in its structure, synchronously carry out counting operation, determine the field by the polarity of the horizontal-drive signal sometime behind the edge of detection of vertical synchronizing signal by usage counter and horizontal-drive signal.
Yet, according to above-mentioned tradition definite circuit, constructed the structure of usage counter, when making this counter, need a plurality of gate circuits, thereby the problem of bringing is that circuit scale increases, cost increases.
The present invention has been proposed in view of the above problems.An object of the present invention is to provide a kind of outer synchro system and use the camera chain of this outer synchro system, it can enough simple circuit configuration be stably determined.
According to an aspect of the present invention, a kind of camera chain is provided, be used for according to the composite synchronizing signal that comprises horizontal-drive signal and vertical synchronizing signal that provides from the outside, form inner horizontal synchronizing signal and internal vertical synchronizing signal, synchronously to finish the operation of camera chain with formed inner horizontal synchronizing signal and formed vertical synchronizing signal, described camera chain comprises synchronous separator circuit, be used for separating described horizontal-drive signal and described vertical synchronizing signal from described composite synchronizing signal, with be used for cycle horizontal scanning interval as unit, with the horizontal synchronization of described composite synchronizing signal part as a reference, first and second pulses that output has constant phase difference therebetween; First pulse shaping circuit, be used to form have with described first and described second pulse between the 3rd pulse of the consistent pulse duration of phase difference; Second pulse shaping circuit is used for forming the 4th pulse in the moment of the decline of the vertical synchronizing signal of being separated by described synchronous separator circuit; With the 3rd pulse shaping circuit, be used for based on described the 3rd pulse and the 4th pulse shaping field identification pulse.
According to the camera chain with said structure, first pulse shaping circuit forms the 3rd pulse, and the 3rd pulse was risen in the moment of first pulse, descends in the moment of second pulse.The 3rd pulse has constituted the pulse that is used for determining odd field and even field.Second pulse shaping circuit detects the trailing edge of the vertical synchronizing signal after the simultaneous operation, forms the 4th pulse.The 4th pulse is configured for the pulse of the trailing edge of detection of vertical synchronizing signal.In addition, the 3rd pulse shaping circuit according to the polarity of field identification pulse, is discerned odd field and even field in the moment of the pulse of the trailing edge that is used for the detection of vertical synchronizing signal.
The present invention goes for except comprising a main camera and one or several from the monitoring camera system of video camera, by setting up the system of outer any device construction of operating synchronously by using composite synchronizing signal.For example, that can infer has, a kind of outer synchro system, and wherein main device is a video camera, is made of a plurality of VCR (video tape recorder) from device; Another outer synchro system, wherein main device and one or several all are made of VCR from device; Or the like.
With reference to the detailed description of accompanying drawing to the excellent embodiment of the present invention choosing, above-mentioned and other purposes, feature and advantage of the present invention will become clearer, in the accompanying drawing:
Fig. 1 is the construction profile figure that an example of the structure of using a kind of camera chain of the present invention is shown;
Fig. 2 is the block diagram that the particular circuit configurations of timing control circuit is shown;
Fig. 3 is the sequential chart that is illustrated in the timing of determining in the odd field of NTSC/EIA standard;
Fig. 4 is the sequential chart that is illustrated in the timing of determining in the even field of NTSC/EIA standard;
Fig. 5 is the block diagram of an example that illustrates according to the circuit structure of the definite circuit in field of an embodiment; With
Fig. 6 is the signal waveforms according to the vertical synchronization part of the TV signal of NTSC/EIA standard.
Provide below according to an embodiment of the invention and explain in detail.Fig. 1 is the construction profile figure that an example of the structure of using a kind of camera chain of the present invention is shown.
Here, the situation of the structure that is realized by analogue system with the camera signal treatment system has provided explanation as an example.Yet the present invention also can be applied to the situation that is realized the structure of this system by digital system naturally similarly.In addition, for example, this camera chain as using from video camera, has adopted a kind of system in monitoring camera system, be used as external synchronization signal based on the TV signal that provides from main camera comprising the composite synchronizing signal of horizontal-drive signal and vertical synchronizing signal.
In Fig. 1, the output signal of ccd image element 11 (ccd signal) is imported into signal processing circuit 12.Signal processing circuit 12 is configured to comprise: be used to sample and keep the circuit (S/H circuit) of the output signal of ccd image element 11; The circuit (agc circuit) that is used to amplify sampling and keeps outputing to fixed level; Be used for ccd signal is converted to the circuit of vision signal.Timing control circuit 13 is mounted to form the CCD drive signal, is used for driven CCD image component 11 and forms the signal processing drive signal, is used for drive signal treatment circuit 12 etc.
Fig. 2 illustrates the particular circuit configurations of timing control circuit 13.Be imported into timing control circuit 13 by the composite synchronizing signal CSYNC that provides from main camera.Timing control circuit 13 is configured to comprise synchronous separator circuit 21.
Synchronous separator circuit 21 is isolated horizontal-drive signal HD and the vertical synchronizing signal VD among the composite synchronizing signal CSYNC that is included in input respectively.Thereafter, the horizontal-drive signal HD and the vertical synchronizing signal VD of process separated in synchronization are described to horizontal-drive signal Sep-HD and vertical synchronizing signal Sep-VD.Horizontal-drive signal Sep-HD is temporarily outputed to the outside of timing control circuit 13.
In addition, horizontal-drive signal Sep-HD must be via phase regulating circuit 22 phase adjusted, phase regulating circuit 22 is installed in the outside of timing control circuit 13, and after this horizontal-drive signal Sep-HD is input to timing control circuit 13 once more, constitutes an input of phase comparator (PC) 23.The relatively output of phase comparator 23 is output to the outside of timing control circuit 13, and is level and smooth by LPF (low pass filter) 24, is provided for VCO (voltage controlled oscillator) 25 as its control voltage.
VCO 25 is vibrated by original running clock 2MCK, and its frequency is the reference clock of camera chain, i.e. the twice of the frequency of the master clock MCK of 14MHz.Frequency of oscillation changes according to control voltage.Original running clock 2MCK is imported into timing control circuit 13, and by 1/2 frequency divider, 26 1/2 frequency divisions, thereby the master clock MCK of formation 14MHz offers inner HD then and forms circuit 27.
Inner HD forms circuit 27 and forms (the H: the horizontal frequency signal fH in cycle cycle horizontal scanning interval) that has 1H by the master clock MCK frequency division to 14MHz, output horizontal frequency signal fH is to the outside of timing control circuit 13, as from horizontal-drive signal SLV-HD, offer V (vertically) counter 28 and timing generator 29, and offer phase comparator 23, as its another one input.
Phase comparator 23 relatively constitutes the phase place of the horizontal-drive signal Sep-HD after the phase adjusted of an input and the phase place of horizontal frequency signal fH, will offer VOC25 through above-mentioned LPF24 according to the relatively output of phase difference.
That is, form horizontal frequency signal fH and provide this signal to constitute PLL (phase-locked loop) circuit based on phase comparator 23, LPF24, VOC25 and original running clock 2MCK by being used for to the Circuits System of phase comparator 23.Finish the external sync operation by the PLL circuit, the horizontal-drive signal Sep-HD after horizontal-drive signal SLV-HD and phase adjusted is synchronous.
V counter 28 with the vertical synchronizing signal Sep-VD that provides from synchronous separator circuit 21 as the input that resets, horizontal frequency signal fH is counted, form vertical frequency signal fV based on count value, output vertical frequency signal fV is to the outside of timing control circuit 13, as from vertical synchronizing signal SLV-Vd, fV offers timing generator 29 with this vertical frequency signal.Timing generator 29 forms from composite synchronizing signal SLV-SYNC, will output to the outside of timing control circuit 13 from composite synchronizing signal SLV-SYNC.
The inside of timing control circuit 13 also is equipped with a definite circuit 30, is used to determine that the field when input composite synchronizing signal CSYNC is odd field or even field.The definite circuit 30 in field is characteristics of the present invention, and the detailed explanation of physical circuit structure and circuit operation thereof will provide in the back.
Come self-fields to determine that definite result of circuit 30 is provided for counting decoder 31.Counting decoder 31 is used for reset value (loading value), is used for being loaded into V counter 28 when V counter 28 resets.Reset values is set at a value, this value is according to from the phase state of horizontal-drive signal SLV-HD with respect to horizontal-drive signal Sep-HD, that is, and and homophase or lagging phase or leading phase and difference, and reset values is set at a value, and this value is odd field or even field and difference according to this.
Thereby counting decoder 31 needs to determine the result of field.In addition, counting decoder 31 is loaded into V counter 28 with reset values.In the reset operation based on the V counter 28 of vertical synchronizing signal Sep-VD, this reset values is under the situation of odd field and under the situation at even field, based on determining definite result that circuit 30 provides from the field and difference.
Then, will give the explanation of the particular circuit configurations of definite circuit 30 that appears on the scene according to embodiment.The definite circuit 30 in field is characterised in that, by using from the pulse P2 and the P3 of synchronous separator circuit 21 outputs, determines that the field when input composite synchronizing signal CSYNC is odd field or even field.
Here, before explaining a definite circuit 30, will provide the explanation of the operation of synchronous separator circuit 21 with reference to the sequential chart of figure 3 and Fig. 4.By the way, Fig. 3 shows the situation of odd number (ODD) field of NTSC (National Television System Committee)/EIA (Electronic Industries Association), and Fig. 4 shows the situation of the even field of NTSC/EIA.In this case, EIA refers to the black and white standard corresponding to NTSC.
Synchronous separator circuit 21 forms pulse P1 by the rising edge that detects composite synchronizing signal CSYNC, with the pulse P1 consistent with the horizontal synchronization part of composite synchronizing signal CSYNC is reference,, be that unit forms pulse P2 and P3 roughly with 1H at the corresponding interval of 1/3H and 2/3H.The result is that pulse P2 and pulse P3 constitute constant phase difference.In addition, by constructing a latch (1atch), horizontal-drive signal Sep-HD separates from composite synchronizing signal CSYNC.This latch was set in moment of pulse P3, resetted constantly in the decline of composite synchronizing signal CSYNC.
In addition, form pulse P4 by constructing a latch, this latch was set in the moment of pulse P2 or P3, resetted in the moment of pulse P1.In addition, form pulse P5 by the composite synchronizing signal CSYNC that samples constantly in the rising of pulse P4.In addition, by at the moment of pulse P1 sampling pulse P5, vertical synchronizing signal Sep-VD separates from composite synchronizing signal CSYNC.
By this way, be used at various moment formation pulse P1 to P5 with based on they synchronous separator circuits 21 from composite synchronizing signal CSYNC separation of level synchronizing signal Sep-HD and vertical synchronizing signal Sep-VD, export the horizontal-drive signal Sep-HD and the vertical synchronizing signal Sep-VD that separates that separate, will be used for determining that the pulse P2 of field and P3 export definite circuit 30 of showing up.
By the vertical synchronizing signal Sep-VD that uses the pulse P2 that provided by synchronous separator circuit 21 and P3 and use to be separated by synchronous separator circuit 21, a definite circuit 30 is determined fields.Fig. 5 illustrates an example of the circuit structure of definite circuit 30.
In Fig. 5, a definite circuit 30 is configured to comprise: first pulse shaping circuit 41, and input pulse P2 and P3 and master clock MCK are used to form pulse P6, and the pulse duration of pulse P6 is consistent with the phase difference between pulse P2 and the P3; Second pulse shaping circuit 42, input vertical synchronizing signal Sep-VD and master clock MCK are used for forming pulse P7 constantly in the decline of vertical synchronizing signal Sep-VD; With the 3rd pulse shaping circuit 43, be used for forming an identification pulse based on pulse P6 and P7.
For example, first pulse shaping circuit 41 is made of JK flip-flop 44, and pulse P2 imports as J, and pulse P3 imports as K, and master clock MCK imports as clock.For example, second pulse shaping circuit 42 is made of d type flip flop 45, d type flip flop 46 and dual input NOR (nondisjunction) door 47.D type flip flop 45 usefulness vertical synchronizing signal Sep-VD import as D, and master clock MCK imports as clock.The Q output of d type flip flop 46 usefulness d type flip flops 45 is as the D input, and master clock MCK imports as clock.47 inputs of dual input NOR door are from the Q of d type flip flop 45 outputs and the XQ that exports from d type flip flop 46.
The 3rd pulse shaping circuit 43 comprises phase inverter 48 and 49, the polarity of be used to overturn pulse P6 and P7; Dual input NOR door 50 is used to import each output of phase inverter 48 and 49; Dual input NOR door 51 is used for the output of input pulse P6 and phase inverter 49; Dual input OR (" or ") door 52, be output as an one input with dual input NOR door 50; Dual input AND (" with ") door 53, with each output of NOR door 51 and dual input OR door 52 as importing; With d type flip flop 54, to import as D from the output of AND door 53, master clock MCK imports as clock.The Q output of d type flip flop 54 is derived as field identification signal FP, becomes another input of OR door 52.
Then, with reference to the sequential chart of figure 3 and Fig. 4, provide the explanation of the circuit operation of the definite circuit 30 in field with said structure.
At first, provide the explanation of the formation of pulse P6 and P7.In first pulse shaping circuit 41, JK flip-flop 44 is imported as J with pulse P2, and input forms pulse P6 to pulse P3 as K, and pulse P6 rose in the moment of pulse P2, descended in the moment of pulse P3.Pulse P6 is configured for determining the pulse of ODD/EVEN field.
Simultaneously, in second pulse shaping circuit 42, dual input NOR door 47 calculates by d type flip flop 45 by latching latching output Q and exporting the non-OR that latchs paraphase output XQ that Q produces by d type flip flop 46 by latching latch of vertical synchronizing signal Sep-VD generation, thereby form pulse P7, the trailing edge of pulse P7 detection of vertical synchronizing signal Sep-VD.
Then, in the 3rd pulse shaping circuit 43, under the situation of odd field shown in the sequential chart of Fig. 3, definite pulse P6 and VD trailing edge detect pulse P7 all at " H " level, and correspondingly, the field identification pulse FP of the Q of d type flip flop 54 output becomes " H " level.That is, having indicated at the field of " H " level identification pulse FP is odd field.
Simultaneously, under the situation of even field shown in the sequential chart of Fig. 4, definite pulse P6 is at " L " level, and the VD trailing edge detects pulse P7 at " H " level, and correspondingly, the field identification pulse FP of the Q of d type flip flop 54 output becomes " L " level.That is, having indicated at the field of " L " level identification pulse FP is odd field.
As mentioned above, according to the camera chain of using composite synchronizing signal CSYNC as external synchronization signal, the ODD by utilizing horizontal synchronization pulse, vertical sync pulse and composite synchronizing signal CSYNC and the particularity of the equalizing pulse between the EVEN field, by using the pulse P2 and the P3 that in synchronous separator circuit 21, in the separated in synchronization process, form to determine the field, do not use the counter in the conventional art, by the combination of simple logic circuit, just can determine that the field when input composite synchronizing signal CSYNC is odd field or even field.
In addition, the circuit structure of the definite circuit 30 in field shown in Figure 5 only is an example, the invention is not restricted to this.In a word, can constitute a kind of circuit structure, be used for forming a definite pulse P6 and being used for trailing edge at vertical synchronizing signal Sep-VD forming the VD trailing edge and detecting pulse P7 based on the pulse P2 that provides from synchronous separator circuit 21 and P3.By it,, can discern the polarity of a definite pulse P6 in the moment of Sep-VD trailing edge detection pulse P7.
In addition, although according to the foregoing description, provided the explanation of the situation that is applied to the NTSC/EIA television system, but the present invention goes for finishing interleaved any standard substantially, such as PAL (phase-aoternation line system)/CCIR (Le Comite Consultatif International de R).In this case, CCIR refers to the black and white standard corresponding to PAL.
As mentioned above, according to the present invention, in using the outer synchro system of composite synchronizing signal as the camera chain of external synchronization signal, utilize the particularity of the ODD and the equalizing pulse between the EVEN field of horizontal synchronization pulse, vertical sync pulse and composite synchronizing signal by constructing a kind of structure, determine the field by using the pulse that in the separated in synchronization process, forms, do not use the counter in the conventional art, by the combination of simple logic circuit, just can determine fully that the field when the input composite synchronizing signal is odd field or even field.Correspondingly, circuit structure is simplified, and can realize low cost.
Claims (4)
1, a kind of camera chain, be used for according to the composite synchronizing signal that comprises horizontal-drive signal and vertical synchronizing signal that provides from the outside, form inner horizontal synchronizing signal and internal vertical synchronizing signal, synchronously to finish the operation of camera chain with formed inner horizontal synchronizing signal and formed vertical synchronizing signal, described camera chain comprises:
Synchronous separator circuit, be used for separating described horizontal-drive signal and described vertical synchronizing signal from described composite synchronizing signal, with be used for cycle horizontal scanning interval as unit, with the horizontal synchronization of described composite synchronizing signal part as a reference, first and second pulses that output has constant phase difference therebetween;
First pulse shaping circuit, be used to form have with described first and described second pulse with the 3rd pulse of the consistent pulse duration of phase difference;
Second pulse shaping circuit is used for forming the 4th pulse in the moment of the decline of the vertical synchronizing signal of being separated by described synchronous separator circuit; With
The 3rd pulse shaping circuit is used for based on described the 3rd pulse and the 4th pulse shaping field identification pulse.
2, a kind of outer synchro system, be used for based on the composite synchronizing signal that comprises horizontal-drive signal and vertical synchronizing signal that provides from main device, from device, forming inner horizontal synchronizing signal and internal vertical synchronizing signal, synchronously to operate described from device with described inner horizontal synchronizing signal and described vertical synchronizing signal
Wherein saidly comprise from device:
Synchronous separator circuit, be used for separating described horizontal-drive signal and described vertical synchronizing signal from described composite synchronizing signal, with be used for cycle horizontal scanning interval as unit, with the horizontal synchronization of described composite synchronizing signal part as a reference, first and second pulses that output has constant phase difference therebetween;
First pulse shaping circuit, be used to form have with described first and described second pulse between the 3rd pulse of the consistent pulse duration of phase difference;
Second pulse shaping circuit is used for forming the 4th pulse in the moment of the decline of the vertical synchronizing signal of being separated by described synchronous separator circuit; With
The 3rd pulse shaping circuit is used for based on described the 3rd pulse and the 4th pulse shaping field identification pulse.
3, outer synchro system as claimed in claim 2, wherein said main device is a video camera, described is one or several video camera or video tape recorder from device.
4, outer synchro system as claimed in claim 2, wherein said main device is VTR, described is one or several VCR from device.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP259794/1998 | 1998-09-14 | ||
| JP25979498 | 1998-09-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1250311A true CN1250311A (en) | 2000-04-12 |
| CN1132412C CN1132412C (en) | 2003-12-24 |
Family
ID=17339095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99118807A Expired - Fee Related CN1132412C (en) | 1998-09-14 | 1999-09-13 | External synchronous system and camera chain using the same system |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6727957B1 (en) |
| KR (1) | KR20000023125A (en) |
| CN (1) | CN1132412C (en) |
| TW (1) | TW468339B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7009604B2 (en) * | 2002-07-19 | 2006-03-07 | Sun Microsystems, Inc. | Frame detector for use in graphics systems |
| JP4589631B2 (en) * | 2004-01-13 | 2010-12-01 | ソニー株式会社 | Imaging apparatus, phase control method, and synchronization establishment method |
| US7257508B2 (en) * | 2005-09-09 | 2007-08-14 | Advantest Corporation | Timing generator, and timing generating method |
| JP5262047B2 (en) * | 2007-09-28 | 2013-08-14 | ソニー株式会社 | Solid-state imaging device and imaging device |
| JP5080218B2 (en) * | 2007-11-28 | 2012-11-21 | パナソニック株式会社 | Solid-state imaging device |
| CN102821227B (en) * | 2011-06-10 | 2017-03-15 | 上海华虹集成电路有限责任公司 | A kind of decision method of video signal parity field |
| KR102158831B1 (en) * | 2014-04-29 | 2020-09-22 | 한화테크윈 주식회사 | Imaging Device including Image Signal Processing |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4375101A (en) * | 1980-09-30 | 1983-02-22 | Video Education, Inc. | System for formatting data on video tape for high accuracy recovery |
| US4860101A (en) * | 1987-11-06 | 1989-08-22 | Vicon Industries, Inc. | Central station synchronization system |
| JPH0453365A (en) * | 1990-06-21 | 1992-02-20 | Matsushita Electric Ind Co Ltd | Field discrimination correction device |
| JPH04150382A (en) * | 1990-10-11 | 1992-05-22 | Nec Ic Microcomput Syst Ltd | Automatic frequency control circuit |
| KR930004640B1 (en) * | 1990-12-22 | 1993-06-02 | 삼성전자 주식회사 | Video camera |
| KR950005054B1 (en) * | 1991-12-31 | 1995-05-17 | 삼성전자주식회사 | Apparatus for detecting odd/even field of tv signal |
| US5485220A (en) * | 1992-11-23 | 1996-01-16 | Eastman Kodak Company | Sync stripper circuit |
| KR970008382B1 (en) * | 1994-01-08 | 1997-05-23 | 파이오니아 가부시키가이샤 | Stereoscopic converting device for two dimensional video signal |
| JPH08256291A (en) * | 1994-12-19 | 1996-10-01 | Samsung Electron Co Ltd | Image superposing device |
| JPH08186767A (en) * | 1994-12-30 | 1996-07-16 | Sony Corp | Field discrimination method and circuit |
| KR100206767B1 (en) * | 1995-12-13 | 1999-07-01 | 구자홍 | Stereoscopic television reciever |
-
1999
- 1999-09-07 TW TW088115426A patent/TW468339B/en not_active IP Right Cessation
- 1999-09-10 US US09/393,834 patent/US6727957B1/en not_active Expired - Fee Related
- 1999-09-13 CN CN99118807A patent/CN1132412C/en not_active Expired - Fee Related
- 1999-09-14 KR KR1019990039223A patent/KR20000023125A/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| TW468339B (en) | 2001-12-11 |
| CN1132412C (en) | 2003-12-24 |
| US6727957B1 (en) | 2004-04-27 |
| KR20000023125A (en) | 2000-04-25 |
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