CN1248301C - Testing component including work line of memory and capacitor overlaped and offset as well as its testing method - Google Patents
Testing component including work line of memory and capacitor overlaped and offset as well as its testing method Download PDFInfo
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- CN1248301C CN1248301C CN02141562.5A CN02141562A CN1248301C CN 1248301 C CN1248301 C CN 1248301C CN 02141562 A CN02141562 A CN 02141562A CN 1248301 C CN1248301 C CN 1248301C
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- word line
- contact plunger
- capacitor
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Abstract
The present invention relates to a semiconductor test element and a method thereof, particularly to a test element for testing whether the word line structure of a dynamic random access memory is overlapped with a deep groove capacitor or not to generate offset, which is arranged in a cutting channel of a chip. The present invention comprises a trench capacitor, a rectangular word line, a first across word line, a second across word line, a first doping region and a second doping region, a first contact plug, a second contact plug and a third contact plug, wherein the trench capacitor is arranged in the cutting channel and is provided with an embedding plate; the rectangular word line is arranged on the cutting channel and is used for covering part of the deep groove capacitor; the first across word line and the second across word line are arranged on both sides of the upper part of the trench capacitor; the first doping region and the second doping region are respectively arranged between the rectangular word line and the first across word line and the rectangular word line and the second across word line; the first contact plug is coupled to the doping region; the second contact plug is coupled to the second doping region; the third contact plug is coupled to the embedding plate.
Description
Technical field
The present invention relates to a kind of testing element (test key) and method, the testing element of particularly a kind of word line structure that detects dynamic random access memory and the overlapping skew of deep trench capacitor (deep trench capacitor), detect the testing element of the mis-alignment (misalignment) of trench type capacitor and active region (active area).
Background technology
Trench type capacitor is a kind of dynamic random access memory (dynamic random access memory; Abbreviation DRAM) common capacitor arrangement in, it is formed in the semiconductor silicon substrate, and can increase its surface area by increasing the degree of depth of trench type capacitor in the semiconductor silicon substrate, to increase its capacitance.
Fig. 1 is the layout of traditional trench type capacitor.Trench type capacitor 10 is to be configured in to pass by word line (passing wordline) below.Transistor 14 is the storage nodes 16 that are electrically coupled to trench type capacitor 10 via diffusion region 18.Another diffusion region 20 is to be connected to contact hole 22, and contact hole 22 then is connected to bit line (not illustrating), to read or to write to storage node 16 by transistor 14.Transistor 14 is to drive by word line 12.When voltage is applied to word line 12, the passage of word line 12 belows meeting conducting, and between two diffusion regions 18 and 20, produce electric current and inflow or flow out storage node 16.
Fig. 2 is the A-A profile for Fig. 1.After trench type capacitor 10 is finished, can be in substrate and trench type capacitor form shallow trench isolation 28, with definition active region AA, and in order to isolate will form pass by word line 12 and trench type capacitor 10.Afterwards, in substrate, form word line 12.Cooperating with word line and shallow trench isolation 28 again is the ion injecting mask, and the active region in the word line both sides forms the doped region 18 and 20 as source/drain.Therefore, if during the photomask misalignment of the photomask of word line and trench type capacitor, can influence the size of formed doped region 18 and 20.So can make adjacent memory unit produce leakage current, and memory cell is invalid, thereby causes the decline of manufacture process qualification rate.
Therefore, if the alignment error of the photomask of the photomask of energy control word line structure and trench type capacitor then can improve the reliability of memory cell and the qualification rate of manufacture process in admissible scope.
Summary of the invention
Primary and foremost purpose of the present invention is to provide a kind of word line structure and overlapping method of testing that whether produces skew of deep trench capacitor that detects dynamic random access memory, and the alignment error of the photomask of control word line structure and the photomask of trench type capacitor is in admissible scope.
In addition, another object of the present invention is to provide a kind of word line structure and overlapping testing element that whether produces skew of deep trench capacitor that detects dynamic random access memory.
According to above-mentioned purpose, a kind of word line structure and overlapping testing element that whether produces skew of deep trench capacitor that is used to detect dynamic random access memory that the present invention provides is to be arranged in the Cutting Road of a chip.Above-mentioned testing element comprises a trench type capacitor, is arranged in the above-mentioned Cutting Road, has the plate of imbedding; One rectangle word line is arranged on the above-mentioned Cutting Road trench type capacitor of cover part; One first via is crossed word line and one second and is passed by word line, is arranged at both sides, trench type capacitor top; One first doped region and one second doped region are arranged at the rectangle word line and the first via respectively and cross between the word line, and rectangle word line and second is passed by between the word line; One first contact plunger is coupled to first doped region; One second contact plunger is coupled to second doped region; And one the 3rd contact plunger, be coupled to and imbed plate.
According to above-mentioned purpose, the present invention also provides a kind of word line structure and overlapping method of testing that whether produces skew of deep trench capacitor that detects dynamic random access memory, comprises providing a chip, said chip to have a Cutting Road and a memory cell areas at least; Form a testing element in the Cutting Road of said chip, and form a plurality of memory cell in the memory cell areas of said chip simultaneously, wherein this testing element comprises a trench type capacitor, is arranged in the Cutting Road, has the plate of imbedding; One rectangle word line is arranged on the Cutting Road, the trench type capacitor of cover part; One first via is crossed word line and one second and is passed by word line, is arranged at both sides, trench type capacitor top; One first doped region and one second doped region are arranged at the rectangle word line and the first via respectively and cross between the word line, and rectangle word line and second is passed by between the word line; One first contact plunger is coupled to first doped region; One second contact plunger is coupled to second doped region; One the 3rd contact plunger is coupled to and imbeds plate; Measure one first current value between first contact plunger and the 3rd contact plunger respectively, and one second current value of second contact plunger and the 3rd contact plunger; According to first and second current value, the rectangle word line structure on the estimation testing element and the overlapping degrees of offset of trench type capacitor; And the overlapping degrees of offset by rectangle word line structure on the testing element and trench type capacitor, the word line structure in the estimation memory cell areas stored unit and the overlapping degrees of offset of trench type capacitor.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 is the layout for common DRAM capacitor.
Fig. 2 is the profile for Fig. 1 section along the line A-A ';
Fig. 3 is detected words line structure of the present invention and the overlapping layout that whether produces the testing element of skew of deep trench capacitor;
Fig. 4 a is the profile for Fig. 3 section along the line B-B ';
Fig. 4 b is the profile for Fig. 3 section along the line C-C '.
Embodiment
Please refer to Fig. 3 and Fig. 4 a, Fig. 4 b, in order to explanation one embodiment of the invention.Wherein Fig. 3 among the present invention in order to the layout of the testing element of the detected words line structure that detects a dynamic random access memory and the overlapping skew of deep trench capacitor, wherein testing element is to be arranged in the Cutting Road of chip.Fig. 4 a is the profile for Fig. 3 section along the line B-B ', and Fig. 4 b is the profile for Fig. 3 section along the line C-C '.
One trench type capacitor 110 at first is set on the Cutting Road zone 160 of a chip 100.This trench type capacitor 110 comprises storage node 116, be arranged in imbedding plate (buried plate) 181 and placing between the two capacitor dielectric of flush type n type well region NW.Do electrical isolation by dielectric eckband 126 between storage node 116 and the doped p type well region PW.
Then, on this Cutting Road zone 160, one rectangle word line 12a is set respectively, a first via is crossed word line 12b and one second and is passed by word line 12c, this deep trench capacitor 110 of rectangle word line 12a cover part wherein, and the first via is crossed word line 12b and second and is passed by word line 12c and be arranged at both sides, trench type capacitor 110 top.In addition, first, second width of passing by word line 12b, 12c all equates, be roughly 0.2 micron, and the width of rectangle word line 12a can be passed by the width of word line 12b, 12c greater than this first, second, is roughly 0.6 micron.
Next,,, form one first doped region 201 and pass by between the word line 12c, form one second doped region 202, as shown in Fig. 4 a in rectangle word line 12a and second in crossing between the word line 12b respectively at the rectangle word line 12a and the first via by the mode of implanting ions.
At last, first to fourth contact plunger CS1, CS2, CB1, CB2 are set respectively, are coupled to first doped region 201, second doped region 202, above-mentioned plate 181 and the rectangle word line 12a of imbedding, as shown in the figure.
Refer again to Fig. 4 a and Fig. 4 b, imbed plate 181, first doped region 201 and rectangle word line 12a and can constitute a transistor 141, wherein imbed the source electrode of plate 181 as transistor 141, first doped region 201 is as the drain electrode of transistor 141, and rectangle word line 12a is then as the grid of transistor 141.On the other hand, imbed plate 181, second doped region 202 and rectangle word line 128 and can constitute a transistor 142, wherein imbed the source electrode of plate 181 as transistor 142, first doped region 202 is as the drain electrode of transistor 142, and rectangle word line 12a is then as the grid of transistor 142.
Therefore, the present invention can be by applying a set bias voltage V
BiasTo rectangle word line 12a, and a set voltage V
DCIn between the first contact plunger CS1 and the 3rd contact plunger CB1, and the suspension joint second contact plunger CS2, and record one first electric current I
1, and first electric current I
1Can meet mathematical expression one:
I
1=C * W/ (L
S-L
BS+ Δ L) (formula one)
Wherein, W is the width of the 3rd contact plunger CB1, L
BSFor imbedding the diffusion length of plate, Δ L is the side-play amount of rectangle word line, L
SBe the distance between first doped region and trench type capacitor, the fixed constant that C forms for several coefficients.
On the other hand, by applying a set inclined to one side V
BiasTo rectangle word line 12a, and a set voltage V
DCIn between the second contact plunger CS2 and the 3rd contact plunger CS1, and the suspension joint first contact plunger CS1, and record one second electric current I
2, and second electric current I
2Can meet mathematical expression two:
I
2=C * W/ (L
S-L
BS-Δ L) (formula two)
Wherein, W is the width of the second contact plunger CB2, L
BSFor imbedding the diffusion length of plate, P
LBe the side-play amount of rectangle word line, L
SBe the distance between second doped region and trench type capacitor, the fixed constant that C forms for several coefficients.
Owing to be under identical manufacture process condition, form transistor 141,142, so the width of first, second contact plunger CS1, CS2 is all W, the diffusion length of imbedding plate is all L
BS, the distance between first, second doped region and trench type capacitor is all L
SSo formula one and formula two can be rewritten as:
I
1/ I
2=(L
S-L
BS+ Δ L)/(L
S-L
BS-Δ L); (formula three)
Δ L=(L
BS-L
S) * (I
1-I
2)/(I
1+ I
2); (formula four)
According to above-mentioned formula three and formula four, can learn that first electric current can be equal to second electric current when if the offset L of rectangle word line is 0.If first electric current when being not equal to second electric current, is then represented overlapping between rectangle word line and trench type capacitor the skew of generation is arranged conversely speaking,, but and side-play amount and offset direction through type four try to achieve.For instance, when being offset toward transistor 141 directions as if word line 12a, 12b, 12c, first electric current I
1Can be less than second electric current I
2When being offset toward transistor 141 directions as if word line 12a, 12b, 12c conversely speaking,, first electric current I
1Can be greater than second electric current I
2Therefore, two MOS transistor 141,142 that can be by measuring symmetry in the above-mentioned testing element are in the conducting electric current that the same terms produces down, monitor in the manufacture process whether produce skew between word line structure and zanjon electric capacity.
The method of the concentration abnormality of embedding layer comprises the following steps in the detection trench type capacitor provided by the invention, and a chip 100 at first is provided, and this chip has a Cutting Road district and a memory cell areas at least.
Then, form a testing element, and form a plurality of memory cell in this memory cell areas of this chip 100 simultaneously in this Cutting Road 160 of this chip 100, wherein the structure of this testing element as shown in Figure 3, and the structure of this memory cell is as shown in Figure 1 and Figure 2.
Then, by applying a set bias voltage V
BiasTo rectangle word line 12a, and a set voltage V
DCIn between the first contact plunger CS1 and the 3rd contact plunger CB1, and the suspension joint second contact plunger CS2, to record first electric current I of transistor 141
1In addition, by applying a set bias voltage V
BiasTo rectangle word line 12a, and a set voltage L
DCIn between the second contact plunger CS2 and the 3rd contact plunger CB1, and the suspension joint first contact plunger CS1, to record first electric current I of transistor 142
2
Then, according to first and second electric current I
1, I
2, and above-mentioned formula three, formula four are estimated the rectangle word line 12a on the testing element and the overlapping degrees of offset of trench type capacitor 110.At last, by the overlapping degrees of offset of rectangle word line 12a on the testing element and trench type capacitor 110, the word line structure in the plural memory cell of estimation memory cell areas and the overlapping degrees of offset of trench type capacitor.
Because when photomask is offset, no matter be the skew that the testing element on memory cell areas or the Cutting Road all can produce unanimity, therefore, by the testing element on the Cutting Road, can reflect the situation that whether overlaps skew between the grid structure of memory cell and zanjon electric capacity.
In addition, testing element of the present invention and method of testing are arranged at testing element on the Cutting Road, can carry out identical manufacture process with memory cell areas synchronously, whether in the monitoring trench type capacitor there be unusually the doping content of embedding layer, and avoid occupying the space of speech memory cell areas
Though the present invention with preferred embodiment openly as above; right its is not in order to restriction the present invention, any those of ordinary skill in the art, without departing from the spirit and scope of the present invention; can do equivalence and change and retouching, so protection scope of the present invention is as the criterion with claim.
Claims (11)
1. the testing element of memory word line structure and the overlapping skew of capacitor is arranged in the Cutting Road of a chip, it is characterized in that this testing element comprises:
One trench type capacitor is arranged in this Cutting Road, has the plate of imbedding;
One rectangle word line is arranged on this Cutting Road, this trench type capacitor of cover part;
One first via is crossed word line and one second and is passed by word line, is arranged at this both sides, trench type capacitor top;
One first doped region and one second doped region are arranged at this rectangle word line and this first via respectively and cross between the word line, and this rectangle word line and this second passed by between the word line;
One first contact plunger is coupled to this first doped region;
One second contact plunger is coupled to this second doped region; And
One the 3rd contact plunger couples this and imbeds plate.
2. the testing element of memory word line structure according to claim 1 and the overlapping skew of capacitor is characterized in that, also comprises at least one the 4th contact plunger, is coupled to this rectangle word line.
3. the testing element of memory word line structure according to claim 1 and the overlapping skew of capacitor, it is characterized in that between described first contact plunger and the 3rd contact plunger in order to recording one first current value, and between this second contact plunger and the 3rd contact plunger in order to record one second current value.
4. the testing element of memory word line structure according to claim 1 and the overlapping skew of capacitor it is characterized in that the described width that first, second passes by word line all equates, and the width of this rectangle word line is passed by the width of word line greater than this first, second.
5. the testing element of memory word line structure according to claim 1 and the overlapping skew of capacitor, the width that it is characterized in that described rectangle word line is 0.6 micron.
6. the method for testing of memory word line structure and the overlapping skew of capacitor is characterized in that it comprises the following steps:
One chip is provided, and this chip has a Cutting Road and a memory cell areas at least;
This Cutting Road in this chip forms a testing element, and simultaneously forms a plurality of memory cell in this memory cell areas of this chip, and wherein this testing element comprises:
One trench type capacitor is arranged in this Cutting Road, has the plate of imbedding;
One rectangle word line is arranged on this Cutting Road, this trench type capacitor of cover part;
One first via is crossed word line and one second and is passed by word line, is arranged at this both sides, trench type capacitor top;
One first doped region and one second doped region are arranged at this rectangle word line and this first via respectively and cross between the word line, and this rectangle word line and this second passed by between the word line;
One first contact plunger is coupled to this first doped region;
One second contact plunger is coupled to this second doped region; And
One the 3rd contact plunger couples this and imbeds plate;
Measure one first current value between first contact plunger and the 3rd contact plunger respectively, and one second current value of this second contact plunger and the 3rd contact plunger;
According to this first with this second current value, estimate on this testing element this rectangle word line structure with should
The overlapping degrees of offset of trench type capacitor; And
By the overlapping degrees of offset of this rectangle word line on this testing element and this trench type capacitor, estimate the word line structure in these memory cell of this memory cell areas and the overlapping degrees of offset of trench type capacitor.
7. the method for testing of memory word line structure according to claim 6 and the overlapping skew of capacitor is characterized in that described testing element also comprises at least one the 4th contact plunger, is coupled to this rectangle word line.
8. the method for testing of memory word line structure according to claim 6 and the overlapping skew of capacitor, it is characterized in that, by applying set this rectangle word line that is biased into, one set voltage is between this first contact plunger and the 3rd contact plunger, and while this second contact plunger of suspension joint, and record this first electric current.
9. the method for testing of memory word line structure according to claim 6 and the overlapping skew of capacitor, it is characterized in that, by applying set this rectangle word line that is biased into, one set voltage is between this second contact plunger and the 3rd contact plunger, and while this first contact plunger of suspension joint, and record this second electric current.
10. the method for testing of memory word line structure according to claim 6 and the overlapping skew of capacitor, it is characterized in that described testing element this first, second pass by word line width equate that all and the width of this rectangle word line is passed by the width of word line greater than this first, second.
11. the method for testing of memory word line structure according to claim 6 and the overlapping skew of capacitor, the width that it is characterized in that this rectangle word line of described testing element is 0.6 micron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02141562.5A CN1248301C (en) | 2002-09-02 | 2002-09-02 | Testing component including work line of memory and capacitor overlaped and offset as well as its testing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02141562.5A CN1248301C (en) | 2002-09-02 | 2002-09-02 | Testing component including work line of memory and capacitor overlaped and offset as well as its testing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1481009A CN1481009A (en) | 2004-03-10 |
| CN1248301C true CN1248301C (en) | 2006-03-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN02141562.5A Expired - Lifetime CN1248301C (en) | 2002-09-02 | 2002-09-02 | Testing component including work line of memory and capacitor overlaped and offset as well as its testing method |
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| CN (1) | CN1248301C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109411448B (en) * | 2018-10-15 | 2020-10-02 | 武汉新芯集成电路制造有限公司 | Reliability test structure and test method |
| CN112838017A (en) * | 2019-11-22 | 2021-05-25 | 长鑫存储技术有限公司 | Photoetching pattern detection method and system |
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2002
- 2002-09-02 CN CN02141562.5A patent/CN1248301C/en not_active Expired - Lifetime
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| Publication number | Publication date |
|---|---|
| CN1481009A (en) | 2004-03-10 |
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Granted publication date: 20060329 |
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