CN1246892C - Method and structure for testing embedded analog/mixed signal magnetic core - Google Patents
Method and structure for testing embedded analog/mixed signal magnetic core Download PDFInfo
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Abstract
The present invention relates to a method for testing embedded analog magnetic cores in integrated-circuit chips with microprocessor magnetic cores and memory magnetic cores, which comprises the following steps: a testing register is arranged on an integrated-circuit chip between a microprocessor magnetic core and an analog magnetic core to be tested to test the microprocessor magnetic core and a memory magnetic core, an assembly language test program running on the microprocessor magnetic core is used so as to generate a test pattern by the microprocessor magnetic core, the test pattern is applied to the analog magnetic core through the microprocessor magnetic core, and the response value of the analog magnetic core is obtained by the microprocessor magnetic core or an external test system.
Description
Technical field
The present invention relates to be used for the method and structure of the embedded kernel of the IC of system on the test chip (SoC:system-on-a-chip), more particularly, relate to test the method and structure of the analog kernel among system on chip (SoC) IC based on microprocessor.
Background technology
In the last few years, ASIC (application-specific IC) technology developed into system on chip (SoC) notion based on embedded kernel from the chipset basic concept.A SoC IC comprises the various functional blocks that can use once again, for example microprocessor, interface, storage array and DSP (digital signal processor).This functional block that designs in advance is commonly called " kernel " (cores).
Fig. 1 is the schematic diagram of example of the internal structure of the such SoC IC of expression.In the example of Fig. 1, SoC IC 10 comprises a micro-processor kernel 12, memory core 13-16, specific function kernel 21-23, a phase-locked loop (PLL) kernel 25,26, A/D of test access port (TAP) (modulus) and D/A (digital-to-analogue) kernel 27, PCI (interface) kernel 28 and glue logic circuit (supporting logical circuit as I/O etc.).How testing this embedded kernel is a new and complicated problems in the IC test.The present invention is exactly this embedded kernel that is used for testing among the SOC IC, particularly simulates and/or the mixed signal kernel, as the method and structure of analog to digital converter (ADC) and digital to analog converter (DAC).
The test of embedded analog kernel is considered to a difficult problem in the SoC IC test.Usually, use various tests to visit for example digital to analog converter (DAC) and analog to digital converter embedded simulated blocks such as (DAC), and carry out this test by for example specialised hardware of mixed signal automatic testing equipment (ATE) or IC tester with design (DFT) scheme.The difficulty of testing embedded analog piece is dual; At first be the visit simulated block so that can encourage by application testing, the response that secondly is the observation simulated block is to be used for evaluation.Need analog signal to be output as the fact of analog signal based on these modules, so further increased difficulty as test input or their response.Like this, in test, just can not carry out simple binary system relatively.
In aforesaid routine techniques, the simulation and the mixed signal block of coming test case such as DAC and ADC as the special mixed signal test device of mixed-signal IC tester have been used.No matter be the DAC/ADC or the embedded DAC/ADC of monolithic, this method of testing is identical.When the inlet of the input and output among the DAC/ADC of monolithic had passed main input one output pin, use test point inserted and tests input one output that visits embedded DAC/ADC with logic (DFT).
Offset voltage (Vos), FSR full scale range (FSR:Full Scale Range), whole code value, particularly missing code (missing codes) and main (major transitions), differential nonlinearity (DNL) and the integral nonlinearity degree (INL) etc. of changing all are the key parameters that is used to the DAC/ADC test.Normally usedly be used to measure code to change level be AC bar chart method, slope bar chart method and code density method of testing in the hope of the method for testing of these parameters.
In all conventional methods, a specialized hardware is used near the load board of device just tested in the ATE system (DUT).When utilizing the mixed-signal IC tester to test, the tester pin interface circuit is used to test pattern and uses and measure, and the response evaluation is finished by the software of tester.In some projects about simulation built-in self-test method, hardware is used for producing test and response evaluation (on the IEEE J. solid-state circuit 318-330 page or leaf in March, 1999, author be " being used for the generation of the chip analog signals of mixed signal built-in self-test " of B.Dufort and G.W.Roberts) on the special-purpose chip.Yet the method for this routine needs a large amount of additional hardware (overhead), causes productivity ratio to descend and the cost increase.In addition, this hardware system expense causes performance loss, for example, and signal propagation delays.
Summary of the invention
Therefore, an object of the present invention is to provide the embedded simulation among the IC of system on a kind of test chip (SoC) and/or the method and structure of mixed signal kernel, it does not have the increase of the overhead of hardware among the SoCIC basically.
Another object of the present invention provides the method and structure of the embedded analog kernel among the IC of system on a kind of test chip (SoC), and it is not basically to the unfavorable factor on the performance of SoC IC.
A further object of the present invention provide embedded analog kernel among the IC of system on a kind of test chip (SoC), have high testing efficiency and low cost method and a structure.
One aspect of the present invention is a kind of method of testing the embedded simulation kernel in the integrated circuit (IC) chip that has micro-processor kernel and memory core in it.This method is made of the following step: provide a scratchpad register at micro-processor kernel with in the integrated circuit (IC) chip between the tested simulation kernel; Test this micro-processor kernel and memory core; Use an assembler language test program that on this micro-processor kernel, moves, produce a test pattern by this micro-processor kernel; By this micro-processor kernel this test pattern is applied to this simulation kernel, and the response of this simulation kernel is provided by this micro-processor kernel or test macro that provides from this integrated circuit (IC) chip outside.
In above-mentioned method of testing, at first test this micro-processor kernel by using pseudo-random data repeatedly to carry out microprocessor instruction and obtain end value.Then, by generating the storage test pattern and will storing this micro-processor kernel that test pattern is applied to this memory core and tries to achieve the value of the storage data in this memory core and test this memory core.The test of aforesaid micro-processor kernel and memory core is by the independent U.S. Patent application 09/170,179,09/182,382 of identical inventor's submission of the present invention and 09/183,033 theme.
Another aspect of the present invention is the structure that test simulation/the mixed signal kernel is used.This structure comprises: be formed at this micro-processor kernel and with a scratchpad register in the integrated circuit (IC) chip between the tested simulation kernel; Between this scratchpad register and this simulation kernel, be used for selectively providing a multiplexer of data to this simulation kernel; Be used for repeatedly carrying out microprocessor instruction and try to achieve integrality and the device by by this micro-processor kernel generation one storage test pattern test a memory core and try to achieve this result of this result to guarantee micro-processor kernel; With one be used for providing the main frame that can carry out test program to this micro-processor kernel by an interface circuit; Wherein, this simulation kernel is provided a test pattern that is generated by this micro-processor kernel, and is tried to achieve the value of the synthetic output of this simulation kernel by this microprocessor or this main frame.
According to the present invention, this method of testing does not need large-area overhead (it only needs a register and a multiplexer among the system on chip IC).Because this hardware system expense can be ignored, so this new method of testing can not cause performance loss.The present invention can also avoid specific testing equipment, therefore, need in SoC IC design special-purpose observation and control point be set.This method can be applicable to standard DAC/ADC product, also can be used for based on the embedded analog kernel in the system on chip of microprocessor.
Description of drawings
Fig. 1 is the schematic diagram of internal structure that expression has the large scale integrated circuit (LSI) that is commonly called system on chip (SoC) IC of a plurality of embedded kernels;
Fig. 2 is the schematic diagram of the total of the expression analog kernel that is used for testing SoC IC among the present invention;
Fig. 3 is the schematic diagram that expression is used for testing the basic structure among the SoC IC of simulation among the SoC IC and/or mixed signal kernel among the present invention;
Fig. 4 A and 4B are the schematic diagrames of the graphic extension of the various test parameters that relate in the simulation kernel that is illustrated in as DAC/ADC;
Thereby Fig. 5 represent to be applied among the SoC IC little processing kernel, from the outside, with generating the test signal that is applied to the analog kernel and trying to achieve an example of the assembler language test program of response.
Embodiment
The invention provides one and be used for testing the simulation among system on chip (SoC) IC with micro-processor kernel and memory core and/or the method and structure of mixed signal kernel.Typically, the analog kernel is ADC (analog to digital converter) and DAC (digital to analog converter).In this method of testing, at first test micro-processor kernel, then, utilize the rated output of this micro-processor kernel to generate the test pattern that is used for the analog kernel.This micro-processor kernel is applied to this with this test pattern and wants tested analog kernel, and judges fault by the value of trying to achieve this test response.The present inventor is at the method and structure of having described the micro-processor kernel among the test SoC IC in the U.S. Patent application of submitting on October 29th, 1,998 09/182,382.Except the negligible hardware that is additional to this micro-processor kernel, this method of testing is without any need for design change or as being used for the additional circuit (hardware system expense) of conventionally test with design (DFT) and built-in self-test (BIST) method.
About being embedded in the DAC/ADC among such SoC IC, it is pointed out that its input was normally accessible when the output of working as ADC was inaccessible.On the other hand, when the input of DAC when being inaccessible, its output is normally accessible.Like this, the simplest form of testing DAC is exactly (on the chip) generation test and excitation (pattern) in this chip, because the input of this DAC is inaccessible, and responds evaluation by outside ATE (sheet is outer), because output is accessible.Similarly, the simplest form of test ADC is exactly to be generated and the application testing excitation by ATE, and responds evaluation in this chip, because output is inaccessible.
Fig. 2 is the schematic block diagram that expression is used for testing the structure of the analog kernel among the SoC IC.In Fig. 2, provide the automatic testing equipment (ATE) that comprises a main frame 31, a hard disk 33 and an I/O interface 36 in the outside of SoC IC.The IC tester that the example of ATE is a routine.Typically, 33 one of the storage of this hard disk are used for testing the test program of the simulation kernel of SoCIC.Main frame 31 provides the executable code of assembler language test program by little processing kernel 12 of I/O interface 36 in the SoC chip.This assembler language test program converts binary form to by the assembler of little processing kernel 12.This assembler can be arranged in the main frame 31 of SoC outside.Like this, micro-processor kernel 12 generates test pattern from this object code.These test patterns are applied to the analog kernel.
Fig. 3 is the schematic block diagram that expression is used for testing the basic structure among the SoC IC of the analog kernel among the SoC IC among the present invention.Fig. 3 represents tested DAC27 and micro-processor kernel 12, and scratchpad register 44 and multiplexer 46.This scratchpad register 44 and multiplexer 46 in dotted line only are the external hardwares that is added among the SoC IC.
This scratchpad register 44 will be applied to DAC 27 with tested by the test data (pattern) that micro-processor kernel 12 produces.Test data in the scratchpad register 44 is provided by a data register in the microprocessor.Multiplexer 36 is based on the mode select signal test data of self-test register 44 or import data normally and be sent to DAC 27 in the future selectively.Under test pattern, multiplexer 46 provides test data to DAC, and under normal mode, it provides normal input data to DAC 27.
The content of scratchpad register 44 can be changed by indexed addressing, for example by the addressing by any one Microprocessor Address register.The realization of scratchpad register 44 can be an independently memory cell of register or a special use.Scratchpad register 34 and multiplexer 46 can be carried out separately or when having bus on the chip, be performed in the bus on this chip.
In the structure of Fig. 2 and 3, under micro-processor kernel 12 trouble-free hypothesis, then can carry out the test of ADC/DAC by micro-processor kernel 12.The method and structure of testing such embedded microprocessor kernel is at the U.S. Patent application of being submitted on October 29th, 1998 by identical inventor of the present invention 09/182, be described in the U.S. Patent application 09/183,033 that on October 30th, 382 and 1998 submitted to.The purpose that is used for this test has been developed a kind of assembly language program(me) (assembler language with microprocessor is write), with when being carried out by micro-processor kernel 12, generates essential test and excitation.Use the microprocessor assembler to convert such test program to binary code.This binary code is stored in the ATE memory in the hard disk 33 for example, and can it be applied to micro-processor kernel 12 by interface circuit 36.
This micro-processor kernel 12 is carried out and is comprised this binary code of microprocessor instruction and data, thereby generates the required test pattern that is used for DAC/ADC 27.DAC/ADC 27 is for the response of this test pattern or by micro-processor kernel 12 evaluation simultaneously, or is stored in the on-chip memory to be used for later evaluation.Perhaps, the response of DAC/ADC 27 also can come evaluation by ATE (main frame 31).
When micro-processor kernel 12 also carries out under the situation of evaluation, such evaluation process is undertaken by another program of carrying out on the micro-processor kernel 12, also develop this program similarly, convert thereof into binary code and be applied to micro-processor kernel 12 with assembler language.In response to this evaluation program, micro-processor kernel 12 carries out the response of necessary calculating in the hope of ADC/DAC, and determines wherein whether to have fault.It should be noted that then this response should be stored in the ATE memory, and is passed through/fault with decision by the ATE evaluation if on-chip memory is not enough to store this ADC/DAC to answering.
Aforesaid order is summarized as follows:
Step 1: test micro-processor kernel and memory core.A kind of new method that is used for this test is described in the identical inventor's of the present invention who mentions in the above the patent application.
Step 2: develop an assembly language program(me) that can generate the required test pattern that is used for DAC/ADC kernel 27 that will be tested.In Fig. 5, provided the example procedure that generates this test pattern that is used for various DAC/ADC parameters.
Step 3: use the assembler of this micro-processor kernel 12 to generate the object code of this assembly language program(me).A general process that generates this object code has been described in above-mentioned patent application.
Step 4: this object code is applied to micro-processor kernel 12 by an interface circuit.
Step 5: micro-processor kernel 12 generates the DAC/ADC test pattern, and this test pattern is applied to want tested DAC/ADC kernel 27.
Step 6: the response that nuclear signal in the DAC/ADC was collected and tried to achieve to micro-processor kernel 12.On the one hand, this response is collected in the on-chip memory.Micro-processor kernel 12 is carried out this test evaluation program and is calculated specific parameter value.Based on these values, micro-processor kernel 12 decision is sent this information by/fault and to main frame.On the other hand, this response is collected in the main frame in ATE or other tester.Program of main frame execution calculates various parameters and decision is passed through/fault.This program needs not to be the form with assembler language.
Fig. 4 A and 4B represent the various test parameters that relate in the simulation kernel of for example digital to analog converter (DAC) and analog to digital converter (ADC).With reference to Fig. 4 A and 4B, typical test parameter is as follows:
(P1) offset voltage (Vos): for DAC, offset voltage Vos is an analog output voltage when applying invalid or all-zero code in the input.The width of test vector is identical with the width that DAC differentiates the position, and length is 2
N, as 16,32,64 or the like.In addition,, repeatedly use identical vector, and get the mean value that responds output and calculate offset voltage Vos for fear of the distortion that causes by noise.Just can obtain this test vector by apply complete zero to a microprocessor data register simply.A single microprocessor instruction " MVI0000H, Di " is used to this purpose, and wherein, Di is an i data register.In the example of Fig. 5, replace i register to be used for explanation with register D1.
(P2) FSR full scale range (FSR): for DAC, FSR full scale range FSR is when apply this full scale code (complete 1) value (V in the input
FS) time analog output voltage and the analog output voltage when applying invalid (complete 0) code value (Vos) in the input between poor, as FSR=V
Fs-Vos.Be used for this FSR full scale range voltage V
FSTest and excitation be complete 1 value, like this, this process is identical with the process that generates the test vector be used for offset voltage Vos.Thus, two instructions are provided for the essential test and excitation (complete 0 and complete 1 value) of FSR.
(P3) missing code and main the transformation: for DAC, the main transformation is to cause that a carry is to reverse minimum effective nonzero digit and transformation between the code of next bit is set.For the DAC of N position, from 0 to 2
N-1 counter provides all possible code value, like this, just is enough to test any missing code and main the transformation.One assembly language program(me) provides this tally function.It should be noted that for code changes test, only main code change just enough, for example 1/4 of FSR full scale range, 1/2 and 3/4 and need not to use all code values.
(P4) differential nonlinearity: for DAC, it is the maximum deviation that realistic simulation output amplitude between adjacent input code departs from 1 (one) LSB (least significant bit).It will demand perfection 0, complete 1 and a linear precedence of all codes input.Like this, the process of the combination that provides in above-mentioned parameter P2 and P3 provides necessary test and excitation.
(P5) integral nonlinearity degree: for DAC, it be code edge or simulation output depart from first and last code between the maximum deviation of the straight line painted.Like this, the process of the combination that provides in above-mentioned parameter P2 and P3 provides necessary test and excitation.
After this test pattern is applied to tested DAC/ADC, obtain above-mentioned parameter by following processes.Though with the computational methods vague generalization, the use of response is exported in the digitlization of following case representation DAC for explanation.
(S1) offset voltage (Vos): as mentioned above,, preferably repeatedly use complete 0 vector and therefore obtain a mean value for the distortion that abates the noise.In order to calculate Vos, the output of DAC is added up 2 in a data register of micro-processor kernel 12
NInferior, wherein N is an integer.This accumulated value N position that moved to right, it is equivalent to divide operations, to obtain this mean value.
(S2) FSR full scale range (FSR): for DAC, this value is FSR=V
FS-Vos, wherein, V
FSBe the FSR full scale range voltage of measuring, the offset voltage of Vos for measuring.Obtain FSR full scale range voltage V
FSMechanism identical with the mechanism that obtains offset voltage, except for FSR full scale range V
FS, input vector is complete 1 rather than complete 0.Therefore, for FSR full scale range FSR, the output of DAC27 under complete 0 is accumulated in the data register (D1), and the output of DAC27 under complete 1 is stored in another data register (D2).The content of two data register D1 and D2 moves right the N position to obtain voltage V
FSAnd Vos.At last, poor between register D2 and the D1, promptly D2-D1 provides this FSR full scale range FSR.The value FSR of this calculating can be stored in another data register (D3).Aforesaid step is as described below:
(S2-a) described in step (S1), obtain offset voltage Vos.This value of storage Vos in data register D1.
(S2-b) process of usefulness described in step (S2) obtains the V under complete 1
FSShould be worth V
FSBe stored among the data register D2.
(S2-c) carry out subtraction D2-D1 to obtain FSR full scale range FSR.Should be stored among the data register D3 by value FSR.Carry out this data register D1-D3 by specifying the internal register in the memory cell in the memory core among micro-processor kernel or the SoC IC.
(S3) missing code and main the transformation: digitlization DAC exports and it is stored in on-chip memory or the ATE memory as hard disk 33.Use two extra data registers (D4 and D5) under two continuous code values, to store digitized output.Carry out this data register D1-D5 by specifying the internal register in the memory cell in the memory core among micro-processor kernel or the SoC IC.As previously described, the DAC27 under a counter (carrying out under assembler language) is applied to this code value to test.The content representation code of data register D4 and D5 changes.When register D4 or invalid value of D5 acquisition, detect a missing code.This main transformation of difference identification between the value of D4 and D5.
(S4) DNL degree (DNL): after FSR full scale range FSR is calculated, carry out the size that a further divide operations obtains LSB (least significant bit).Store two digitlizations outputs under the continuous code with two extra data registers (D4 and D5), simultaneously, a counter is applied to DAC under the foregoing test with this code value.From D5, deduct data D4 DNL promptly is provided.Further the DNL that will calculate compares with the maximum of setting in advance, passes through/Reflector to generate one.Abovementioned steps is:
(S4-a) obtaining offset voltage Vos described in step (S1) also should be stored among the data register D1 by value Vos.Described in step (S2-b), obtain full scale voltage V
FSThis value is stored among the register D2.Described in step (S2-c), obtain FSR.
(S4-b) with 2
N-1 divided by the size of FSR with acquisition LSR.This value is stored among the register D6.
(S4-c) corresponding to about missing code and the main step (S3) that changes, use as described from 0 to 2
N-1 binary sequence.
(S4-d) will be placed in register D4 and the D5 in the output of the digitlization under each continuous code.Calculate the D4-D5 difference to obtain DNL.
(S4-e) DNL that calculates and the DNL that sets are in advance compared.If the DNL that calculates then produces a Reflector greater than the DNL that sets in advance.
The major advantage of this method of testing is to utilize insignificant area overhead to test very effectively embedded analog circuit.The present invention has avoided special testing apparatus, and therefore special-purpose observation and control point need be set in design.Though we with ADC/DAC as an example, this method is by vague generalization and can be applicable to any analog circuit.
Though only specify and described a most preferred embodiment here, but should be understood that, do not breaking away under essence of the present invention and the desired extent, under the inspiration of above-mentioned instruction and in the scope of following claim, many changes of the present invention and change are possible.
Claims (15)
1. a method that is used for testing the embedded simulation kernel on the integrated circuit (IC) chip that has a micro-processor kernel and a memory core in it comprises the following steps:
Provide a scratchpad register at this micro-processor kernel with on the integrated circuit (IC) chip between the tested simulation kernel;
By repeatedly carrying out microprocessor instruction and trying to achieve the result and test this micro-processor kernel;
Use an assembler language test program that on this micro-processor kernel, moves, to produce a test pattern by this micro-processor kernel;
To be applied to this simulation kernel by this scratchpad register by this test pattern that this micro-processor kernel generates, and the response of this simulation kernel will be provided by this micro-processor kernel or test macro that provides from this integrated circuit (IC) chip outside.
2. the method that is used to test embedded simulation kernel as claimed in claim 1, also be included in by the micro-processor kernel that generates memory test patterns and this memory test patterns is applied to described memory core and assesses this memory core and test before this simulation kernel, test the step of this memory core.
3. the method that is used to test embedded simulation kernel as claimed in claim 1, wherein, the test program that is applied to this micro-processor kernel is the object code of this assembler language test program.
4. the method that is used to test embedded simulation kernel as claimed in claim 3, wherein, described assembler language test program offers described micro-processor kernel by external host by the I/O interface.
5. the method that is used to test embedded simulation kernel as claimed in claim 3, wherein, described assembler language test program offers described micro-processor kernel by exterior I C tester by the I/O interface.
6. the method that is used to test embedded simulation kernel as claimed in claim 1, wherein, this integrated circuit (IC) chip is a system on chip IC.
7. the method that is used to test embedded simulation kernel as claimed in claim 1, wherein, this embedded simulation kernel is analog to digital converter and/or digital to analog converter.
8. structure that is used to test the embedded simulation kernel on the integrated circuit (IC) chip that has a micro-processor kernel and a memory core in it comprises:
Scratchpad register on integrated circuit (IC) chip that is formed between this micro-processor kernel and the tested simulation kernel;
One between this scratchpad register and this simulation kernel, be used for optionally data being offered the multiplexer of this simulation kernel;
Be used for repeatedly carrying out microprocessor instruction and assess this result with the integrality of guaranteeing this micro-processor kernel and be used for by generating a memory test patterns by this micro-processor kernel and assessing the device that a memory core is tested this memory core; With
One is used for providing the main frame that can carry out test program to this micro-processor kernel by interface circuit;
Wherein, this simulation kernel is provided a test pattern that is produced by this micro-processor kernel by this scratchpad register, and result's output of this simulation kernel comes evaluation by this micro-processor kernel or this main frame.
9. the structure that is used to test embedded simulation kernel as claimed in claim 8, wherein, when when this multiplexer provides test mode signal, this scratchpad register is sent to tested simulation kernel with test pattern from this micro-processor kernel by this multiplexer.
10. the structure that is used to test embedded simulation kernel as claimed in claim 8, wherein, before testing this simulation kernel, carry out the test of this memory core by this micro-processor kernel that produces a memory test patterns and this memory test patterns is applied to described memory core and assesses this memory core.
11. the structure that is used to test embedded simulation kernel as claimed in claim 8, wherein, the test program that is applied to this micro-processor kernel is the object code of an assembler language test program.
12. the structure that is used to test embedded simulation kernel as claimed in claim 11, wherein, this assembler language test program offers this micro-processor kernel by external host by the I/O interface.
13. the structure that is used to test embedded simulation kernel as claimed in claim 11, wherein, this assembler language test program offers this micro-processor kernel by exterior I C tester by the I/O interface.
14. the structure that is used to test embedded simulation kernel as claimed in claim 8, wherein, this integrated circuit (IC) chip is a system on chip IC.
15. the structure that is used to test embedded simulation kernel as claimed in claim 8, wherein, this embedded simulation kernel is analog to digital converter and/or digital to analog converter.
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