CN1245999A - Master backup reverse device - Google Patents
Master backup reverse device Download PDFInfo
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- CN1245999A CN1245999A CN 98118143 CN98118143A CN1245999A CN 1245999 A CN1245999 A CN 1245999A CN 98118143 CN98118143 CN 98118143 CN 98118143 A CN98118143 A CN 98118143A CN 1245999 A CN1245999 A CN 1245999A
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Abstract
The present invention relates to a primary and backup changeover equipment, including differential formation unit capable of converting primary and backup changeover control command into differential level output signal and transferring it into bus mother board and the device capable of making flutter-eliminating treatment of primary and backup changeover control signal and making the control signal form switching control between primary and backup. By using board position control signal to discriminating different slot position said changeover equipment makes the changeover control circuit only on one single-board produce action, and its control signal is differential signal, and is buffered and driven by means of identical devices and is transmitted and delayed through identical passage so as to implement synchronous switching of controlled signal turn-on and turn-off and seamless switching effect.
Description
The present invention relates to reliability engineering, be specifically related to a kind of device of quick realization master backup reverse.
The backup of circuit (plate) and redundancy are to improve the most direct, the effective method of electronic system reliability.Backup can be divided into 1+1 backup, backup in 1: 1 and n+1 backup usually.Wherein: 1+1 backup, claim Hot Spare again, it is meant that circuit has adopted dual backup, arranged side by side between circuit board, while operate as normal does not almost have any difference; Backup in 1: 1 claims cold standby again, though it is meant that circuit has adopted dual backup, the operating state difference of two circuit boards always has only a plate working completely, and promptly one main one is equipped with mode and works; N+1 backup is meant that the shared same circuit board of the identical circuit board of n piece backs up, and after any generation unusually in the n piece plate that backs up, all backs up plate thus and substitutes work.Further backup is dual above multiple duplication, and it can effectively improve the reliability of fallback circuit even machine system, and is widely used in electronic product fields such as communication, industry control, aviation, to satisfy it is had the occasion of high reliability requirement.Because the backup of 1+1 does not have the branch of primary and secondary weight, the normally output of composite signal, there is not the masterslave switchover problem, and to 1: 1 or n+1 backup, circuit in being in work or equipment need artificial the execution to switch order or when breaking down, just can take place active and standby and switch (switching) problem, be i.e. the process of work, i.e. masterslave switchover from main board (main system) work of transformation to standby plate (standby system).Thisly switch the direct output performance that influences signal, may cause the non-continuous event of phase of output signal, i.e. phase hit.The amplitude of saltus step sometimes is that institute of system is unallowed, and this masterslave switchover performance to system has proposed the more requirement of Gao Gengyan.The saltus step problem of phase of output signal when the present invention mainly considers how to control masterslave switchover.In the prior art, realize the masterslave switchover of n+1 or backup in 1: 1, its circuit theory is the same.As the most general way is to adopt rest-set flip-flop or JK flip-flop.Its fundamental diagram as depicted in figs. 1 and 2, utilize rest-set flip-flop (among Fig. 1, constitute the most basic rest-set flip-flop by 2 with door) or JK flip-flop (among Fig. 2, by 2 or constitute the most basic JK flip-flop) can pass through R, S or two trigger ends of J, K produce the control Q of two opposite states and the characteristic of QN output, by triggering the state turnover that input R, S or J, K make Q and QN, control having or not of its output signal that exports main board and standby plate to, guarantee to have only a veneer all the time in work.Be that example describes only further with the rest-set flip-flop shown in Fig. 1.
The dotted line left side is the A plate, and dotted line the right is the B plate, and the cross complaint holding wire has 2 to finish interconnection on bus mother board, and purpose is to guarantee that A, B two groove potential energies use the same veneer, finish active and standby double copies function.The masterslave switchover control end is R and S, and default setting is a high level, if sufficiently long low level pulse appears in one of R, S, be enough to make the QQN upset, visible by triggering the RS control end, finish the QQN upset, hold enabling of controlling output circuit by QQN again, finish switching of active and standby plate, see the following form.
| R | ?S | ?Q | ?QN |
| ?0 ?0 ?1 ?1 | ?0 ?1 ?0 ?1 | Do not allow 1001 Q QN | |
Hold the circuit on the control board how to enable work as for Q, QN, method is varied, can three-state driver spare, cmos switch etc., do not enumerate one by one here.
When what deserves to be mentioned is actual master/slave switch circuit, also need indispensable practicality to require to have:
When 1, having only a veneer, it must operate as normal.
When 2, when having a veneer, plugging another slave board again, can not influence the work of existing veneer.
3, extracted arbitrarily when one of wherein being by two veneers, another remaining standby plate can guarantee that signal exports continuously.
When 4, active and standby plate exists simultaneously, can finish manual active and standby example and change.
5, two plates exist simultaneously, and when powering on simultaneously again, the priority that can distinguish work is with active and standby.
For this reason, side circuit can become complicated.
What be concerned about most here is the time of masterslave switchover, does an analysis below:
Since masterslave switchover be from (Q=0, therefore QN=1) → (Q=1 QN=0), has two kinds of possible middle transition states to exist, (Q=0, QN=1) → (Q=0, QN=0) → (Q=1 is QN=0) with (Q=0, QN=1) → (Q=1, QN=1) → (Q=1, QN=0).
To Q=0, QN=0 and Q=1, two veneers of QN=1 explanation start simultaneously or forbid work simultaneously, make the signal of exporting to keep the continuity of phase place, wherein the time length of middle transition state depends on the minimal time delay of the gate circuit that adopts, the time delay of (seeing shown in the dotted line among the figure) is relevant during with the cabling of PCB (circuit printing plate), this situation is obvious further with the increase of signal frequency, make that intermediateness Q=0 QN=0 and Q=1 QN=1 relative time are longer, generally also want youngster more than ten nanoseconds, can't satisfy the occasion higher the phase continuity requirement.
The object of the present invention is to provide a kind of novel master backup reverse device, utilize this master backup reverse device, can require under the prerequisite not using the low time delay device of high-performance and satisfy above-mentioned practicality, reach inevitable when overcoming prior art and switching 2 kinds of middle transition states and phase hit, masterslave switchover is controlled in several nanosecond precision finishes, thereby under the prerequisite that guarantees system reliability, the stability and the phase continuity of signal when improving the system mode change greatly by shortening switching time.
The object of the present invention is achieved like this, construct a kind of by active and standby part of master backup reverse device that connects and switch of bus mother board 1 realization, wherein, realize the necessary control signal wire of master backup reverse, adopt interconnection to guarantee being fit to different groove positions with a kind of veneer, described master backup reverse device comprises:
Be arranged on active and standby distinguishing signal end ID0 on the bus mother board 1, work in which unit that is used for pointing out mutually redundant two unit and another unit is in high-impedance state, also be provided with the control signal end Q1Q1N that is used to finish master backup reverse on the described bus mother board 1
First differential formation unit 2, the output signal Q0Q0N that is used for transferring differential level to from the first masterslave switchover control command of controlling trigger end outputs to Q1 end on the described bus mother board.
Second differential formation unit 3, the output signal Q0Q0N that is used for transferring differential level to from the second masterslave switchover control command of controlling trigger end outputs to Q1 end on the described bus mother board,
First jitter elimination and switch control unit 4 are used for handling and forming and enable control signal switching device between active and standby part is carried out switch control carry out jitter elimination from the masterslave switchover control signal of Q1 end on the bus mother board 1,
Second jitter elimination and switch control unit 5 are used for handling and forming and enable control signal switching device between active and standby part is carried out switch control carry out jitter elimination from the masterslave switchover control signal of Q1 end on the bus mother board 1,
Between the Q1 input of described first jitter elimination and switch control unit 4 and ground, be connected with first pull down resistor 6, between the Q1 input of described second jitter elimination and switch control unit 5 and ground, be connected with second pull down resistor 7.
According to master backup reverse device provided by the invention, it is characterized in that described first, second differential formation unit 2 and 3 can be realized by application-specific integrated circuit, also can be replaced realizing by common NOR gate circuit.
According to master backup reverse device provided by the invention, it is characterized in that, can be three state device, cmos switch and light-sensitive realy by enabling of producing of described first, second jitter elimination and switch control unit 4,5 switching device that control signal controls between active and standby part.
Implement master backup reverse device provided by the invention, can when satisfying the backup procedure fail safe, realize the high-speed and flatness of reversed process, simultaneously,, lowered the realization cost of changeover apparatus greatly owing to simple in structure.This board back-up of 1: 1, be based on identical single plate hardware, insert different active and standby groove positions, the control circuit of switching by special-purpose symmetry, realize the same moment switching of signal on the different veneers, owing to used plate (groove) position control signal, distinguished different groove positions, make to have only and switch control circuit in action on the veneer, because control signal is a differential signal, drive through the identity unit buffering, again through same path transmission delay (PCB designs consideration), make that the switching of through and off of manipulated signal is synchronous, so reached the effect of seamless switching.
Below in conjunction with drawings and Examples, further characteristics of the present invention are described, in the accompanying drawing:
Fig. 1 is an electrical schematic diagram of realizing masterslave switchover in the prior art with rest-set flip-flop;
Fig. 2 is an electrical schematic diagram of realizing masterslave switchover in the prior art with the JKS trigger;
Fig. 3 is the principle schematic of an embodiment of active/standby changeover apparatus provided by the invention;
Fig. 4 is the principle schematic that realizes difference unit among Fig. 3 with XOR gate;
Fig. 5 is an ID0 control signal schematic diagram;
Fig. 6 is the circuit diagram of output signal control;
Fig. 7 is the principle schematic of another embodiment of active/standby changeover apparatus provided by the invention.
In conjunction with Fig. 3 circuit theory diagrams, the characteristics and the operation principle of active/standby changeover apparatus of the present invention is described.
1, the common bus motherboard is interconnected:
As shown in Figure 3, master backup reverse device provided by the invention is by being connected a main part on the bus mother board 1, backup is realized master backup reverse, realize on the bus mother board that the necessary control signal wire of master backup reverse adopts interconnection, to guarantee being fit to different groove positions with a kind of veneer (can be main part part or backup), on the bus mother board shown in Fig. 31, setting is by active and standby distinguishing signal end ID0 and master backup reverse control signal end Q1Q1N, wherein: active and standby distinguishing signal end ID0, this ID0 control line is the control signal of active and standby groove position difference, one is high level, one is low level, guaranteed that the control circuit of switching on the mutually redundant circuit board has only an energy job, another is in high-impedance state all the time.In other words, this signal is used for pointing out that work in which unit of mutually redundant two unit and another unit is in high-impedance state, master backup reverse control signal end Q1Q1N provide the control signal of finishing master backup reverse, this finishes control signal Q1 and Q1N that single board main/standby part is switched, is in rp state all the time.
2, first and second differential formation units (2,3): active and standby leading changed the output signal output that control command transfers differential level to, and it requires Q consistent as much as possible with the phase hit edge of QN, as the ps order of magnitude.Difference channel both can adopt the also available common NOR gate circuit of IC dedicated devices such as Fig. 4 to show.
3, first and second jitter elimination and switch control unit (4,5)
The shake that disappears of active and standby control signal disturb is handled, and final transition enabled control signal to switch (three state device, cmos switch, relay etc.), is finished active and standby plate task switching.
4, first and second pull down resistors (6,7)
As shown in Figure 3, between the Q1 input of first jitter elimination and switch control unit 4 and ground, be connected with first pull down resistor 6 (R), between the Q1 input of second jitter elimination and switch control unit 5 and ground, be connected with second pull down resistor 7 (R).
In conjunction with Fig. 3, illustrate that the course of work of active/standby changeover apparatus of this embodiment is as follows:
1, when a plate veneer job is only arranged, the existence of pull down resistor resistance R, the ternary control end that makes is always low level, (this supposition buffer is that low level is effective and guarantee normal output is arranged the buffer contact, otherwise, if buffer when to be high level effective, should use pull-up resistor, relevant extremely several kilohms of the hundreds ofs that are generally with differential driving ability size of the size of resistance).
2, when having a veneer, if insert a veneer, because the control signal of two veneers has only one of them really effective, conflict can not appear in the control signal that (such as the output of A plate effectively, B plate output high resistant) makes active and standby plate switch.
When 3, having active and standby plate at the same time, variation by control end level QQN, having finished active and standby plate switches, because its switching time phase difference AND circuit device and PCB time delay are irrelevant, the absolute static phase that only depends on Q and QN is poor, therefore can reach below the 1ns, this scheme is that any rest-set flip-flop JK flip-flop is too far behind to catch up when realizing the masterslave switchover function.
Fig. 5 shows the situation that is connected of ID0 control line and triple gate, establish this triple gate to enable control end effective when low level.As shown in the figure, when the ID0 control line is the control termination high level (Vcc) of triple gate, difference control signal invalid (Q and QN, be high resistant), when the ID0 control line was the control termination low level (GND) of triple gate, the difference control signal is (Q and QN, one high and one low) effectively.
Fig. 6 shows the situation that manipulated signal is connected with triple gate.As shown in the figure, the control end of triple gate is by grounding through resistance, and promptly the input of being controlled by this tristate gate control end receives the output signal from system, and this signal is provided by described bus mother board 1 with 1: 1 backup mode.Fig. 7 illustrates an alternative embodiment of the invention, wherein with jitter elimination and switch control unit among the last embodiment of tri-state switch replacement, promptly be used to form and enable control signal switching device between active and standby part is carried out switch control, be used to form with tri-state switch 51 and enable control signal switching device between active and standby part is carried out switch control with tri-state switch 41.
Claims (6)
1, a kind of by active and standby part of master backup reverse device that connects and switch of bus mother board 1 realization, wherein, realize the necessary control signal wire of master backup reverse, adopt interconnection to guarantee being fit to different groove positions with a kind of veneer, described master backup reverse device comprises:
Be arranged on active and standby distinguishing signal end ID0 on the bus mother board 1, work in which unit that is used for pointing out mutually redundant two unit and another unit is in high-impedance state, also be provided with the control signal end Q1Q1N that is used to finish master backup reverse on the described bus mother board 1
First differential formation unit 2, the output signal Q0Q0N that is used for transferring differential level to from the first masterslave switchover control command of controlling trigger end outputs to Q1 end on the described bus mother board,
Second differential formation unit 3, the output signal Q0Q0N that is used for transferring differential level to from the second masterslave switchover control command of controlling trigger end outputs to Q1N end on the described bus mother board,
First jitter elimination and switch control unit 4 are used for handling and forming and enable control signal switching device between active and standby part is carried out switch control carry out jitter elimination from the masterslave switchover control signal of Q1 end on the bus mother board 1,
Second jitter elimination and switch control unit 5 are used for handling and forming and enable control signal switching device between active and standby part is carried out switch control carry out jitter elimination from the masterslave switchover control signal of Q1N end on the bus mother board 1,
Between the Q1 input of described first jitter elimination and switch control unit 4 and ground, be connected with first pull down resistor 6, between the Q1N input of described second jitter elimination and switch control unit 5 and ground, be connected with second pull down resistor 7.
2, master backup reverse device according to claim 1 is characterized in that, described first, second differential formation unit 2 and 3 can be realized by application-specific integrated circuit, also can be realized by common NOR gate circuit.
3, master backup reverse device according to claim 1, it is characterized in that, can be three state device, cmos switch and light-sensitive realy by enabling of producing of described first, second jitter elimination and switch control unit 4,5 switching device that control signal controls between active and standby part.
4, a kind of by active and standby part of master backup reverse device that connects and switch of bus mother board 1 realization, wherein, realize the necessary control signal wire of master backup reverse, adopt interconnection to guarantee being fit to different groove positions with a kind of veneer, described master backup reverse device comprises:
Be arranged on active and standby distinguishing signal end ID0 on the bus mother board 1, work in which unit that is used for pointing out mutually redundant two unit and another unit is in high-impedance state, also be provided with the control signal end Q1Q1N that is used to finish master backup reverse on the described bus mother board 1
First differential formation unit 2, the output signal Q0Q0N that is used for transferring differential level to from the first masterslave switchover control command of controlling trigger end outputs to Q1 end on the described bus mother board,
Second differential formation unit 3, the output signal Q0Q0N that is used for transferring differential level to from the second masterslave switchover control command of controlling trigger end outputs to Q1N end on the described bus mother board,
First switch control unit 41 is used to form and enables control signal switching device between active and standby part is carried out switch control,
Second switch control unit 51 is used to form and enables control signal switching device between active and standby part is carried out switch control,
Between the Q1 input of described first switch control unit 4 and ground, be connected with first pull down resistor 6, between the Q1N of described second switch control unit 5 input and ground, be connected with second pull down resistor 7.
5, master backup reverse device according to claim 4 is characterized in that, described first, second differential formation unit 2 and 3 can be realized by application-specific integrated circuit, also can be realized by common NOR gate circuit.
6, master backup reverse device according to claim 4 is characterized in that, can be three state device by enabling of producing of described first, second switch control unit switching device that control signal controls between active and standby part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN98118143A CN1092864C (en) | 1998-08-25 | 1998-08-25 | Master backup reverse device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN98118143A CN1092864C (en) | 1998-08-25 | 1998-08-25 | Master backup reverse device |
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| CN1245999A true CN1245999A (en) | 2000-03-01 |
| CN1092864C CN1092864C (en) | 2002-10-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN98118143A Expired - Fee Related CN1092864C (en) | 1998-08-25 | 1998-08-25 | Master backup reverse device |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006007785A1 (en) * | 2004-07-23 | 2006-01-26 | Huawei Technologies Co., Ltd. | Master-spare converting control circuit and method thereof |
| CN100388737C (en) * | 2004-01-18 | 2008-05-14 | 华为技术有限公司 | Method for realizing LCAS protocol nondestructive switching on source end |
| CN100459503C (en) * | 2006-08-25 | 2009-02-04 | 华为技术有限公司 | Method and system of obtaining physical slot number of single board, and type of slot |
| CN100530996C (en) * | 2004-08-06 | 2009-08-19 | 华为技术有限公司 | System and method for realizing veneer active/standby changeover in communication equipment |
| CN101159525B (en) * | 2007-11-13 | 2011-04-20 | 上海华为技术有限公司 | Veneer master-slave rearranging method and system and a veneer |
| CN101166415B (en) * | 2007-07-09 | 2011-09-14 | 华为技术有限公司 | Master/slave switch circuit and method |
| CN101465670B (en) * | 2007-12-21 | 2013-01-02 | 大唐移动通信设备有限公司 | Method and circuit for eliminating two-shipper control circuit dithering |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100359818C (en) * | 2002-12-30 | 2008-01-02 | 中兴通讯股份有限公司 | Device and method for realizing backup of single plate |
| CN100461645C (en) * | 2003-04-08 | 2009-02-11 | 中兴通讯股份有限公司 | Main and standby boards inverter device and its inversion method |
| CN1299464C (en) * | 2003-06-04 | 2007-02-07 | 中兴通讯股份有限公司 | Method and device for realizing main backup of clock in synchronizing system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5136498A (en) * | 1990-09-26 | 1992-08-04 | Honeywell Inc. | Method for enacting failover of a 1:1 redundant pair of slave processors |
| US5418490A (en) * | 1994-03-01 | 1995-05-23 | Tx Rx Systems, Inc. | Failure responsive alternate amplifier and bypass system for communications amplifier |
| US5941994A (en) * | 1995-12-22 | 1999-08-24 | Lsi Logic Corporation | Technique for sharing hot spare drives among multiple subsystems |
| US5777874A (en) * | 1996-02-12 | 1998-07-07 | Allen-Bradley Company, Inc. | Programmable controller backup system |
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- 1998-08-25 CN CN98118143A patent/CN1092864C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100388737C (en) * | 2004-01-18 | 2008-05-14 | 华为技术有限公司 | Method for realizing LCAS protocol nondestructive switching on source end |
| WO2006007785A1 (en) * | 2004-07-23 | 2006-01-26 | Huawei Technologies Co., Ltd. | Master-spare converting control circuit and method thereof |
| CN100530996C (en) * | 2004-08-06 | 2009-08-19 | 华为技术有限公司 | System and method for realizing veneer active/standby changeover in communication equipment |
| CN100459503C (en) * | 2006-08-25 | 2009-02-04 | 华为技术有限公司 | Method and system of obtaining physical slot number of single board, and type of slot |
| CN101166415B (en) * | 2007-07-09 | 2011-09-14 | 华为技术有限公司 | Master/slave switch circuit and method |
| CN101159525B (en) * | 2007-11-13 | 2011-04-20 | 上海华为技术有限公司 | Veneer master-slave rearranging method and system and a veneer |
| CN101465670B (en) * | 2007-12-21 | 2013-01-02 | 大唐移动通信设备有限公司 | Method and circuit for eliminating two-shipper control circuit dithering |
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