CN1239822A - Plug manufacturing method - Google Patents

Plug manufacturing method Download PDF

Info

Publication number
CN1239822A
CN1239822A CN 98115222 CN98115222A CN1239822A CN 1239822 A CN1239822 A CN 1239822A CN 98115222 CN98115222 CN 98115222 CN 98115222 A CN98115222 A CN 98115222A CN 1239822 A CN1239822 A CN 1239822A
Authority
CN
China
Prior art keywords
plug
dielectric layer
layer
manufacture
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN 98115222
Other languages
Chinese (zh)
Other versions
CN1115724C (en
Inventor
何青原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SHIDA INTEGRATED CIRCUIT CO Ltd
Original Assignee
SHIDA INTEGRATED CIRCUIT CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SHIDA INTEGRATED CIRCUIT CO Ltd filed Critical SHIDA INTEGRATED CIRCUIT CO Ltd
Priority to CN 98115222 priority Critical patent/CN1115724C/en
Publication of CN1239822A publication Critical patent/CN1239822A/en
Application granted granted Critical
Publication of CN1115724C publication Critical patent/CN1115724C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Plug manufacture includes the steps of the formation on one substrate of one dielectric layer with opening to expose the area to be used to conduct other structure; the formation of adhesive layer to cover the opening area and conduct other structure; the formation of plug matter layer in the opening area and itching to form plug with height slightly lower than that of the dielectric layer; and the etching of the dielectric layer to make the height of the dielectric layer basically the same as that of plug.

Description

Plug manufacture
The present invention relates to a kind of semi-conductive manufacture craft, the manufacture method of particularly a kind of connector (plug) can avoid the connector surface to produce the groove phenomenon.
Tungsten plug is widely used on the multiple internal connecting lines (Interconnection) of ultra-large type integrated circuit.And at present most important be exactly how to control tungsten to eat-back (etch back) groove (recess) phenomenon that manufacture craft produced.In the tungsten etch back process,, need carry out crossing for a long time etching (overetching) step, to avoid producing short circuit current in order to remove the residual tungsten metal on the wafer fully.Yet the overetched time is long more, and the groove phenomenon of tungsten plug is serious more.And when semiconductor structure needed the stacked structure of multilayer, then the groove phenomenon can be more and more serious.The groove phenomenon can cause the electrical variation of semiconductor element or qualification rate to reduce.And existing chemical mechanical milling method (chemical mechanical polishing though CMP) can alleviate this groove phenomenon, because the machinery of chemical mechanical milling method is too expensive, therefore can increase manufacturing cost.
Figure 1A~1D represents the manufacturing process profile of existing connector.Please refer to Fig. 1, a substrate 10 at first is provided, this substrate 10 for example is formed with a bottom metal layers 12, and bottom metal layers 12 is to be provided with to be used for the zone of other structure of conducting.Form one dielectric layer 14 with the chemical vapor deposition (CVD) method then and cover underlying structure.Then, with traditional photolithography techniques dielectric layer 14 compositions are exposed bottom metal layers 12 to form an opening 16.
Please refer to Figure 1B, form one deck adhesion layer (glue layer) 18, the bottom metal layers 12 in the covering opening 16 and the sidewall of dielectric layer 14 and dielectric layer 14.The purpose of adhesion layer 18 is to increase the tackness of plug material in the follow-up manufacture craft, and as the usefulness of etch stop.Wherein, the material of adhesion layer for example is titanium (Ti)/titanium nitride (TiN).Its formation method is for depositing sidewall and the dielectric layer 14 that one deck titanium covers dielectric layer 14 in this bottom metal layers 12, the opening 16 earlier.Then in the mode of nitridation reaction or deposit one deck titanium nitride in the mode of reactive sputtering and cover titanium layer.Then, with adhesion layer 18 on the chemical vapour deposition technique deposition plug material 20 covering dielectric layers 14 and the adhesion layer 18 in the opening 16.Wherein the material of plug material 20 for example is a tungsten, perhaps is aluminium.
Please refer to Fig. 1 C, eat-back plug material 20 with anisotropic dry ecthing method or chemical mechanical milling method, and remove plug material 20 fully to expose dielectric layer 14, make plug material 20 form connectors, yet the shortcoming of this prior art is can produce groove 22 on the surface of connector.
Please refer to Fig. 1 D, then, carry out follow-up manufacture craft, for example form layer of metal layer 24 and cover connector, to form the stacked structure of bottom metal layers 12/ connector/metal level 24.Owing to produce groove 22 on the connector, therefore cover on the metal level 24 of connector also and can fluted 26 to produce.When semiconductor structure needed the stacked structure of multilayer, then the groove phenomenon can be more and more serious.And when follow-up another layer of deposition dielectric layer covers this metal level 24 with groove, then can cause dielectric material to remain in the groove of metal level 24, and can't remove totally, cause electrical variation or qualification rate to reduce.
Therefore, main purpose of the present invention is to provide a kind of plug manufacture, to improve the groove phenomenon of connector, reduces to avoid electrical variation or qualification rate, and must not use the mechanical device of chemical mechanical milling method, can make the connector of no depressed phenomenon.
According to main purpose of the present invention, a kind of plug manufacture is provided, comprises the following steps: at first to provide a substrate, be formed with a dielectric layer in this substrate, wherein be formed with an opening on the dielectric layer, and this opening exposes in the substrate zone that is used for other structure of conducting.Forming an adhesion layer then covers and to be used for the sidewall and the dielectric layer of dielectric layer in the zone, opening of other structure of conducting in the opening.Then in opening, form the plug material layer, and fill up opening.Eat-back the plug material layer then, make the height of the plug material layer in the opening be less than about the height of dielectric layer, and use the etching method etching dielectric layer that dielectric layer comparison plug material layer is had high selectivity, make the height of dielectric layer approximate the plug material layer.
Feature of the present invention is to utilize the high etch selectivity method of dielectric layer to plug material, and dielectric layer is etched back to the height of connector, so can avoid the connector surface in the opening to produce the groove phenomenon with the layer on surface of metal that follow-up manufacture craft is deposited.And avoid the electrical variation of semiconductor element and qualification rate to reduce.And must not use the mechanical device of chemical mechanical milling method, can make the connector of no groove phenomenon.
The present invention is further detailed explanation below in conjunction with drawings and Examples, wherein:
Figure 1A~1D represents the manufacturing process profile of traditional connector; And
Fig. 2 A~2E represents the manufacturing process profile of a kind of connector of one embodiment of the present invention.
Please refer to Fig. 2 A, Fig. 2 A~2E represents the manufacturing process profile of a kind of connector of one embodiment of the present invention.One substrate 30 at first is provided, and this substrate 30 for example is formed with a bottom metal layers 31, and bottom metal layers 31 is to be provided with to be used for the zone of other structure of conducting, and its material for example can be aluminium alloy.Use the chemical vapour deposition technique that is same as prior art to form one dielectric layer 32 then and cover underlying structure, the material of dielectric layer 32 for example can be silicon dioxide.Yet in the present invention, the height of dielectric layer 32 (label 55) is approximately higher than default height (label 56).Then, thus with traditional photolithography techniques dielectric layer 32 compositions are exposed bottom metal layers 31 to form an opening 33.Being used for the zone of other structure of conducting in the present embodiment is example with bottom metal layers 31.Yet the invention is not restricted to this, opening 33 also can for example be used for exposing the source/drain region (not shown) in the substrate 30, and this source/drain region is to be provided with to be used for the zone of other structure of conducting.
Please refer to Fig. 2 B, then, form one deck adhesion layer 35 in opening 33, cover the sidewall and the dielectric layer 32 of dielectric layer 32 in bottom metal layers 31, the opening 33.The purpose of adhesion layer 35 is to increase the tackness of plug material in the follow-up manufacture craft, and as the usefulness of etch stop.Wherein, the material of adhesion layer for example is titanium/titanium nitride stacked structure.Its formation method covers sidewall and the dielectric layer 32 of dielectric layer 32 in this bottom metal layers 31, the opening 33 for first deposition one deck titanium, deposits one deck titanium nitride covering titanium layer in the mode of nitridation reaction or in the mode of reactive sputtering then.Then, for example with adhesion layer 35 on the chemical vapour deposition technique deposition plug material 37 covering dielectric layers 32 and the adhesion layer 35 in the opening 33.Wherein the material of plug material 37 for example is a tungsten, perhaps is aluminium.
Please refer to Fig. 2 C, eat-back plug material 37 to form connector with anisotropic dry ecthing method.In the present invention, the height of the plug material 37 after eat-backing approximates the preset height 56 of dielectric layer 32.In other words, the height of connector approximates the preset height 56 of dielectric layer 32.
Please refer to Fig. 2 D, use then the selection of dielectric layer 32 frequently the selection of plug material 37 than high etching method.If the material of dielectric layer 32 is a silicon dioxide, and plug material 37 is tungsten, then for example can use C4F8/CO/Ar/O2 gas as etching gas.Because the speed of these etchant gas dielectric layers 32 is very fast, therefore can makes the height of dielectric layer 32 approximate the height of connector, that is equal the preset height 56 of dielectric layer 32.
Please refer to Fig. 2 E, then carry out follow-up manufacture craft, for example cover connector with chemical vapour deposition technique deposition layer of metal layer 39, the material of metal level 39 for example is an aluminium alloy.
Feature of the present invention is to utilize the high etch selectivity method of dielectric layer 32 with respect to plug material 37, dielectric layer 32 is etched back to the height of connector, so can avoids the connector surface in the opening 33 to produce the groove phenomenons with metal level 39 surfaces that follow-up manufacture craft is deposited.And avoid the electrical variation of semiconductor element and qualification rate to reduce.And must not use the expensive machinery that carries out cmp, can make the connector of no groove phenomenon, to reduce manufacturing cost.
Though the present invention is illustrated in conjunction with a preferred embodiment, so it is not in order to limit the present invention, to those skilled in the art, under the situation that does not break away from the spirit and scope of the present invention, can make various improvement.

Claims (15)

1. a plug manufacture comprises the following steps:
One substrate is provided, is formed with a dielectric layer in this substrate, wherein be formed with an opening on this dielectric layer, and this opening exposes the zone that a setting is used for electrically conducting in the described substrate;
Form an adhesive layer, cover the sidewall of dielectric layer in zone that described suprabasil setting is used for electrically conducting and the described opening;
Form a plug material layer in opening, the plug material layer fills up described opening;
Eat-back the plug material layer, make the height of plug material layer in the opening be less than about dielectric layer, so as to forming connector; And
Etching dielectric layer makes the height of this dielectric layer be about as much as the height of connector.
2. plug manufacture as claimed in claim 1 wherein, be formed with a bottom metal layers in the described substrate, and described dielectric layer covers this bottom metal layers.
3. plug manufacture as claimed in claim 2, wherein, the zone that described setting is used for electrically conducting is a bottom metal layers.
4. plug manufacture as claimed in claim 1, wherein, the material of described plug material layer comprises tungsten.
5. plug manufacture as claimed in claim 1, wherein, the material of described plug material layer comprises aluminium.
6. plug manufacture as claimed in claim 1, wherein, the material of described dielectric layer is a silicon dioxide.
7. plug manufacture as claimed in claim 1, wherein, the material of described adhesion layer is titanium/titanium nitride.
8. plug manufacture as claimed in claim 1, wherein, the method that forms described adhesion layer comprises the following steps:
Deposition one titanium layer in described opening covers the sidewall and the described dielectric layer of dielectric layer described in zone that described setting is used for electrically conducting, the opening; And
Form the titanium nitride layer and cover described titanium layer surface.
9. plug manufacture as claimed in claim 8, wherein, the method that forms described titanium nitride layer comprises reactive sputtering.
10. the plug manufacture of stating as claim 8, wherein, the method that forms described titanium nitride layer comprises the nitridation reaction method.
11. plug manufacture as claimed in claim 1, wherein, the method that forms described plug material layer is a chemical vapour deposition technique.
12. plug manufacture as claimed in claim 1, wherein, the method for eat-backing described plug material layer is a dry ecthing method.
13. plug manufacture as claimed in claim 1, wherein, the method for the described dielectric layer of etching comprises that use compares the etching method that described plug material layer has high selectivity to described dielectric layer.
14. plug manufacture as claimed in claim 13, wherein, described etching method comprises with C 4F 8/ CO/Ar/O 2Gas is as etching gas.
15. plug manufacture as claimed in claim 1 wherein, after the step of the described dielectric layer of etching, comprises that also forming a metal level covers described connector.
CN 98115222 1998-06-24 1998-06-24 Plug manufacturing method Expired - Lifetime CN1115724C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 98115222 CN1115724C (en) 1998-06-24 1998-06-24 Plug manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 98115222 CN1115724C (en) 1998-06-24 1998-06-24 Plug manufacturing method

Publications (2)

Publication Number Publication Date
CN1239822A true CN1239822A (en) 1999-12-29
CN1115724C CN1115724C (en) 2003-07-23

Family

ID=5224465

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 98115222 Expired - Lifetime CN1115724C (en) 1998-06-24 1998-06-24 Plug manufacturing method

Country Status (1)

Country Link
CN (1) CN1115724C (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019138280A1 (en) * 2018-01-12 2019-07-18 International Business Machines Corporation Low-resistivity metallic interconnect structures with self-forming diffusion barrier layers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019138280A1 (en) * 2018-01-12 2019-07-18 International Business Machines Corporation Low-resistivity metallic interconnect structures with self-forming diffusion barrier layers

Also Published As

Publication number Publication date
CN1115724C (en) 2003-07-23

Similar Documents

Publication Publication Date Title
US4936950A (en) Method of forming a configuration of interconnections on a semiconductor device having a high integration density
US5227335A (en) Tungsten metallization
US5892286A (en) Semiconductor device and manufacturing method thereof
CN1250947A (en) Method for making dual-inlaid contact window
US5462893A (en) Method of making a semiconductor device with sidewall etch stopper and wide through-hole having multilayered wiring structure
US5281850A (en) Semiconductor device multilayer metal layer structure including conductive migration resistant layers
US4872050A (en) Interconnection structure in semiconductor device and manufacturing method of the same
JPH01503021A (en) Flattening method for forming through conductors in silicon wafers
US6027994A (en) Method to fabricate a dual metal-damascene structure in a substrate
US5320979A (en) Method of connecting wirings through connection hole
US5935876A (en) Via structure using a composite dielectric layer
US6952051B1 (en) Interlevel dielectric structure
EP0267730A2 (en) Tungsten metallization
US6762108B2 (en) Method of forming a metal-insulator-metal capacitor for dual damascene interconnect processing and the device so formed
US5770518A (en) Semiconductor device and method of manufacturing without undercutting conductive lines
CN1115724C (en) Plug manufacturing method
EP0507881A1 (en) Semiconductor interconnect structure utilizing a polyimide insulator
US6228757B1 (en) Process for forming metal interconnects with reduced or eliminated metal recess in vias
CN1239823A (en) Plug manufacturing method
US5930671A (en) CVD titanium silicide for contract hole plugs
US5973387A (en) Tapered isolated metal profile to reduce dielectric layer cracking
CN1229268A (en) Metal interlayer dielectric layer and making method thereof
CN1208819C (en) Process for preparing double metal inlaid structure
KR100414745B1 (en) Method for forming metal interconnection of semiconductor device
KR100652358B1 (en) A method of forming dual damascene

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20030723