CN1238983C - Multi-path extracting method and system in broadband CDMA searching - Google Patents
Multi-path extracting method and system in broadband CDMA searching Download PDFInfo
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- CN1238983C CN1238983C CN 02156293 CN02156293A CN1238983C CN 1238983 C CN1238983 C CN 1238983C CN 02156293 CN02156293 CN 02156293 CN 02156293 A CN02156293 A CN 02156293A CN 1238983 C CN1238983 C CN 1238983C
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Abstract
The present invention relates to a method and a system for multi-path extraction in WCDMA searching. The method for multi-path extraction has the following steps: A. according to odd/even sequence marks and control signals for a writing register of a single antenna, a multi-path referring sign register group unit (3) generates pick-up condition signals; B. according to the pick-up condition signals, an energy value comparing unit (2) selects whether to read data from an accumulation algorithm random-access memory unit (1) or not and compare the read-in data to obtain a maximum value and a corresponding address; C. the energy value comparing unit (2) outputs the maximum value, simultaneously generates control signals for the writing register and inputs the multi-path referring sign register group unit (3). For the next comparison, the maximum value which is outputted already is shielded. The system for multi-path extracting comprises the accumulation algorithm random-access memory unit (1), the energy value comparing unit (2) and the multi-path referring sign register group unit (3). The present invention has the advantages of simple data moving time sequence, little resource consumption and fast processing speed.
Description
Technical field
The present invention relates to electrical communication technology, relate in particular to the method and system that multipath extracts in a kind of Wideband Code Division Multiple Access (WCDMA) (WCDMA) search.
Background technology
In the WCDMA system, the source transmission signals is by reflections such as barrier such as building and mountains, and receiver will receive the copy signal of a plurality of different delay, and the RAKE folding by demodulation module obtains the peak signal gain to the signal plus of these different delay.And the delay character of these unlike signals is exactly top said multipath information, and 8 multipaths just are equivalent to the copy signal of 8 different delay.Therefore the extraction of multipath is the key technology of WCMDA system, does not have it just can not correctly merge received signal effectively, and the advantage of WCDMA is also just all gone.The data of the multipath in the general sub-district in certain sector are selected from the several values of the maximum of two antennas and do the RAKE merging, but when certain antenna in certain sector lost efficacy suddenly for various reasons, just need obtain all multipath information from the another one antenna.
In the existing technical scheme, usually adopt and earlier the content of accumulation algorithm RAM is moved among the multipath RAM, the value of reading multipath RAM then one by one compares, after running through one time, the value that finds a maximum is exactly first multipath, and note the position and the energy value of this multipath, then toward this address and about each 3 address write-back 0, shield this maximum and totally 7 values on every side; And then once read the value of RAM one by one and compare and find the 2nd multipath, and the like find 8 multipaths; The position and the energy value of last unified again these 8 multipaths of output realize that the multipath of 8 channels extracts.
As shown in Figure 1, accumulation algorithm RAM of per 2 channel sharings and multipath RAM, the sub-chip of search has 8 channels, therefore always have 4 accumulation algorithm RAM and 4 multipath RAM, and the energy value comparison module is 8 channel multiplexings.After the accumulation algorithm of every frame was finished, promptly the value stabilization among the accumulation algorithm RAM was just moved the value among the accumulation algorithm RAM among the multipath RAM of correspondence; The value of reading multipath RAM then one by one compares, after running through one time, the value that finds a maximum is exactly first multipath, and note the position and the energy value of this multipath, then toward this address and about each 3 address one 0 of totally 7 address ram unit write-back, and then once read the value of multipath RAM one by one and compare and find the 2nd multipath, because the position of the 1st multipath has been written into 0, so the maximum that this time finds is the 2nd multipath, and the like find 8 multipaths.The position and the energy value of last unified again these 8 multipaths of output.
Owing to use when history value when the requirement on the algorithm, the value of the accumulation algorithm RAM of present frame do accumulation algorithm will for back one frame, therefore can not be directly in the accumulation algorithm RAM write-back.So duplicating every frame accumulation algorithm RAM stable data with multipath RAM, the scheme of Fig. 1 carries out the multipath extraction once of every frame.
The shortcoming of this prior art scheme is as follows:
1) computation system RAM stable after, all data-moving just can be begun the extraction of multipath in the multipath RAM of correspondence, additionally increased the data-moving sequential, for the design of the interface logic of back has brought difficulty.
2) existing scheme is because multipath RAM of per 2 channel multiplexings, and this chip totally 40 channels, therefore just needing use 20 block RAMs, size is 768 * 52bit, so the bit number of the RAM that needs altogether is: 768*52*20=798720 (bits), expending of resource is very big.
Summary of the invention
The object of the present invention is to provide the method and system that multipath extracts in the WCDMA search that a kind of data-moving sequential is simple and resource cost is little.
The method that multipath extracts in the WCDMA search of the present invention, it is characterized in that: it adopts following steps:
A. multipath Warning Mark register group unit 3 is according to strange/even sequence sign of single antenna with write the register controlled signal and produce and extract status signal;
B. energy value comparing unit 2 selects whether read in data from accumulation algorithm random memory unit 1 according to extracting status signal, and the data of reading in are compared draws maximum and corresponding address thereof;
C. energy value comparing unit 2 output maximums produce new writing the register controlled signal and import multipath Warning Mark register group unit 3, the maximum that shielding has been exported when comparing next time simultaneously.
Each data in the accumulation algorithm random memory unit 1 are corresponding with the register in the multipath Warning Mark register group unit 3 respectively.Writing of exporting when multipath Warning Mark register group unit 3 obtains maximum according to the energy value comparing unit 2 extraction status signal that the register controlled signal produces makes this maximum in the accumulation algorithm random memory unit 1 not in the intake value comparing unit 2.
Multipath Warning Mark register group unit 3 is to produce the extraction status signal according to strange/even sequence sign of single antenna and the shift enable signal of writing in the register controlled signal in the steps A;
Described multipath Warning Mark register group unit 3 is consistent relevant extraction status signal by shift register group and corresponding combinational logic between 4 phase places of adjacent multi-path.
The system of the extraction multipath that the present invention adopts comprises accumulation algorithm stochastic storing unit 1, energy value comparing unit 2 and multipath Warning Mark register group unit 3; Multipath Warning Mark register group unit 3 produces extracts status signal, and send into energy value comparing unit 2, energy value comparing unit 2 reads in data according to extracting status signal from accumulation algorithm stochastic storing unit 1, and compare and draw maximum and corresponding address thereof, produce simultaneously and write the register controlled signal, and with its input multipath Warning Mark register group unit 3.
Described multipath Warning Mark register group unit 3 comprises that each phase value of reflection antenna extracts the selection circuit 33 of the multipath Warning Mark registers group 31 of state, the decoding logic circuit 32 that is used for obtaining a certain bit addresses of register, output sequence of parity sign, and the combinational logic circuit 34 that the extraction status signal is consistent between 4 phase places of adjacent multi-path; The register controlled signal of writing that energy value comparing unit 2 produces is imported combinational logic circuit 34 and decoding logic circuit 32; Decoding logic circuit 32 links to each other with registers group 31, is used for obtaining the address of a certain bit of register; Select circuit 33 to export strange/even sequence sign of single antenna to combinational logic circuit 34 according to the input of registers group 31,34 of combinational logic circuits are according to according to strange/even sequence sign of single antenna with write the register controlled signal and produce and extract status signal, and give energy value comparing unit 2.
Deposit in the described multipath Warning Mark registers group 31 with accumulation algorithm random memory unit 1 in data corresponding one by one.
The selection circuit 33 of described output sequence of parity sign comprises the 192:1 selector of two the even sequence signs of obtaining same single antenna and odd sequence sign and obtains the even sequence 2:1 selector of single antenna even sequence sign and single antenna odd sequence sign and the 2:1 selector of odd sequence.
Described combinational logic circuit 34 comprises shift register group and logical-arithmetic unit, single antenna even sequence sign and single antenna even sequence sign are imported corresponding shift register respectively, the output of shift register obtains control signal corresponding through logical-arithmetic unit again, and this control signal obtains extracting status signal with the register controlled signal through logical operation respectively again.
Described combinational logic circuit 34 comprises the first to the 99 shift register, wherein, single antenna even sequence sign is through the first shift register D1, the 3rd shift register D3, the 5th shift register D5, the 7th shift register D7, the 9th shift register D9, single antenna odd sequence sign is through the second shift register D2, the 4th shift register D4, the 6th shift register D6, the 8th shift register D8, the shift enable signal that shift register group is reflected in writing the register controlled signal triggers, the 3rd shift register D3, the 4th shift register D4, the 5th shift register D5, the 6th shift register D6, the output of the 7th shift register D7 and the 8th shift register D8 gets signal M through logic OR, this signal M respectively with the second shift register D2, the output of the 9th shift register D9 is non-through logic OR, obtain control signal corresponding, control signal obtains extracting status signal with shift enable signal through logical AND respectively.
The value of two phase places of odd even of the respectively corresponding stochastic storing unit 1 of described extraction status signal.
Described extraction status signal is transported to two triggers as triggering signal respectively, and described two triggers are positioned at the input of energy value comparing unit 2.
Beneficial effect of the present invention is: in the present invention, utilize 384 register Warning Marks of each antenna add simple logic make multipath extract if etc. the value stabilization of accumulation algorithm just can will begin in a minute and carry out relevant numeric ratio, and needn't resemble the data-moving that needs in the prior art scheme between the extra RAM, for sequential has greatly been saved in follow-up design, by this method, can simplify the sequential anxiety that data-moving brings between 2 block RAMs; And, can find by simple calculating, it is 768 * 52bit that the prior art scheme needs 20 multipath RAM sizes altogether, the bit number of the RAM that needs altogether is: 768*52*20=798720 (bits), be converted to 1: 10 ratio of register bit according to the RAM bit, be equivalent to need altogether to spend 79872 registers, and the register bit number that increases in the present invention is: (384*2+11) * 5=3895 (bits), resource cost has been saved more than 20 times, expending of resource is much smaller comparatively speaking, therefore, data-moving sequential of the present invention is simple and resource cost is little; Extract the value of two phase places of odd even of the respectively corresponding random memory (RAM) of status signal fngr_ind_l, fngr_ind_h unit, therefore whenever read a RAM and just can obtain two phase values and compare, increased processing speed.
Description of drawings
Fig. 1 is the structural representation of existing multipath extraction scheme;
Fig. 2 is the principle schematic of multipath extraction scheme of the present invention;
Fig. 3 is the block diagram of multipath extraction scheme of the present invention;
Fig. 4 is a multipath Warning Mark register group unit structural representation of the present invention;
Fig. 5 is the combinational logic circuit schematic diagram.
Embodiment
With reference to the accompanying drawings the present invention is described in further detail below:
As shown in Figure 2, the present invention includes accumulation algorithm stochastic storing unit 1, energy value comparing unit 2 and multipath Warning Mark register group unit 3.Multipath Warning Mark register group unit 3 produces extracts status signal fngr_ind_l, fngr_ind_h, and send into energy value comparing unit 2, energy value comparing unit 2 reads in data according to extracting status signal from accumulation algorithm stochastic storing unit 1, and compare and draw maximum and corresponding address thereof, produce simultaneously and write register controlled signal indication_write_address, and with its input multipath Warning Mark register group unit 3.According to writing register controlled signal indication_write_address, the data that all need extract are sought out in circulation to multipath Warning Mark register group unit 3 so repeatedly more then.
As shown in Figure 3, multipath Warning Mark register group unit 3 comprises multipath Warning Mark registers group 31, decoding logic circuit 32, select circuit 33 and combinational logic circuit 34,384*2 the value that registers group 31 correspondences are read from accumulation algorithm random memory unit 1, decoding logic circuit 32 is used for obtaining the address of a certain bit of register (corresponding to peaked position), select circuit 33 to export strange/even sequence sign of single antenna to combinational logic circuit 34 according to the input of registers group 31,34 of combinational logic circuits are according to according to strange/even sequence sign of single antenna with write a sky line index ant_flag who is reflected in the register controlled signal and produce and extract status signal, and give energy value comparing unit 2, energy value comparing unit 2 repeats to read in data according to extracting status signal again, register controlled signal indication_write_address is write in search and output maximum and generation, and input combinational logic circuit 34 and decoding circuit 32, so circulation is to seek out the data that all need extract.
In said process, it is to read in data from accumulation algorithm random memory unit 1 that the extraction status signal that energy value comparing unit 2 produces according to combinational logic circuit 34 is selected, still making and reading in data is 0 input (making that promptly the data of input are minimum value), compare then and draw maximum and corresponding address thereof and export maximum, produce simultaneously and write the register controlled signal and to import decoding logic circuit 32 and combinational logic circuit 34 in the multipath Warning Mark register group unit 3, the maximum that shielding has been exported when comparing next time, like this, energy value comparing unit 2 compares the respective phase value according to the corresponding extraction status signal that combinational logic circuit 34 produces, and obtains and export 8 position and energy informations with peaked multipath.
As shown in Figure 4,384*2 the value that registers group 31 correspondences are read from accumulation algorithm random memory unit 1, decoding logic circuit 32 is used for obtaining the address of a certain bit of register (corresponding to peaked position).Wherein registers group 31 comprises 384*2 register, 384 values that the accumulation algorithm random memory ram unit 1 of the 0th～383 corresponding the 0th antenna of register is read, 384 values that the accumulation algorithm random memory ram unit 1 of the 384th～767 corresponding the 1st antenna of register is read.The input of registers group 31 is constants of fixing: 0 or 1, and selecting which value is to be determined by the signal of decoding logic circuit 32.
The register controlled signal indication_write_address that writes that energy value comparing unit 2 produces comprises day a line index ant_flag and a shift enable signal, 34 of combinational logic circuits are according to strange/even sequence sign of single antenna and write a sky line index ant_flag who is reflected in the register controlled signal and produce and extract status signal, and give energy value comparing unit 2, like this, multipath Warning Mark register group unit 3 is consistent relevant extraction status signal by shift register group and corresponding combinational logic between 4 phase places of adjacent multi-path, the extraction status signal is consistent between 4 phase places of adjacent multi-path.
The selection circuit 33 of output sequence of parity sign comprises the 192:1 selector of two the even sequence signs of obtaining same single antenna and odd sequence sign and obtains the even sequence 2:1 selector of single antenna even sequence sign and single antenna odd sequence sign and the 2:1 selector of odd sequence.
Whether two antennas merge 8 multipaths of output still is that 8 multipaths of individual antenna output are decided by the sky line index, multipath Warning Mark registers group 31 outputs in the multipath Warning Mark register group unit 3 are through two-way 192:1 selector, obtain the even sequence sign and the odd sequence sign of same single antenna, promptly corresponding to the even sequence sign and the odd sequence sign of 0 antenna and 1 antenna.This sign passes through the 2:1 selector of even sequence and odd sequence more respectively, according to writing the sky line index ant_flag that is reflected among the register controlled signal indication_write_address, the selector of even sequence selector and odd sequence is input single antenna even sequence sign of the shift register group in logical circuit 34 and single antenna odd sequence sign respectively, the register flag that has shown same antenna among Fig. 4, another antenna is identical in an identical manner, produce even sequence sign and odd sequence marking signal, and insert the 2:1 selector.
As shown in Figure 5, combinational logic circuit 34 comprises 9 shift registers, be respectively: the first shift register D1, the second shift register D2, the 3rd shift register D3, the 4th shift register D4, the 5th shift register D5, the 6th shift register D6, the 7th shift register D7, the 8th shift register D8, the 9th shift register D9, wherein, single antenna even sequence sign is through the first shift register D1, the 3rd shift register D3, the 5th shift register D5, the 7th shift register D7, the 9th shift register D9, single antenna odd sequence sign is through the second shift register D2, the 4th shift register D4, the 6th shift register D6, the 8th shift register D8, the shift enable signal that shift register group is reflected in writing register controlled signal indication_write_address triggers, the 3rd shift register D3, the 4th shift register D4, the 5th shift register D5, the 6th shift register D6, the output of the 7th shift register D7 and the 8th shift register D8 gets signal M through logic OR, this signal M respectively with the second shift register D2, the output of the 9th shift register D9 is non-through logic OR, obtain control signal corresponding L, H, control signal L, H obtains extracting status signal fngr_ind_l with shift enable signal through logical AND respectively, fngr_ind_h, as shown in Figure 4 and Figure 5, by shift register group with write the shift enable signal that is reflected among the register controlled signal indication_write_address, the output of each shift register is through logic OR, the logical operation of logic OR not sum logical AND obtains extracting status signal fngr_ind_l, fngr_ind_h, like this, multipath Warning Mark register group unit 3 makes relevant extraction status signal fngr_ind_l by shift register group with corresponding combinational logic, fngr_ind_h is consistent between 4 phase places of adjacent multi-path, realizes the necessary width that keeps 4 phase places of phasetophase distance between the adjacent multi-path.
Multipath of the present invention extracts detailed process as shown in Figure 2, extraction status signal fngr_ind_l in 3 outputs of initial condition multipath Warning Mark register group unit, the fngr_ind_h signal is 1, so the data of reading from RAM can be sent into and compare, when whenever running through 384 values of one-accumulate algorithm RA M and relatively obtaining a maximum and during its relevant position, energy value comparing unit 2 output is write register controlled signal indication_write_address and is obtained the address of a certain bit in 384 registers (corresponding to peaked position) through decoding logic circuit 32, and to this than feature 1 ' b1; When carrying out the 2nd maximum extraction, when reading obtain for the 1st time peaked, because the value of that corresponding register is 1 ' b1, make fngr_ind_l or fngr_ind_h be output as 1 ' b0, thereby shielded the last RAM that obtains and exported peaked input, so the maximum that relatively obtains specifically is exactly the 2nd big value in fact, just the 2nd multipath; When carrying out the extraction of the 3rd multipath, because the corresponding fngr_ind_l and the fngr_ind_h of the 1st, the 2nd multipath are 1 ' b0, therefore the maximum of these two RAM outputs is with regard to conductively-closed, so what obtain specifically is the 3rd big value, i.e. and the 3rd multipath.Here can notice, as shown in Figure 4 and Figure 5, when the 1st multipath searched for, single antenna even sequence sign and single antenna odd sequence sign all are 0, therefore extract status signal fngr_ind_h and fngr_ind_l has become 1, make the sense data of accumulation algorithm random memory ram unit 1 just can enter energy value comparing unit 2 as shown in Figure 2 and compare and obtain the 1st multipath, put 1 at the corresponding multi-path location of corresponding single antenna multipath sign indicator register group then; When the 2nd multipath searched for, except the extraction status signal fngr_ind_l and the fngr_ind_h of each 3 phase place of the 1st multipath phase place and front and back is that other phase places all are 1 constantly 0, promptly allows to remove other accumulation algorithm random memory ram unit 1 sense datas 3 phase places in the 1st multipath phase place and front and back thereof and enter energy value comparing unit 2 and carry out the multipath extraction; The search way of residue multipath is by that analogy up to the position of finding 8 multipaths and energy.
In the present invention, extract the value of two phase places of odd even of the respectively corresponding random memory ram unit of status signal fngr_ind_l, fngr_ind_h, transport to two triggers as triggering signal respectively, as shown in Figure 2, two triggers are positioned at the input of energy value comparing unit 2.
Claims (14)
1. the method that multipath extracted during a WCDMA searched for, it is characterized in that: it adopts following steps:
A, multipath Warning Mark register group unit (3) are according to strange/even sequence sign of single antenna and write the register controlled signal and produce and extract status signal;
B, energy value comparing unit (2) are to read in data from accumulation algorithm random memory unit (1) according to extracting that status signal selects, and still making and reading in data is 0 input, and the data of reading in are compared draw maximum and corresponding address thereof;
C, energy value comparing unit (2) output maximum produce new writing the register controlled signal and import multipath Warning Mark register group unit (3), the maximum that shielding has been exported when comparing next time simultaneously.
2. the method that multipath extracts in the WCDMA search according to claim 1, it is characterized in that: each data in the accumulation algorithm random memory unit (1) are corresponding with the register in the multipath Warning Mark register group unit (3) respectively.
3. the method that multipath extracts in the WCDMA according to claim 1 search is characterized in that: multipath Warning Mark register group unit (3) makes this maximum in the accumulation algorithm random memory unit (1) not in the intake value comparing unit (2) according to writing of exporting when obtaining maximum of energy value comparing unit (2) the extraction status signal that the register controlled signal produces.
4. the method that multipath extracts in the WCDMA search according to claim 1 is characterized in that: multipath Warning Mark register group unit (3) is to extract status signal according to strange/even sequence sign of single antenna and the shift enable signal generation of writing in the register controlled signal in the steps A.
5. the method that multipath extracts in the Wideband Code Division Multiple Access (WCDMA) WCDMA search according to claim 1 is characterized in that: described multipath Warning Mark register group unit (3) is consistent relevant extraction status signal by shift LD and corresponding combinational logic computing between 4 phase places of adjacent multi-path.
6. the method that multipath extracts in the WCDMA search according to claim 3 is characterized in that: the initial value of the strange/even sequence sign of described single antenna is 0.
One kind realize the described multipath extracting method of claim 1 system, it is characterized in that: this system comprises accumulation algorithm stochastic storing unit (1), energy value comparing unit (2) and multipath Warning Mark register group unit (3); Multipath Warning Mark register group unit (3) produces extracts status signal, and send into energy value comparing unit (2), energy value comparing unit (2) reads in data according to extracting status signal from accumulation algorithm stochastic storing unit (1), and compare and draw maximum and corresponding address thereof, produce simultaneously and write the register controlled signal, and with its input multipath Warning Mark register group unit (3).
8. system according to claim 7, it is characterized in that: described multipath Warning Mark register group unit (3) comprises that each phase value of reflection antenna extracts the selection circuit (33) of the multipath Warning Mark registers group (31) of state, the decoding logic circuit (32) that is used for obtaining a certain bit addresses of register, output sequence of parity sign, and the combinational logic circuit (34) that the extraction status signal is consistent between 4 phase places of adjacent multi-path; The register controlled signal of writing that energy value comparing unit (2) produces is imported combinational logic circuit (34) and decoding logic circuit (32); Decoding logic circuit (32) links to each other with registers group (31), is used for obtaining the address of a certain bit of register; Select circuit (33) to export strange/even sequence sign of single antenna to combinational logic circuit (34) according to the input of registers group (31), combinational logic circuit (34) is then according to according to strange/even sequence sign of single antenna with write the register controlled signal and produce and extract status signal, and gives energy value comparing unit (2).
9. system according to claim 7 is characterized in that: register is corresponding one by one with the data in the accumulation algorithm random memory unit (1) in the described multipath Warning Mark registers group (31).
10. system according to claim 7 is characterized in that: the selection circuit (33) of described output sequence of parity sign comprises 192: 1 selectors of two the even sequence signs of obtaining same single antenna and odd sequence sign and obtains 2: 1 selectors of even sequence of single antenna even sequence sign and single antenna odd sequence sign and 2: 1 selectors of odd sequence.
11. system according to claim 7, it is characterized in that: described combinational logic circuit (34) comprises shift register group and logical-arithmetic unit, single antenna odd sequence sign and single antenna even sequence sign are imported corresponding shift register respectively, the output of shift register obtains control signal corresponding through logical-arithmetic unit again, and this control signal obtains extracting status signal with the register controlled signal through logical operation respectively again.
12. system according to claim 11, it is characterized in that: described combinational logic circuit (34) comprises the first to the 99 shift register, wherein, single antenna even sequence sign is through first shift register (D1), the 3rd shift register (D3), the 5th shift register (D5), the 7th shift register (D7), the 9th shift register (D9), single antenna odd sequence sign is through second shift register (D2), the 4th shift register (D4), the 6th shift register (D6), the 8th shift register (D8), the shift enable signal that shift register group is reflected in writing the register controlled signal triggers, the 3rd shift register (D3), the 4th shift register (D4), the 5th shift register (D5), the 6th shift register (D6), the output of the 7th shift register (D7) and the 8th shift register (D8) gets signal M through logic OR, this signal M respectively with second shift register (D2), the output of the 9th shift register (D9) is non-through logic OR, obtain control signal corresponding, control signal obtains extracting status signal with shift enable signal through logical AND respectively.
13. system according to claim 7 is characterized in that: the value of two phase places of odd even of the respectively corresponding random memory unit of described extraction status signal (1).
14. the system that multipath extracts in the Wideband Code Division Multiple Access (WCDMA) WCDMA search according to claim 7, it is characterized in that: described extraction status signal is transported to two triggers as triggering signal respectively, and described two triggers are positioned at the input of energy value comparing unit (2).
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