CN1235430A

CN1235430A - Grid coder with first-in first-out queue and ring combination

Info

Publication number: CN1235430A
Application number: CN 99100300
Authority: CN
Inventors: 王匡; 谢磊
Original assignee: Hi-Tech Research & Development Center State Science & Technology Commission
Current assignee: Hi-Tech Research & Development Center State Science & Technology Commission
Priority date: 1999-01-29
Filing date: 1999-01-29
Publication date: 1999-11-17

Abstract

A lattice encoder with FIFO queue and annular interleaving is composed of input buffer, encode controller, encode-state queue cells and single encoder. Said encode-state queue cells have N stages, each stage corresponding to one encoder, that is, including the encode state of one encoder and one byte of encording data. In the cell, N encode state data are sequentially arranged in FIFO queque. One encoder is used for sequential encoding and N : 1 interleaving is realized, so the circuit size is reduced by 60%.

Description

The trellis encoder of fifo queue and ring combination

The present invention relates to a kind of trellis encoder, the trellis encoder of particularly a kind of fifo queue and ring combination.

In the high definition TV terrestrial broadcast system, owing to exist simulated television with the problem of broadcasting, its channel coding-decoder needs particular design, specifically be exactly in the trellis encoder (TCM) of transmitting terminal, to embed interweaving of N:1, add the digital comb filter of (1+D) and the lattice shape decoding of N:1 band deinterleaving at receiving terminal, N wherein is decided by the frequency spectrum configuration.

The trellis encoder that traditional embedding interweaves is shown in Fig. 1, and it comprises the MUX MUX of an input ₁, the MUX MUX of an output ₂With N trellis encoder.In Fig. 1, MUX ₁With byte (8bits) is unit, and data flow is distributed to N trellis encoder successively; Each encoder resolves into 4 symbols (every symbol 2bits) to 1 byte data of input, and carries out the channel symbol that convolutional encoding generates 3bits by symbol; MUX ₂With 4 times to MUX ₁Speed switch, encoder selected when at every turn switching generates a channel symbol, MUX ₂Therefrom read this channel symbol, enter N byte data of N encoder like this, through MUX ₂The just whole code interleavings of 4 circulations finish interleaved order such as Fig. 2 of this N byte.At MUX ₂Circulate when switching MUX ₁Also switching, only its speed is MUX ₂1/4, it whenever switches to the byte data one by one that a new encoder newly sends into input and delivers in this encoder, uses in order to the next round coding; Work as MUX ₂4 loop ends after (each encoder is all finished the coding of 1 byte), MUX ₁Just in time finish once circulation, a new N byte data be put into respectively in N the encoder, whole coding circuit begin again a next group N byte data coding and interweave.

Each trellis encoder (TCM) is shown in Fig. 3.Wherein the capacity of coded buffer is 3 bytes, and it is responsible for handle by MUX ₁The new data temporary cache of sending here once; Symbol segmentation resolves into 4 symbols to 1 byte (8bit), and each 2bit (is respectively high-order X ₁, low level X ₀), send in the symbol encoder successively; Symbol encoder carries out 2/3 convolutional encoding (physical circuit of encoder is shown in empty frame among Fig. 3), and it is the symbol (X of 2bit ₁, X ₀) be encoded into the channel symbol (Z of 3bit ₂, Z ₁, Z ₀); Control logic is responsible for producing control signal and is made the each several part collaborative work.Carry out N:1 like this and interweave and need N duplicate coding circuit, so circuit scale can be bigger.

For addressing the above problem, the purpose of this invention is to provide the trellis encoder of a kind of fifo queue and ring combination.

For this purpose, the trellis encoder of a kind of fifo queue of the present invention and ring combination comprises: input buffer is used for and will imports the new data to be encoded that data arrangement becomes buffer queue; Coding controller is connected to input buffer output, is used for control and reads in N level encoding state data from the buffering formation, and be used to control the process of coding; Encode state queue cell, the N level encoding state data that are used for coding controller is read in are arranged in wherein from left to right by fifo queue, and when encoding, N level formation right-to-left moves lattice at every turn, the status data of formation head is sent into encoder, and new status data moves the row afterbody; Single encoded device, under the control of coding controller, N encoding state data that are used for encode state queue cell is arranged are encoded successively, interweave thereby reach N:1.This encode state queue cell has the N level, and encoder of every grade of correspondence comprises that promptly the encoding state of an encoder and 1 byte are just in coded data.Single encoded device and coding controller also comprise: MUX MUX, symbol segmentation device, symbol encoder and control logic device.

The invention has the advantages that, adopt the trellis encoder of fifo queue and ring-type can make the circuit scale of whole encoder taper to 60% of conventional way, greatly reduced the scale of hardware, realize about 6000 of the circuit (adopting the FPGA of ALTERA company) of this structure with FPGA (Field Programmable Gate Array), if adopt the conventional way of Fig. 1 approximately to need 11000, as seen this structure has significant effect for the reduction circuit scale.

Above-mentioned purpose of the present invention and other advantage will become more clear in reference to the thin description of saying of each accompanying drawing.Wherein

Fig. 1 represents the block diagram of the trellis encoder that traditional embedding interweaves;

The code interleaving order of the trellis encoder of Fig. 2 presentation graphs 1;

The block diagram of the single trellis encoder of Fig. 3 presentation graphs 1;

Fig. 4 represents the block diagram of the trellis encoder of fifo queue of the present invention and ring combination;

Fig. 5 represents the functional-block diagram of single encoded device of the present invention and coding controller.

Now in conjunction with the accompanying drawings work of the present invention is illustrated.Fig. 4 represents the block diagram of the trellis encoder of fifo queue of the present invention and ring combination.In Fig. 4, the trellis encoder of fifo queue of the present invention and ring combination comprises: input buffer, single encoded device and coding controller and a coding team state queue unit.Wherein there is the N level in encode state queue cell, encoder of every grade of correspondence, and it comprises the encoding state of an encoder and 1 byte just in coded data.Because N encoder is isomorphism fully, unique difference is exactly the internal state and the coded data of each encoder between them, therefore can characterize this N encoder fully with these states and data; Each encoder is to work successively to finish in turn to interweave among Fig. 1 simultaneously, we just can ceaselessly carry out coding work with an encoder so, and the state and the data of taking out different encoders from state queue when encoding are sent to coding at every turn, promptly present this N encoding state and data successively, thereby reach the effect that N:1 interweaves; At the same time the new status data in coding back is fed to the formation afterbody in order to use next time.The flow process of data and state as shown in phantom in Figure 4.

After coded data used up in the encode state queue cell, coding controller can read in data from the input buffering formation, as the dotted line among Fig. 4.The main effect of this buffer queue is to replace coded data buffer among Fig. 3, is brought together being dispersed in N the buffer in the encoder, makes data volume minimum in the encoding state formation.

The contrast by Fig. 1 and Fig. 4 now further specifies the course of work of the present invention.In Fig. 1 by MUX ₂The encoder of choosing is a current encoder, is the encoder that current time is being worked, and then other encoder is idle.Face then is in first encoding state data of " formation of N level encoding state " head (leftmost side) in Fig. 4.The How It Works of circuit is to pass through MUX among Fig. 1 ₂Motion choose each encoder work (promptly from encoder TCM#1 to TCM#N) successively, promptly current encoder is by MUX ₂Determine; And being flowing of data, the inventive method of Fig. 4 replaces the MUX among Fig. 1 ₂Rotation, its key is to represent encoder with data and status data, current encoder is those encoding state data of the head of N level encoding state formation, lattice are moved in the N level formation of each coding back from right to left, the status data in current encoder back moves to the position of current encoder, simultaneously the new state of original current encoder is delivered to rear of queue (rightmost side).If the encoder of the N among Fig. 1 is corresponded among Fig. 4, among Fig. 4 " formation of N level encoding state " unit in from left to right be arranged in order state and the data of encoder TCM#1, the MUX in Fig. 1 to TCM#N ₂When encoder TCM#1, in the corresponding diagram 4 is the head (leftmost side) of the status data of TCM#1 in formation, is promptly from left to right arranging TCM#1 in the formation in turn, TCM#2, TCM#3, the status data of TCM#N, " symbol encoder " among Fig. 1 only encoded to the TCM#1 of the formation leftmost side; MUX in Fig. 1 ₂When turning to encoder TCM#2, it is TCM#2 that the status data of corresponding formation is arranged, TCM#3, TCM#4,, TCM#N, TCM#1 ', be that one-level has been moved in formation from right to left, simultaneously original T CM#1 be put into formation afterbody (rightmost side) through the new status data TCM#1 ' that " symbol encoder " operation back generates; MUX in Fig. 1 ₂When encoder TCM#2 switched to TCM#N successively, corresponding status data in Fig. 4 formation went out successively to move, and finally TCM#N is moved to the head of formation, status data in the formation is arranged as TCM#N, TCM#1 ', TCM#2 ', TCM#3 ' ..., TCM#N-1 '; When the TCM#N end-of-encode, and move to rear of queue, entire circuit begins new one again and takes turns coding.After all data all were encoded in 4 whole formations that circulate, the coded data in the formation was all encoded and has been finished, and data new under the control of " coding controller " are admitted to formation, began new one coding of taking turns N byte data, so moved in circles.

The functional-block diagram of " single encoded device and coding controller " among Fig. 4 as shown in Figure 5.

As can see from Figure 5, be divided into two branches from the input of formation: the 1st, " encoder data " represents data to be encoded; The 2nd, " coder state ".This two encoder in the phenogram 1 fully.When just starting working, because the data in the encode state queue cell all are empty, so the control that MUX MUX is subjected to " control logic " circuit is arrived " symbol segmentation device " to top one tunnel the new data delivery from buffer; If the data of encode state queue cell are not empty, MUX MUX is giving " symbol segmentation device " from the data of formation head (current encoder).The symbol segmentation device takes out 2bit (X from 1 byte data of newly sending into (8bit) simultaneously ₁, X ₀), the circuit code that these 2bit data are lived by the institute of the dotted line among Fig. 5 frame becomes the coding result (Z of 3bit ₂..Z ₀), and the state in the above-mentioned coding circuit is from formation (" D of branch below promptly importing on the left of figure ₀..D ₂Coder state "), the coding back generates new state D ＇ ₀..D ＇ ₂, it and behind the coding of " symbol segmentation device " output remaining uncoded data Data ' [7..0] lump together the afterbody of sending into " formation of N level encoding state ", in order to next round coding.

Claims

1, the trellis encoder of a kind of fifo queue and ring combination is characterized in that, it comprises:

Input buffer is used for and will imports the new data to be encoded that data arrangement becomes the input buffering formation;

Coding controller is connected with input buffer output, is used for control and reads in N level encoding state data from the buffering formation, and be used to control the process of coding;

Encode state queue cell, be used for the formation of N level encoding state data that coding controller is read in by first in first out, be arranged in order from left to right therein, during each the coding, N level formation right-to-left moves lattice, the status data of formation head is sent into encoder, and new status data moves on to afterbody;

Single encoded device, under coding controller control, N encoding state data that are used for encode state queue cell is arranged are encoded successively, interweave thereby reach N:1.

2, the trellis encoder of a kind of fifo queue according to claim 1 and ring combination, it is characterized in that, this encode state queue cell has the N level, and encoder of every grade of correspondence comprises that promptly the encoding state of an encoder and 1 byte are just in coded data.