CN1233025C

CN1233025C - Local forming process of metal silicide layer

Info

Publication number: CN1233025C
Application number: CN 01132675
Authority: CN
Inventors: 赖二琨; 陈昕辉; 陈盈佐; 黄守伟; 黄宇萍
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2001-09-06
Filing date: 2001-09-06
Publication date: 2005-12-21
Anticipated expiration: 2021-09-06
Also published as: CN1404116A

Abstract

The present invention mainly provides a method for partially forming a silicification metal layer on an integrated circuit. The method can avoid forming silicification metal on the surface of an element requiring a high resistance value, so the efficiency of the element can not be reduced. The method can also avoid the phenomenon of current leakage caused by the formation of silicification metal between memories on the same character line. The method of the present invention mainly forms a covering sleeve on the element of which the surface doesn't need forming silicification metal, and then a metal layer is deposited. A heating step is carried out for forming silicification metal. As a result, the goal can be achieved.

Description

The local method that forms metal silicide layer

Invention field

The present invention is the method for relevant one local formation metal silicide layer, particularly relevant one avoids in the method that needs to form metal silicide on the element surface of high resistance and avoid producing between memory the part formation metal silicide layer of omitting electric current.

Background of invention

Be generally and reduce resistance value to promote integrated circuit efficient, regular meeting deposits a metal silicide layer on circuit and element surface, such as titanizing silicon.Should not reduce the zone of resistance value then must avoid forming metal silicide on its surface; such as interval region between memory on the same character line and the element that needs high resistance; such as load transistor (load transistor) and static discharge (electrostaticdischarge, ESD) protective device.Traditional formation method is as shown in Figure 1: at first, provide a silicon base material 100, on this ground 100, have two zones at least: one is array region 101, and another is neighboring area 102.In array region 101, a dielectric layer 105 is arranged, such as silica-silicon-nitride and silicon oxide (ONO) layer, on ground 100.By a memory array of being made up of a plurality of memories 110,110 of adjacent two memories on the wherein same character line have one first interval region 106 on this dielectric layer 105.And in neighboring area 102, have a plurality of transistors 120 at least, and one second interval region 107 is arranged between the adjacent two-transistor 120.After the step that forms metal silicide, can on the top portions of gates surface of the top portions of gates surface of memory 110, transistor 120 and silicon base material 100 surfaces, form metal silicide (150,160,170).

Yet in the conventional method, when the step of the sidewall 130 that forms memory 110, tend to because control is difficult for, to such an extent as to and cause over etching to expose to be positioned at first interval region 206 silicon base material partly, shown in Fig. 2 A.To such an extent as to when forming the step of metal silicide, also form on the surface of the silicon base material 100 of a metal silicide layer 240 in first interval region 206, shown in Fig. 2 B.So will cause omitting electric current, and influence the effect of memory.

In addition,,, also can form metal silicide in its surface simultaneously, so will throw into question such as load transistor or electrostatic protection device if when having other elements to exist on the ground.We can find that these undesirable problems are not cause because conventional method does not have the selectivity that forms metal silicide.

Summary of the invention

A purpose of the present invention provides a method with the local metal silicide layer that forms on integrated circuit.

Another object of the present invention provides a method and causes the phenomenon of omitting electric current to avoid forming metal silicide between memory on the same character line.

A further object of the present invention provides a method to avoid needing to form metal silicide on the element surface of high resistance.

According to above purpose, method of the present invention mainly comprises the following step; At first, one silicon base material is provided, can divide into an array (array) zone and a periphery (periphery) zone on this silicon base material, wherein in this array region, comprise one first dielectric layer on ground and a plurality of the first transistor, such as memory array, be positioned on this first dielectric layer.Between adjacent two transistors one first interval region is arranged in these a plurality of the first transistors.And in this neighboring area, comprise a plurality of transistor secondses and a plurality of semiconductor element is positioned on the ground, wherein these a plurality of semiconductor elements are the device with high electrical resistance value, and between adjacent two transistor secondses one second interval region are arranged in these a plurality of transistor secondses.Then, conformally deposit one deck second dielectric layer to cover the surface of this ground, this array region, a plurality of the first transistor, this neighboring area, these a plurality of transistor secondses and these a plurality of semiconductor elements.Afterwards, deposit a photoresist layer again to cover this second dielectric layer.Then, remove the photoresist layer on the zone that does not need to form metal silicide, such as first interval region and this a plurality of semiconductor elements.Be a mask with this remaining photoresist layer again, carry out another etching step removing partly second dielectric layer, then remaining second dielectric layer only is present in this first interval region and on the surface of these a plurality of semiconductor elements.Afterwards, remove this remaining photoresist layer.Then, deposit a metal level with on the surface that covers this total.Carry out a heating steps to form metal silicide.At last, remove this metal level and this remaining second dielectric layer.

Description of drawings

Fig. 1 is conventional method local schematic cross-section that forms metal silicide layer on an integrated circuit;

Fig. 2 A to Fig. 2 B is that conventional method produces one of over etching problem embodiment in the schematic cross-section in each stage;

Fig. 3 A to Fig. 3 J forms one of metal silicide layer embodiment in the schematic cross-section in each stage according to the method for inventing part on an integrated circuit.

Embodiment

The method that the invention provides forms metal silicide with regional area on integrated circuit, and it comprises the following step: at first, as shown in Figure 3A, provide a ground 100, have two zones on it at least, one is that array region 101, is neighboring area 102.On this array region 101, deposit a dielectric layer, such as silica-silicon-nitride and silicon oxide (ONO) layer 105, and one memory array list on this ONO layer 105, wherein, between adjacent two memories 110 one first interval region 306 is arranged on the same character line.And on neighboring area 102, comprising two class components at least: a class is to reduce its sheet resistance person, such as a plurality of transistors 120; Another kind of is to reduce its sheet resistance person, such as be a load transistor 302 and an electrostatic discharge (ESD) protection (ESD) device 304 in present embodiment.Wherein, one second interval region 307 is arranged between the adjacent two transistor 120.In the present embodiment, be separated by between the grid of two adjacent memories 110 or two adjacent transistor 120 and be about 0.36 micron, and the width of first interval region 306 and second interval region 307 is about 0.34 micron.

Afterwards, conformally deposit one dielectric layer 310, such as silicon oxide layer, with cover whole array region 101, with 102 surfaces, neighboring area on, shown in Fig. 3 B.The thickness of this dielectric layer 310 is about 350 to 500 dusts.Afterwards, depositing a photoresist layer 320 covers on this dielectric layer 310, shown in Fig. 3 C.Carry out design transfer and remove part photoresist layer 320, only keep the photoresist layer 320 that is positioned at first interval region 306, load transistor 302 and electrostatic discharge protective equipment 304 tops, shown in Fig. 3 D.Then, be a mask with remaining photoresist layer 320, carry out an etching step to remove most of dielectric layer 310, only keep the part dielectric layer 310 that is covered by photoresist layer 320, shown in Fig. 3 E.Then, remove photoresist layer 320, shown in Fig. 3 F.

Then, deposit a metal level 330, such as Titanium, to cover on the whole integrated circuit, shown in Fig. 3 G.Carry out a heating steps again so that the reaction of metal and polysilicon forms metal silicide (332,334,336), lay respectively on memory 110 gate surface, on transistor 120 gate surface and on ground 100 surfaces, shown in Fig. 3 H.And first interval region 306,304 of load transistor 302 and electrostatic discharge protective equipments are because there is dielectric layer 310 to exist so can not form metal silicide layer on it.

Afterwards, remove metal level 330, shown in Fig. 3 I.Remove dielectric layer 310 at last, to expose the surface of load transistor 302 and electrostatic discharge protective equipment 304, shown in Fig. 3 J.The dielectric layer 310 that is positioned at first interval region 306 can keep and can also remove, and this does not influence the scope of the invention.So, just, finish the local method that forms metal silicide layer of the present invention.

Subsidiary one carries, and the ONO layer 105 on array region 101 also can be other dielectric layer.Then more can comprise one deck silicon oxide layer with as grid oxic horizon at

silicon base material

100 and 120 in transistor.

The above is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should comprise within the scope of the claims.

Claims

1. local method that forms metal silicide layer, this method comprises the following step at least:

One silicon base material is provided, on this silicon base material, can divides into an an array zone and a neighboring area at least;

Form on the silicon base material of one first dielectric layer in this array region, and a plurality of the first transistor wherein has one first interval region between adjacent two the first transistors in these a plurality of the first transistors on this first dielectric layer;

Form on a plurality of transistor secondses this ground in this neighboring area, wherein between adjacent two transistor secondses one second interval region is arranged in these a plurality of transistor secondses;

Form on a plurality of semiconductor elements this ground in this neighboring area, wherein this a plurality of semiconductor elements top will not form metal silicide;

Conformally deposit one second dielectric layer to cover this ground, this array region, this neighboring area, these a plurality of the first transistors, these a plurality of transistor secondses and a plurality of semiconductor element;

Deposit a photoresist layer to cover this second dielectric layer;

Carry out design transfer and remove the part photoresist layer, keep this photoresist layer that is positioned at this first interval region and this a plurality of semiconductor elements top;

With this photoresist layer is a mask, carries out an etching step to remove this second dielectric layer of part, and remaining this second dielectric layer is positioned at the top of this first interval region and these a plurality of semiconductor elements;

Remove this photoresist layer;

Deposit a metal level to cover this silicon base material, this array region, this neighboring area, these a plurality of the first transistors, these a plurality of transistor secondses and this second dielectric layer;

Carry out a heating steps to form metal silicide;

Remove this metal level, and

Remove this second dielectric layer.

2. method according to claim 1, wherein said first dielectric layer are monoxide-nitride-oxide (ONO) layer.

3. method according to claim 1 more comprises a grid oxic horizon between the grid and this ground of these a plurality of transistor secondses.

4. method according to claim 1, wherein said second dielectric layer is an one silica layer.

5. method according to claim 1, wherein said second dielectric layer is a silicon nitride layer.

6. method according to claim 1, wherein said a plurality of semiconductor elements are load transistor.

7. method according to claim 1, wherein said a plurality of semiconductor elements are electrostatic protection device.

8. method according to claim 1, wherein said a plurality of semiconductor elements comprise a load transistor and an electrostatic protection device at least.

9. method according to claim 1, wherein said metal level are layer of titanium metal.