CN1232331A - Method for error correction and error detection of data transmission between optical large scale memory and host computer - Google Patents
Method for error correction and error detection of data transmission between optical large scale memory and host computer Download PDFInfo
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Abstract
An error check and correction (ECC) method for the data transmission between optical mass storage and host features that it can simplify the processing procedure for data transmission and increase data transmission speed in order to meet the requirement from high-density optical mass storage.
Description
The present invention relates to a kind of error correction and error-detecting method that transfers data to host computer from high-capacity storage, this method can be improved the error correction and the error detection efficient of high-capacity storage (as compact disc read-only memory), and then the data transmission bauds between the data/address bus of enhancement and PC.
The optics high-capacity storage, compact disc read-only memory (CD-ROM) as the well-known, be widely used in the storage and circulation of program and data, it is too big particularly to work as this program or data, in the time of can't sending the user of PC or other personal computer systems easily to.With respect to integrated circuit memory and magnetic storage device, the data access speed of CD-ROM and similar high-capacity storage is slower.Therefore, the personal computer system is limited for the using time of optics high-capacity storage traditionally.For instance, when installation and setting program, routine data can transfer to the magnetic storage device of computer system earlier from CD-ROM.After this routine data is stored in magnetic storage device, will can to former CD-ROM not carry out the action of access when using this program future again.
Some integration procedure audio frequency, image etc. do not need the data of permanent storage in hard disk.These data must be read by CD-ROM term of execution of program one by one.The program of this class and other need use the application program of high-capacity storage, and CD-ROM reading of data and the rate request that transfers data to computer system are raise day by day.In the past, transmitted the main bottleneck of data from the CD-ROM memory block, be from the speed of CD-ROM dish reading of data.In order to overcome this bottleneck, the rotating speed of CD-ROM has increased manyfold by its rated rotational frequency now, and the speed that data are read from the CD-ROM dish obtains the increase of identical multiple.Under this trend, be responsible for to carry out the CD-ROM data format, error correction and error detection, reach the controller of data transfer operations, may form the bottleneck of restricting data transfer rate.Especially in conjunction with the novel high-capacity storage of high density data memory technology, popularize just gradually.The data read rates of these high density high-capacity storages, higher than CD-ROM, therefore need have the more controller of high throughput.
From the data that CD-ROM read, before being sent to the data/address bus of computer system, must be via a series of processing procedure.These processes are the general technology of commonly using in this field haply, comprise decoding (Descrambling), reorganization (Reorganization), buffer-stored (Buffer storage), error correction (Elror correction) and the error detection technology such as (Error detection) of data.Transfer data to the conventional method of host computer data/address bus from the optics high-capacity storage, can be from people's such as Suzuki United States Patent (USP) the 4th, 680, people's such as No. 764, Markvoort United States Patent (USP) the 4th, 802, find in the related data that No. the 5th, 581,715, people's such as No. 152 and Verinsky United States Patent (USP).
The controller hardware calcspar of the known optics high-capacity storage that Fig. 1 is given an example for people's patent such as Verinsky, it can be used for controlling the transfer of data from the CD-ROM dish to IDE (Integrated deviceelectronics, the integrated equipment electronic circuit) bus of a host computer.Data read is the difference via the CD-ROM panel surface institute laser light reflected in rotating, and detects modulation (Modulation) record of panel surface.Change this with a digital quantizer then and be modulated to digital signal data stream, as input to a sector data signal 10 of CD-ROM controller.The data that the CD-ROM dish is stored are normally irregular, present and synchronizing signal or the identical style of other control signals for preventing these data, and storage is before CD-ROM, and (scramble) can be encoded earlier.Therefore,, need the decoding device 12 of data, with the data-signal of dish is decoded (Descrambling) from the data that reverberation solved of dish.Data repacking device 14 these decoded serial bit streams of reorganization (Serial bitstream) are the byte form, and are stored in the storage device 16.
General data is that unit is stored in the CD-ROM dish with the sector (sector) of about 2KB size, and this kind sector also is data employed units when carrying out error correction and error detection and transferring to host computer.After the 2KB sector data from the CD-ROM dish is stored to storage device 16, error correction and error detection computing will begin to carry out at this sector data.About employed correcting data error of this high-capacity storage of CD-ROM and error detection computing, formulated by the ISO/IEC-10149 standard of standard CD-ROM data memory format.
The traditional algorithm that is used for error coded, error correction and the error detection of high-capacity storages such as CD-ROM is disclosed in people's such as people's such as Odaka No. the 4th, 413,340, United States Patent (USP) and Suzuki No. the 4th, 680,764, the United States Patent (USP).The data integrity of desiring to guarantee to be sent to by CD-ROM host computer is errorless, can reach by three groups of error correction datas that added for user's data in a sector data.And these three groups of error correction datas are 172 P-parity check codes (P-parity) byte, 104 Q-parity check code (Q-parity) bytes and 4 error detection codes (Error detection code, EDC) bytes.
The data combination of P-parity check code and Q-parity check code can provide the form coding of double cross mistake (Double interleaved) the Reed-Solomon sign indicating number to the CD-ROM sector data.Each batch sector data can be divided into two data planes (plane), and one is that (one is most significant byte (Most significant byte, MSB) plane to least significant byte for Least significant byte, LSB) plane.Arbitrary datum plane all has a staggered error correction matrix (Error correction matrix), as shown in Figure 2.Matrix in Fig. 2 has 43 P-vectors (P-vector), and each P-vector, is formed and is defined in GF (2 in conjunction with 2 P-parity check code bytes by 24 byte user data
8) (26,24) Reed-Solomon sign indicating number of finite field (finite field).And 26 Q-vectors (Q-vector) are by extending cornerwise 43 the byte user data of this array and 2 Q-parity check code bytes, and that is formed is defined in GF (2
8) (45,43) Reed-Solomon sign indicating number of finite field.
Through after all error correction computings, can then carry out error detection traditionally to this sector data, judging whether still wrong the existence, or there is not the mistake that produces because of the error correction computing.The computing of error detection is by a cyclic redundancy code CRC (Cyclic Redundancy Code, CRC) checker is implemented, this cyclic redundancy code (be about 2000 bytes * 8) is by as a string binary digit, and removes it with a check multinomial (Checkpolynomial).According to the ISO/IEC-10149 standard, this check multinomial is P (x)=(x
16+ x
15+ x
2+ 1) (x1
6+ x
2+ x+1).Each sector data that is stored in the CD-ROM dish has all added 4 error detection codes (EDC) byte, eliminates so that the sector data after additional this error detection code can be verified multinomial.Therefore, can be verified multinomial as if the binary digit that sector data constituted that spreads out of from the CD-ROM dish and eliminate, just can suppose in these data does not have mistake.If in the error detection division non-zero residue is arranged, then represent wrong existence, therefore further error correction is necessary.Usually the method that solves is to read this sector data again from the CD-ROM dish, imposes the computing of error correction and error detection flow process more again.
Traditional error detection division hardware construction is quite simple, comprises that having feedback connects the shift register (Shift registers) of (Feedbackconnections) and have partial sum gate (Exclusive OR) array ().The error detection computing of being implemented by Error Detection Unit 26, the sector datas that must will be stored in the storage device 16 are all read, and each position is moved (shift) in regular turn and gone into CRC device 22 (hereinafter referred to as CRC check device 22) with it.Imported CRC check device 22 all when all positions, get final product the residue of error detection division.After error correction and error detection computing, if the residue that produces is zero, this sector data can transfer in the computer system data/address bus via storage device 16, checked sector data signal output 24 as shown in Figure 1.
In data were transferred to process the computer data bus from the CD-ROM storage device, error correction and error detection computing were quite time-consuming parts.Yet because to the requirement of computer data correctness, it is necessary that the data that the optics high-capacity storage is read impose the error correction computing.In addition, implementing the error correction computing is in order to meet the standard of CD-ROM and other optical memory systems.
In view of this, main purpose of the present invention just provides a kind of in order to from optics high-capacity storage reading of data, and imposes the method for an error correction and an error detection computing, and it can reach the higher data output speed.
In order to achieve the above object, the invention provides a kind of between between an optical disc mass storage system (MSS) and a host computer method of transfer of data, this method comprises at least from this optical disc mass storage system (MSS) and obtains a serial data, and changes this serial data and become a kind of form that is stored in digital storage.Then, in serial data to a storage device after this conversion of storage, the serial data after this conversion also is supplied to an Error Detection Unit, whether to detect in this serial data wrong the existence.At this, the error detection computing of at least a portion is to carry out when being stored in storage device with this serial data.If the error detection computing concludes do not have mistake to be present in this serial data, then transmit this serial data to this host computer.Otherwise when if this error detection computing is determined to a rare mistake and is present in this serial data, then at this serial data of transmission to this host computer, can impose an error correction computing to this serial data earlier.
The present invention also provide a kind of between between an optical disc mass storage system (MSS) and a host computer method of transfer of data, this method comprises at least from this optical disc mass storage system (MSS) and obtains a serial data, and stores this serial data to one buffer storage.In buffer storage, this serial data also is supplied to one " first Error Detection Unit " at this serial data of storage.This first Error Detection Unit can be carried out " the first error detection computing " to this serial data, with decision wrong being present in this serial data whether, and produces one " the first error detection value ", is used for representing the error condition of this serial data.Then this serial data is subjected to an error correction computing.When this error correction computing is carried out, in this serial data, find out a mistake and correct it earlier, carry out one " the second error detection computing " more simultaneously, to determine whether still wrong being present in this serial data.When this second error detection computing pointed out that the mistake of not correcting is stayed this serial data, then this second error detection computing produced an inerrancy signal; And, the serial data after this corrigendum is sent to this host computer by this inerrancy signal that this second error detection computing produced.
Above-mentioned method, wherein this first error detection computing comprises this serial data divided by an error checking multinomial, and wherein this first error detection value for by the residue of this serial data divided by this error checking multinomial gained.In the above-mentioned method, the step of carrying out this second error detection computing also comprises this first error detection value imposed a corrigendum computing, correcting this first error detection value, and confirms whether the error detection value after this amount just is non-zero.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
The simple declaration of accompanying drawing:
Fig. 1 is the Data Transmission Control Unit block hardware diagram of the known optics high-capacity storage of explanation;
Fig. 2 is the standard error correction matrix that the Reed-Solomon sign indicating number that sector data had of explanation CD-ROM dish is formed;
Fig. 3 is the hardware configuration of the optics high-capacity storage of the preferred embodiment according to the present invention;
Fig. 4 is pattern 1 (mode-1) the sector data structure chart that is stored in the CD-ROM dish;
Fig. 5 is cyclic redundancy code testing circuit (the Cyclic Redundancy checkcircuit) calcspar that can use in Fig. 6;
Fig. 6 is the CD-ROM controller circuit block diagram of the preferred embodiment according to the present invention;
Fig. 7 is the error detection processing unit circuit block diagram of the preferred embodiment according to the present invention;
Fig. 8 can be used in a counter of the present invention to implement illustration; And
Fig. 9 is another embodiment circuit block diagram of error detection processing unit of the present invention.
A preferred embodiment of the present invention, the data for read, also will be sent to host computer from optics high-capacity storage (as CD-ROM) provide error correction and error detection computing at a high speed.And embodiments of the invention can be according to generally finishing for the industrial standard of optically read high-capacity storage, for example according to the industrial standard of CD-ROM storage device.According to one object of the present invention, data are read from a high-capacity storage, and the serial data stream of these data can offer a storage device and an error detection circuit concurrently.
--may to be a traditional cyclic redundancy code (CRC) calibration equipment--can carry out the error detection computing to the data that read by high-capacity storage to this error detection circuit, and under preferable situation, this computing can be carried out when data flow just is stored to storage device.For instance, this error detection computing comprises with error checking multinomial (Error check polynomial) except that serial data stream, to determine the residue of this division arithmetic.If this data flow is not found any mistake after testing, then be stored in the sector data that this serial data is constituted in the storage device, can be transferred to the data/address bus of host computer, and must not carry out the error correction computing this batch data.
Compared to the employed error correction of high-capacity storage (as CD-ROM) traditionally, error detection, and and the data transfer mode of host computer data/address bus, system of the present invention only when be sure oing that data are wrong, just can carry out the error correction computing.Owing to reduced unnecessary data error correction computing, the speed of transfer of data can be accelerated.
Above-mentioned advantage of the present invention, for the system from the high-capacity storage reading of data of low error rate (error rate) to host computer, its efficiency of transmission can obtain very big lifting.Yet real system may have the higher data error rate, particularly when new technology is used on the optical memory system.The high density compact disc storage system (Optical disk storage system) that is developing at present, for example (Digital Versatile Disc, DVD) system promptly has higher ratio of error to the digital multi-purpose disk.In addition, WORM (Write once/read many, WORM) and its information of read-write optical storage modulation (Information modulation) quality if the CD-ROM system is ungood, so may have higher error rate.
Therefore, another characteristics of the present invention for it can be applicable in the actual system, promptly contain when wrong when the data that read from high-capacity storage.According to embodiments of the invention, the serial bit stream of reading from a high-capacity storage is provided this to a storage device and an error detection circuit simultaneously.Be integrated into byte and when being stored in a buffer storage, error detection circuit is also to being carried out an error detection computing by this serial data stream at this serial data stream.This error detection computing can this serial data stream of error checking deconv, and obtains a residue.This residue via initial wrong division arithmetic (Error division operation) gained will be stored, and the way of abandoning this residue with traditional EDC system is different.In case a collection of sector data is deposited in the storage device, can impose the error correction computing to this sector data that is stored in the storage device.Can use as long-pending type (Reed-Solomon product-like) sign indicating number of traditional Reed-Solomon at this and to carry out.
When error correction circuit is found wrong byte,, can draw the address and the error code type (Error pattern) thereof at this error byte place via finding the solution wrong equation (Error equations).This error byte is capped and writes back storage device then, the byte that makes a mistake with replacement.Simultaneously,, aforesaid EDC division arithmetic residue is done one revise computing, and get EDC residue newly corresponding to position in the serial data stream and error code type thereof according to this error byte.In brief, whenever error correction circuit to the action of correcting errors in printing of the sector data in the storage device, promptly revise the EDC residue simultaneously.Whether be zero, if non-vanishing, then this EDC residue can be saved if then testing this EDC residue, and continue to carry out the error correction computing.This kind function mode and traditional error correction computing framework are inequality fully--and traditional error correcting system is promptly given up its error code type and errors present information after having corrected the error byte in the storage device.
The error correction computing will continue to proceed to the EDC residue and be modified into till zero.At this moment, can suppose that institute has wrongly been corrected, so be stored in the data/address bus that sector data in the storage device can be transferred to host computer.If all Reed-Solomon sign indicating numbers have been handled in the error correction computing, and the EDC residue is still non-vanishing, then can repeat error correction procedure to the data of having corrected in the storage device.Another kind of way is to read this sectors of data again from high-capacity storage, and the duplicate of laying equal stress on is invented described error detection (EDC) and error correction (ECC) program.
According to the embodiment that is carried before, the present invention also can provide a higher rate of data signalling, because it does not need as traditional framework, data is read from storage device one by one deliver to error detection circuit again.In addition, when the EDC residue becomes zero,, can save some unnecessary error correction computings, and then improve data transmission efficiency by stopping the error correction computing and transmitting this data.For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborate.
Fig. 3 is the hardware configuration of the optics high-capacity storage of the preferred embodiment according to the present invention.This data transmission system operates under the control of microcontroller 40.Microcontroller 40 can be used the microcontroller as 8051 formulas, and operates according to the control programs of being stored in the read-only memory 42.CD 50 is the form stored informations with the concavo-convex or optical property variation of its reflecting surface.Reading the method for signal from dish, is to utilize optical read head 52 to send a laser to CD 50 surfaces and collect its reverberation.After the detector that is positioned at optical read head 52 receives this reverberation, produce an analog electronic signal that contains the information of CD 50 surface storage.Analogue signal processor 54 is from optical read/write head 52 received signals, and obtains servo (servo) control information from the Spindle Motor (spindle motor) of rotating disc 50, provides signal to digital signal processor 56 with appropriate format then.Then this digital signal processor 56 provides a digital output signal to a CD-ROM controller 58 or a digital/analog converter 60.Digital/analog converter 60 will convert analog signal to from the digital signal of digital signal processor 56, be sent to audio socket (audiojack) 62 then, become the music output of CD-ROM device.Digital/analog converter 60 and audio socket 62 are formed a subsystem (subsystem), and music CD is play, and must be through the digital data transfer Circuits System of CD-ROM controller.By CD-ROM controller 58, numerical data can be transferred to the data/address bus of computer system, as an IDE bus 64.Before data were delivered to IDE bus 64, CD-ROM controller 58 was carried out combination and the error correction and the error detection computing of data by buffer storage 66.
The data structure of general CD-ROM sector (sector) is defined in international standard ISO/IEC-1 049: among " Information Technology-Data Interchange on Read-Only 120mm OpticalData Disks (exchanges data on the read-only smooth data disks of information technology-120mm) ".This standard code the data store organisation of most of CD-ROM dish, but this structure allows some variations.This standard code 3 kinds of different sector patterns (mode), so be stored in the data of the CD 50 of Fig. 3, can be following 3 kinds of patterns exist: pattern 0 (mode0), pattern 1 (mode1), pattern 2 (mode2).Therefore, the circuit of Fig. 3 must take suitable mode to handle its data according to the mode initialization in the CD-ROM data.About the difference of different mode CD-ROM data, detailed description is arranged in standard.Following discussion will be with the CD-ROM data instance of pattern 1.
Fig. 4 is the pattern 1 sector data structure chart of CD-ROM dish.This sector data can be subdivided into several fields, wherein comprises synchronous (Synchronization pattern) field of one 12 bytes, in order to indicating the starting point of a sector data, and initial some sector data treatment circuits.One 4 byte header (Header) field has write down the absolute address` (Absolute address) of this sector data, with minute, second, and frame (frame, 1 second=75 frames) form; And a pattern (Mode) byte, to indicate the pattern of this sector data.The data sector of pattern 1 contains 2048 user's data (User data) byte, be positioned at the 16th to 2068 byte of pattern 1 sector data, and then the error detection code (EDC) of 4 bytes, centre (Intermediate) field of 8 bytes, the P-parity check code of 172 bytes and the Q-parity check code field of 104 bytes are arranged thereafter.Amount to 2352 bytes.
Above-mentioned P-parity check code and Q-parity check code are formed error correcting code (ECC).To the sector data of arbitrary CD-ROM, its error detection code (EDC) and error correcting code (ECC) form the error protection framework of two complementations.This EDC field is the part of one 32 cyclic redundancy codes (CRC), and it is used in combination with protected data field, can detect in the sector data whether wrong existence.ECC field of being made up of the Q-parity check code of the P-parity check code of 172 bytes and 104 bytes and the data field of being protected thereof are formed the long-pending type sign indicating number (RSPC) of Reed-Solomon, in order to detect and the corrigendum sector data in the mistake that occurs.
Therefore, error detection code EDC exists to have judged whether any mistake in order to sector data is done a verification, and error correcting code ECC then is used for the more mistake of correction data.As shown in Figure 1, the wrong existence of data that traditional way hypothesis is read from the CD-ROM dish so before carrying out the error detection computing, can carry out all possible error correction computing earlier, is just handled all RSPC one time earlier.Then, use the sector data of EDC verification after the error correction calculation process whether still wrong again.The required control circuit of the unconditional error correcting system of this kind is comparatively simple, because of its execution that must not assess specific error correction computing whether.On the other hand, transfer of data can be slack-off, because no matter whether sector data contains wrongly, or whether its mistake finished by corrigendum, and all error correction computings all must be carried out.And it should be noted that the industrial standard requirement imposes error correction and two kinds of computings of error detection to the data of CD-ROM disk storage, but structure as shown in Figure 1 and non-standard institute are necessary.
For the data sector of CD-ROM pattern 1, its EDC code word (EDC codeword) has comprised the 0th to 2067 byte in the sector data.And the sector data of CD-ROM XA pattern 2 forms 1 (mode2form1), its EDC code word then comprises the 16th to 2075 byte in the sector data.In EDC calculates, the least significant bit (LSB) of preferential calculated data byte.Therefore, if be B with a sectors of data type flags
i, i=0 to 2351, and each of this byte is B
I, j, j=7 (MSB) is to 0 (LSB), and then the EDC code word of CD-ROM pattern 1 sector data is 16544 a binary digit.
B
0,0B
0,1B
0,2B
0,3B
0,4B
0,5B
0,6B
0,7B
1,0B
1,1...B
2066,6B
2066,7B
2067,1
B
2067,2B
2067,3B
2067,4B
2067,5B
2067,6B
2067,7Or be expressed as with polynomial method
B
0,0x
16543+B
0,1x
16542+B
0,2x
16541+B
0,3x
16540+...+B
2067,4x
3+
B
2067,5x
2+ B
2067,6X+B
2067,7To the sector data of a CD-ROM XA pattern 2 forms 1, its EDC code word is 16480 a binary digit
B
16,0B
16,1B
16,2B
16,3B
16,4B
16,5B
16,6B
16,7B
17,0...B
2074,7B
2075,0B
2075,1
B
2075,2B
2075,3B
2075,4B
2075,5B
2075,6B
2075,7Or be shown with polynomial table
B
16,0x
16479+B
16,1x
16478+B
16,2x
16477+B
16,3x
16476+...+B
2075,4x
3+
B
2075,5x
2+B
2075,6x+B
2075,7
For the sector data of pattern 1, field such as the EDC code word has contained synchronously, head, user's data and EDC, so it can be used to detect in this this field whether any mistake is arranged.
According to ISO/IEC-10149, be stored in the EDC code word in CD-ROM pattern 1 sector, its coded system is to select four suitable EDC bytes, after making it and fields such as synchronous, head, user's data combining, can be eliminated by following check multinomial (check polynomial):
P(x)=(x
16+x
15+x
2+1)×(x
16+x
2+x+1) (1)
Or P (x)=x
32+ x
31+ x
16+ x
15+ x
4+ x
3+ x+1
EDC code word in the sector data that will read from CD-ROM divided by above-mentioned check multinomial, can get a residue.Whether by this residue of verification is zero, can verify whether contain in this EDC code word wrong.Easy speech, for pattern 1 sector data of being read by CD-ROM, whether this error detection rule can verification contains wrong in the fields such as it is synchronous, head, user's data and EDC--just in the field that the EDC code word is contained--.
The required division of above-mentioned error detection rule can pass through a cyclic code decoder (Cyclic code decoder) and carry out, as shown in Figure 5.Usually sort circuit, can by the D flip-flop of some series connection, and some partial sum gates that link to each other with these triggers (exclusive-OR gate) form, and this kind circuit is by generally being known.
Each position of EDC code word must be imported cyclic decoder one by one in regular turn, after its final position input cyclic decoder, and the output of this each trigger of cyclic decoder--referred to herein as CRC register (CRC register), be the residue of EDC division.If all positions of CRC register are all zero, then Shu Ru EDC code word should be correct, because it meets EDC error detection rule.Otherwise if the value of CRC register is non-vanishing, then can conclude must be wrong in the data field that the EDC code word contained.But this error detection rule can not point out in the EDC code word which position is wrong on earth.
By error correcting code (ECC), can correct the sector data of reading from CD-ROM.Error correcting code is the long-pending type sign indicating number (RSPC) of Reed-Solomon as used herein, No. the 4th, 680,764, people's such as No. the 4th, 413,340, people's such as the visible Odaka of its operational mode United States Patent (USP) and Suzuki United States Patent (USP).In the sector data of CD-ROM pattern 1, the 12nd to 2075 byte is with the RSPC sign indicating number matrix of P-Parity and Q-Parity field formation double cross mistake (interleaved), as shown in Figure 2.The row of this matrix (column) is called the P-vector, for being defined in finite field GF (2
8) (26,24) Reed-Solomon code word.And the diagonal of this matrix is called the Q-vector, for being defined in finite field GF (2
8) (45,43) Reed-Solomon code word.
A sector has comprised 86 P-vectors and 52 Q-vectors, these vectors are divided equally again in two planes, one is less effective byte (LSB) plane, constitute by the sector data byte that is positioned at even address, another is big effective byte (MSB) plane, is made of the sector data byte that is positioned at odd address.
P-vector and Q-vector are the base units of implementing the error correction computing.Each P-vector comprises 26 bytes, comprises 2 P parity bytes (P-Parity bytes).According to the content of P-vector, can derive one group of mistake equation (error equations).If it is wrong in the P-vector certain byte being arranged, this wrong position (Error location) (that byte that promptly should vector is wrong) and error code type (Errorpattern) (promptly those are wrong in this wrong byte) can be found the solution this mistake equation and get according to the rule of Reed-Solomon sign indicating number.If the P-vector does not have wrong the existence, then its wrong equation has one the error code type is null and separates, otherwise, can solve one group of errors present and error code type by its wrong equation, in order to more to be sitting at the data byte at errors present place.
The length of Q-vector is 45 bytes, wherein comprises 2 Q-parity check code bytes (Q-paritybytes).To the error correction computing that the Q-vector is implemented, similar with the P-vector.Whether therefore, each Q-vector also can be derived one group of mistake equation, wrong with deciding in the Q-vector.If have, then solve the position and the pattern of its error byte, and correct this mistake according to this.
Desire to guarantee that the data that read from the CD-ROM dish are correct, it is not enough depending merely on error correcting code.Because error correction logic (ECC logic is hereinafter referred to as the ECC logic) circuit error correction is limited in one's ability, its necessity is arranged so use the EDC sign indicating number to do further error detection.For each P-vector or Q-vector, its wrong equation of deriving only can solve the information of a mistake.Therefore, if a P-vector or Q-vector contain two (containing) above mistakes, then the ECC logic just can't correctly solve errors present and error code type.Consequently the errors present that solved by wrong equation of ECC logic is invalid (illegal), or ECC logic mistake is actually correct byte with one and carries out " corrigendum ", and causes another mistake.So,, can not guarantee that it is correct via the data that the ECC logical process is crossed.
The design of some ECC logical circuit can be corrected two mistakes in a P-vector or the Q-vector by means of the errors present information that digital signal processor provided.But this ECC logical circuit is comparatively complicated, and also can not handle the above situation of three mistakes.
In sum, use the EDC sign indicating number in the CD-ROM sector, can detect whether mistake of its data; And use the ECC sign indicating number, then can find and the mistake in the correction data more.Error detection logic (EDC logic is hereinafter referred to as the EDC logic) circuit that utilization EDC sign indicating number carries out error detection is a principle of utilizing cyclic redundancy check (CRC) code (CyclicRedundancy Code).The ECC logic that utilization ECC sign indicating number carries out error correction then is a principle of utilizing the Reed-Solomon sign indicating number.Since the principle difference that both use, the use of can arranging in pairs or groups mutually, with the part that compensates its defect.In traditional CD-ROM reading system, being applied in after the ECC logic of EDC logic is to determine not having mistake in the sector data after error correction.
Describe in the 6th figure according to CD-ROM controller functional block diagram of the present invention, this figure also is described in more detail CD-ROM controller among Fig. 3 58 and storage device 66.Learn that by Fig. 6 CD-ROM controller is from digital signal processor 56 (as among Fig. 3) input one serial bit stream 70.Decoding device (Descrambler) 72 receives serial bit stream 70, and after finding synchronous (Synchronizationpattern) field, begin this serial bit stream decode (descramble), to obtain and then the CD-ROM sector data field behind synchronous field, i.e. head, user's data, EDC and ECC etc.These decoded data (descrambled data) are transferred into data repacking device (Data organizer) 74 simultaneously, reach cyclic redundancy code generation device (CRC generator) 78.Wherein, data repacking device 74 converts decoded serial data to the byte form, and these data bytes are stored to appropriate location in the storage device 76, in order to follow-up error correction computing, and finally is transferred to host computer.
Usually the capacity of storage device 76 is quite big, can store a plurality of sector datas in order to promote and host computer between efficient when continuing to transmit.This storage device 76 can be dynamic random access memory (DRAM), or static RAM (SRAM) faster.One of advantage of the present invention, promptly it still allows use than low speed and cheap buffer storage, so can reduce its cost under the situation that does not reduce System Operation usefulness under working at high speed.
From the serial bit stream of data deciphering device 72 outputs,, also import cyclic redundancy code generation device 78 simultaneously except importing data repacking device 74 to store data to storage device.The preferred embodiment of cyclic redundancy code generation device 78 is one 32 cyclic redundancy detectors (Cyclic redundancy checker), as shown in Figure 5, and with the error checking polynomial division of provider's formula (1).
When the data decoded (descramble) of input and when being stored to memory, cyclic redundancy code generation device 78 is carried out a preliminary error detection computing to the serial bit stream of its input simultaneously, just with the bit stream of its input divided by the error checking multinomial.After the EDC code word in the serial bit stream is imported cyclic redundancy code generation device 78 fully, promptly get one 32 initial residue (initial remainder).With CRC
0Expression.Because the data of input cyclic redundancy code generation device 78 are still crossed without the ECC logical process, so the CRC0 value can be considered the error detection result of the initial data that reads from CD-ROM, in order to set in the error detection processing unit (Error Detection Processor) 82 initial value of residue register R.
If error detection processing unit 82 detects residue CRC
0Be zero, then do not have mistake in the sector data of error detection processing unit 82 deducibilitys input.In this case, be stored in this sector data in the storage device 76, can be output data/address bus immediately to host computer.Traditional error-detecting method, must wait until that error correction procedure is finished after, again the sector data in the storage device is read and imported a CRC device (as Fig. 1) one by one, so its spended time is longer, and more to the reading times of memory.
Error correction logic device 80 in Fig. 6 according to the RSPC mode sector data of storage device stored is imposed the error correction computing, and the error correction method that this error correction computing can be traditional carries out.After data repacking device 74 was stored into storage device with a complete sector data, the error correction computing promptly began to carry out.Error correction logic device 80 is obtained the content of each P-vector and Q-vector one by one according to the coding rule of RSPC from storage device 76, whether to determine in each vector wrong the existence.If have, then separate its wrong equation to obtain the errors present and the error code type of wrong byte.Errors present is 12 a binary digit, to point out which byte in this sector data is wrong.And the error code type is one 8 a binary digit, must corrigendum with which position in the byte that points out faults.In the embodiment of Fig. 6, errors present is exactly the address (address) of error byte in the sector in fact.
The error code type is with the errors present use of arranging in pairs or groups.For instance, if the error code type is 01001010
2And errors present is 1234
10, the byte 1234 of this sector data so
10Be wrong.In addition, if the 1234th
10The initial data of byte is 11010101
2, so the 1234th
10The value of byte will be corrected as 11010101
2 01001010
2=10011111
2( represents nonequivalence operation), that is the right value of this byte equals its original value error code type.When error correction logic device 80 is carried out the error correction computing to each P-vector and Q-vector, calculate its errors present and error code type earlier, calculate the right value (right value=improper value error code type) of this error byte again, then correct data byte is write back storage device 76, to replace original error byte.
The difference of embodiments of the invention and traditional error correction system, be that error byte is corrected after, its errors present and error code type can not be dropped, and can be temporarily stored in error correction logic device 80 or the error detection processing unit 82, are used for to initial error detection residue CRC
0Or original error detection residue R
iUpgrade computing.The renewal operation method of this error detection residue will describe in detail below.
During sector data in error correction logic device 80 corrigendum storage devices 76, error detection processing unit 82 can its error detection residue of renewal R
i, check then whether its value is zero.If the R after upgrading
iValue becomes zero, and then the institute in this sector data of error detection processing unit 82 deducibilitys is wrong has corrected all, so this sector data can be transferred to IDE or other host computer bus from storage device 76.When the CD-ROM controller of Fig. 6 operates under this pattern, in case error detection residue R
iBe zero, error correction logic device 80 will stop action because in this sector inerrancy need corrigendum.
Whether error detection processing unit 82 of the present invention does not need read storage device 76, decide the sector data that is stored in the storage device 76 wrong.On the contrary, errors present and error code type information that error detection processing unit 82 utilizes the error correction computing to be produced are with at first or CRC residue value (CRC subsequently
0Or R
i) impose error detection residue renewal computing of the present invention, and produce a new CRC residue value (R
I+1).
For each byte of being corrected by error correction device 80, error correction device 80 will transmit errors present and error code type signal is given error detection processing unit 82.Error detection processing unit 82 upgrades former CRC residue according to this, and just the EDC code word is divided by the residue of check multinomial (check polynomial), and a new residue R
iSo, error detection processing unit 82 just must not impose division to obtain the CRC residue to tediously long EDC code word as traditional way.82 couples of residue R of error detection processing unit
iAfter doing a renewal, its new value R
I+1To be examined.If R
I+1Non-vanishing, then still wrongly in this sector data wait to correct, so the error correction computing will be proceeded.Otherwise, if R
I+1Be zero, the error detection processing unit can assert that mistakes all in this sector is all corrected, and makes error correction procedure stop, and transfers data to host computer.After this new sector data that reads from the CD-ROM dish also will be handled in this way.If after all P-vectors in a sector and Q-vector are processed all, the CRC remainder R of gained is still non-vanishing, then need repeat error correction procedure, in the hope of correcting remaining mistake in the sector, perhaps also can in dish, read this sector data again, implement above-mentioned fault processing step then again.
The function mode of error detection processing unit 82 of the present invention, available one 15 bit word are that example is illustrated.Suppose that c (x) is a collection of 15 data, its content is
C (x)=x
14+ x
11+ x
8+ x
6+ x
5+ x
4+ x
3+ x, or
C (x)=(100100101111010), the present is desired with a check multinomial
P (x)=x
4Whether+x+1 verification c (x) correct, thus with c (x) divided by p (x), must discuss formula
Q (x)=(10001011001), and residue
R (x)=(0001), as follows:
Last example is represented a traditional error-detecting method, promptly utilizes error checking multinomial p (x), can confirm the correctness of code word c (x).As the cyclic redundancy code generation device 78 among Fig. 6, promptly utilize the EDC code word of this principle examination input whether correct.But, its length of EDC code word of cyclic redundancy code generation device 78 is more than 16000, and its error checking multinomial lists in the equation (1), so its division process is also tediously long than this example.Also can find out that from last example traditional CRC division is quite simple, because of its computing is all the arithmetic of modulus 2 (modulo2), so can be carried out by the circuit that partial sum gate (XOR) and shift register are formed.
Residue in the above-mentioned example is non-vanishing, and this EDC computing just finds that code word c (x) contains wrong.Suppose that the error bit of finding out code word c (x) is x with certain error correction computing this moment
10And x
5, that is the error code type of c (x) is e (x)=(000010000100000), then the code word c ' after the corrigendum (x)=c (x) e (x)=(1001101010011010).
(x) as follows with traditional error-detecting method verification c ' once more:
The residue of this division is zero, so the code word c ' after the decidable corrigendum is correct (x).
Above-mentioned traditional error correction and error-detecting routine (doing CRC check with division again after error correction) have the advantage of hardware simplicity, but in the sector data that be applied to CD-ROM dish, and during EDC code word more than 16000, its processing procedure will be quite consuming time.
In preferred embodiment of the present invention, utilize error code type e (x) to revise original error detection residue, whether the revised residue of verification is zero again.Shown in following calculating, the code word c ' after error correction (x), it is divided by the polynomial residue of error checking, can be removed r (x)+e (x) (residue before the error correction with error code type with) and is got by p (x), its result is similar to conventional method:
Error detection processing unit of the present invention is a mode of taking progressive (incremental), revises and check the error detection residue.Wrong in sector data is found in the error correction computing and when being corrected just, the error detection processing unit can use this wrong pattern and positional information, adds original error detection residue, again divided by the error checking multinomial a new residue.This new residue can reflect that this mistake is by the error check results after correcting.If new residue (being revised residue) is zero,, represent that promptly the EDC code word is correct according to the rule of error detection.
Therefore, if one contain wrongly from the sector data that the CD-ROM dish is obtained, then its initial residue that is produced by the error detection division (initial remainder) should be non-vanishing, and this initial residue can be by the traditional cyclic redundancy decoding circuit generation as Fig. 5.After this wrong corrigendum the in this sector can be revised error detection residue value according to its error message (error information).It is till zero that this program will continue to residue because with regard on the mathematics, initial residue with after wrong pattern merges, its result should be divided exactly by the error checking multinomial.Error correction of the present invention and error-detecting method, though follow and the identical mathematical principle of traditional C RC method, the method for its enforcement is gradual, with traditional Error Detection Unit very big difference is arranged.
In the aforesaid example, error code type (error pattern) is the position that the code word domestic demand is replaced.Yet in error detection processing unit of the present invention, the error code type is 8 a byte, and need to cooperate one 12 errors present, with this error code type corresponding to the ad-hoc location in the sector data of byte surplus one 2000.With regard to mathematical operation, the error detection processing unit 82 in Fig. 6 embodiment, can following calculating formula go to calculate new error detection residue:
R
i+1=R
i{(e·x
8λ)modulo?P(x)}， (2)
R shows error detection result (residue) herein, and e represents the error code type, and λ is a numerical value of deriving from errors present L, and P (x) is the error checking multinomial of aforesaid equation (1).In fact, this numerical value R
i (ex
8 λ) may be very long, make the computing of equation (2) quite time-consuming.Yet this computing is still compared the traditional CRC of whole EDC code word execution and is calculated as soon.On the other hand, above-mentioned error detection computing meeting is carried out simultaneously with the error correction computing, thus the time of implementation of whole error correction and error detection computing, can be than the traditional circuit much shorter in Fig. 1.
Fig. 7 can carry out an embodiment of the error detection processing unit 82 of equation (2) computing in the CD-ROM controller of Fig. 6.This error detection processing unit 82 comprises an error detection processing unit control unit 100, and it is a finite state machine (finite state machine), in order to the correction computing action of control error detection residue.Errors present transducer 102, or the ELC of Fig. 7 (Error location converter, errors present transducer), in order to convert errors present L to one 12 λ, used for the correction computing of R value.Corrected Calculation circuit (Correction calculation circuit) 104 calculates (ex
8 λ) value of mod P (x), and export its result, and residue R register 106 storage error detection residues, its initial value is CRC
0, be revised residue value Ri subsequently.
Error code type e (8) and errors present 1 be by error correction device 80, separates the wrong equation of a RSPC vector and get.Error correction device 80 is exported an error code type e and errors present L respectively to error detection processing unit 82 via circuit 108 and circuit 110.Simultaneously, this error correction device 80 to start the computing of error detection processing unit 82, also just makes error detection processing unit control unit 100 by circuit 112 output one starting impulses (Start pulse), begins to carry out error detection residue correction operation program.
Another input of error detection processing unit 82 is the initial value CRC that the cyclic redundancy code generation device 78 among Fig. 6 is calculated
0Before error correction computing starting or simultaneously, the CRC that produces by cyclic redundancy code generation device 78
0Can be stored in the residue R register.If this initial error detection residue CRC
0When being zero,, can not need carry out further error correction computing according to preferred embodiment of the present invention.Otherwise if the initial EDC computing of cyclic redundancy code generation device 78, point out in the sector data that reads, to have one or more when wrong, this CRC
0Non-vanishing and its value will be existed in the residue R register, start error detection processing unit 82 up to error correction device 80.That is when starting impulse occurred, errors present transducer 102 converted errors present L to 12 figure place λ, to supply with corrected Calculation device 104.Simultaneously, error code type e also imports corrected Calculation device 104.Use these information, corrected Calculation device 104 promptly imposes one to original residue value and revises computing.Partial sum gate (XOR gates) 114 be a correction value (Correction value) and the addition of original 32 residue values then, and store its result in residue R register.
After residue through revising produced, whether its value can be zero by check it as negative OR operation (NOR operation).If this residue is zero, can assert that then the mistake in the sector data is all corrected, and send host computer to according to this sector data that the request (request) of host computer will be stored in the storage device.After a sector data is successfully corrected in the error correction computing, the next group sector data that reads from dish also will be handled according to aforesaid error correction and error detection mode.Otherwise residue is still non-vanishing if this revises the back, then should continue the error correction computing, just continues to handle remaining RSPC vector.If all RSPC vectors are processed all, and residue R is still non-vanishing, then can implement the error correction computing once more to P-vector and the Q-vector handled.Perhaps, the preferable practice may be to read this sector data again in dish, and carries out whole error correction and error detection process once more.
Before the error correction computing began, cyclic redundancy code generation device 78 divided by P (x), and drew initial crc value CRC with the EDC code word of a sector data
0CD-ROM sector data with pattern 1 is an example, supposes that its each data byte is B
i, i=0 to 2351, then
(B
0,0x
16543+B
0,1X
16542+...+B
2067,6x+B
2067,7)÷P(x)
=Q
0(x) ... CRC
0(x), P (x) is check multinomial, Q herein
0(x) be merchant's formula.When error correction device solves the error code type e and the errors present L of an error byte, and when correcting this byte, the EDC code word after the corrigendum becomes
B
0,0x
16543+B
0,1x
16542+…
+(B
L,0x
7+B
L,1x
6+B
L,2x
5+B
L,3x
4+B
L,4x
3+B
L,5x
2+B
L,6x+B
L,7)x
8(2067-L)
+...+B
2067,6x+B
2067,7
+ (e
0x
7+ e
1x
6+ e
2x
5+ e
3x
4+ e
4x
3+ e
5x
2+ e
6X+e
7) x
8 (2067-L), herein, e
i, ((least significant bit, Least Significant Bit LSB), are the position of error code type e to i=7 MSB) to 0 for highest significant position, Most Significant Bit.Above-mentioned EDC code word can be got residue divided by P (x)
R (x)=CRC
0(x)+r (x) is wherein
r(x)=(e
0x
7+e
1x
6+e
2x
5+e
3x
4+e
4x
3+e
5x
2+e
6x+e
7)x
8(2067-L)modulo?P(x)
The corrected Calculation device 104 of Fig. 7 is promptly carried out the calculating of above-mentioned r (x).Because in error correction procedure, may correct a plurality of error bytes the sector in, so above-mentioned corrected Calculation also need be carried out same number of times, up to error correction device 80 corrected wrong till.Except the first time corrected Calculation be at CRC
0Outside value was carried out, the error detection processing unit was to R (x) its corrected Calculation repeatedly thereafter, as shown in the formula:
R (x)
(new value)=R (x)
(old value)+ r (x)
Aforesaid equation only needs to revise a little, can apply on the sector data of CD-ROM XA pattern 2 forms 1.So mistake error detection processing unit 82 is actually according to following formula and calculates new R value:
R (x)
Newly=R (x)
Old+ { (ex
8 (Lm-L)) modulo P (x), e is the error code type herein, and L is an errors present, and the Lm value is then decided according to the pattern of CD-ROM sector data.The Lm of pattern 1 sector data equals 2067, and the Lm of pattern 2 forms 1 sector data then equals 2075.
Because L is one 12 bit digital, directly calculate (ex
8 (Lm-L)) modulo P (x) is normally unfavorable, because hardware and chip area that need be huge.So, preferably be in some less multiplyings with this computed segmentation.At first, arithmetic expression is rewritten as:
R (x)
Newly=R (x)
Old+ { (ex
8 λ) modulo P (x), λ=(Lm-L) herein.Then this 12 bit digital λ is broken down into 34 bit positions, i.e. λ=λ as shown in Figure 8
82
8+ λ
42
4+ λ
0It is as follows that this conversion makes that the calculating of error code type becomes:
e·x
8λ=e·x
8(256γ8+16γ4+γ0)
=e·x
2048γ8+128γ4+8λ0
=e{x
2048 λ 8* x
128 γ 4* x
8 γ 0Therefore,
(ex
8 λ) modulo P (x)=e{x
2048 λ 8* x
128 λ 4* x
8 λ 0This equation of modulo P (x) can following rule
(A * B) modulo N={ (A moduloN) * B}modulo N further launches.Ex just
8 γThe calculating of modulo P (x) can be via execution * x
2048ModuloP (x) (multiply by x
2048, again divided by P (x) to obtain residue) computing λ
8Inferior, * x
128Modulo P (x) computing λ
4Inferior and * x
8ModuloP (x) computing λ
0Inferior reaching.
Fig. 9 is a preferred embodiment of error detection processing unit of the present invention.The corrected Calculation of residue will be finished with the polynomial multiplication device 104 on one 3 rank, comprising the first rank polynomial multiplication device 150, the second rank polynomial multiplication device 152, the 3rd rank polynomial multiplication device 154, and λ register 136.
This error detection circuit is identical with Fig. 7 embodiment substantially, so do not repeat them here.According to the embodiment of Fig. 7, the error detection treatment circuit of Fig. 9 can receive and store one 32 initial error detection residue CRC from cyclic redundancy code generation device 78
0, as the initial value of residue R register 106.In this stage, MUX 140 can be selected the output of cyclic redundancy code generation device.When error correction device 80 is found a mistake, can produce one 8 error code type e and one 12 errors present L, and send a starting impulse to error detection processing unit control unit 100.After receiving starting impulse, error code type input value e can be latched in the temporary register 142 by MUX 140, for follow-up calculating.
Equally after receiving starting impulse, corresponding to errors present transducer (ELC) 102 circuit of Fig. 7, can convert 12 bit-errors byte address signals 130 of input to a λ value among Fig. 9, and store this and be worth to λ register 136.The conversion of this λ value according to the pattern of CD-ROM sector data and error byte in the EDC code word the position and decide.According to the pattern of CD-ROM sector data, MUX 132 can output 2067 or 2075 both one of, be length for the EDC code word.If sector data is the form of CD-ROM pattern 1, then MUX 132 can selection minuend be 2067.Otherwise, select minuend 2075 to meet the specification of CD-ROM XA pattern 2 forms 1.12 subtracters 134 deduct 12 misaddress with 12 EDC code word size, and store its result to λ register 136.
λ register 136 is by 34 register λ
8, λ
4And λ
0Form.As shown in Figure 8, λ register output 3 signal γ, β and α:
α=(λ
0≠ 0), β=(λ
4≠ 0), reaches γ=(λ
8≠ 0) α, β and γ control " * x respectively
8Modulo P (x) ", " * x
128Modulo P (x) " reach " * x
2048ModuloP (x) " three rank polynomial multiplication computings.
This 3 rank polynomial multiplication device 104 is used to calculate e * x
8 λThe value of modulo P (x).Its algorithm is as follows:
As (λ
0≠ 0)
{
temp={{{temp×x
8αmodulo?P(x)}×x
2048γmodulo?P(x)}
×x
128βmodulo?P(x)}；
If (λ
8＞0) λ then
8=λ
8-1;
If (λ
4＞0) λ then
4=λ
4-1;
If (λ
0＞0) λ then
0=λ
0-1;
The repetitiousness number of times of above-mentioned circulation is (λ
8, λ
4, λ
0) maximum, and end value temp can be stored to temporary register 142 through MUX 140 between operational stage.It should be noted that in addition that in 3 factorial method circuit 104 ordering of 3 factorials method/modulo computings such as 150,152 and 154 can't influence the end product that this counting circuit produced and be stored to temporary register 142.Arrangement mode in the present embodiment, the optimization result of consideration hardware usefulness and chip area.After above-mentioned algorithm is finished, be ex in the temporary register 142
8 λThe value of modulo P (x).This value is then added the value (CRC of residue R register 106 by partial sum gate 114
0Or R
i), its result stores back residue R register through MUX 120 again.
The state of revised residue R can be learnt by the R=0 output signal.According to the state of this signal, can be according to the explanation of earlier figures 7 embodiment, and the data in the decision store storage device can be transferred to host computer, or need do further error correction computing.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; can be used for a variety of modifications and variations, so protection scope of the present invention only is defined by the following claims.
Claims (20)
1. data transmission method between between an optical disc high-capacity storage and a host computer, described method comprises the following steps: at least
Obtain a serial data from described optical disc high-capacity storage, and described serial data is converted to a kind of form that is stored in digital storage;
During described serial data to one first Error Detection Unit after conversion is provided, store serial data after the described conversion in a storage device;
Described serial data is carried out one first error detection computing, with the decision whether have at least one mistake to exist in the described serial data, when described serial data just is being stored to described storage device, at least executed a part the described first error detection computing;
When the described first error detection computing determines that inerrancy is present in the described serial data, transmit described serial data to described host computer,
And when the described first error detection computing is determined to a rare mistake and is present in the described serial data, to the described host computer, can impose an error correction computing to described serial data earlier at the described serial data of transmission.
2. data transmission method as claimed in claim 1 when the described error correction computing of wherein said method is carried out, also comprises the following steps:
Correct the mistake in the described serial data;
Carry out one second error detection computing, to determine whether wrong being present in the described serial data in addition, when the described second error detection computing pointed out that the mistake of not correcting is present in described serial data, then described second error detection computing produced an inerrancy signal; And
Described inerrancy signal by the described second error detection computing is produced is sent to described host computer with the serial data after the described corrigendum.
3. data transmission method as claimed in claim 2, the step of wherein carrying out the described first error detection computing also comprises generation one first error detection value and stores the described first error detection value, the error property in the described serial data of the described first error detection value representation.
4. data transmission method as claimed in claim 3, the step of wherein carrying out described second error detection computing also comprises the correction value of calculating the described first error detection value and revises the described first error detection value, and checks whether the revised described first error detection value is nonzero value.
5. data transmission method as claimed in claim 4, the wherein said first error detection computing comprises described serial data divided by an error checking multinomial, and the wherein said first error detection value is for by the residue of described serial data divided by described error checking multinomial gained.
6. data transmission method as claimed in claim 5, the wherein said second error detection computing is to quote an error code type and the errors present that described error correction computing is produced.
7. data transmission method as claimed in claim 1, the step of wherein changing described serial data comprises the computing of a digital signal processor and the computing of a data deciphering device.
8. data transmission method as claimed in claim 7, wherein said decoder provide data to described first Error Detection Unit and provide described data to a data repacking device, and wherein said data recombination device is in order to store described serial data to described storage device.
9. data transmission method as claimed in claim 8, wherein said serial data is with the staggered Reed-Solomon sign indicating number form coding of a pair of.
10. data transmission method between between an optical disc high-capacity storage and a host computer, described method comprises the following steps: at least
Obtain a serial data from described optical disc high-capacity storage, and store described serial data in a storage device;
Provide described serial data to one first Error Detection Unit;
Whether described serial data is imposed one first error detection computing, have at least one mistake to be present in the described serial data with decision, and determine one first error detection value, the wherein said first error detection value is the characteristic of the mistake in the described serial data;
Described serial data is imposed an error correction computing, one first mistake that in described serial data, exists with identification, and determine the error code type of described first mistake;
Corrigendum is present in described first mistake in the described serial data; And
Described serial data is imposed one second error detection computing, whether have other mistakes to be present in the described serial data with decision.
11. data transmission method as claimed in claim 10 is wherein carried out the described second error detection computing and is comprised error code type based on described first mistake, revises the described first error detection value.
12. data transmission method as claimed in claim 11 wherein also comprises and revises the described first error detection value, and to store the described revised described first error detection value be one second error detection value, determines then whether the described second error detection value is nonzero value.
13. data transmission method as claimed in claim 12, the wherein said second error detection value determines by one second Error Detection Unit, and described second Error Detection Unit is different with described first Error Detection Unit.
14. data transmission method as claimed in claim 12 wherein after described error correction computing is finished, comprises that also the serial data that provides after the described corrigendum is to described host computer.
15. data transmission method as claimed in claim 10 wherein when described serial data just is being stored to described storage device, promptly provides described serial data to described first Error Detection Unit.
16. data transmission method as claimed in claim 10 wherein also comprises if the described first error detection computing when determining that not mistake is present in described serial data, is transmitted described serial data and given described host computer.
17. data transmission method as claimed in claim 10 wherein when the described first error detection value has been stored, is just carried out the first error correction computing and the described second error detection computing.
18. data transmission method as claimed in claim 10, the wherein said first error detection computing comprise described serial data divided by an error checking multinomial, and the described first error detection value is the residue with the described serial data gained of described error checking deconv.
19. data transmission method as claimed in claim 18, an error code type and an errors present that is produced by described error correction computing quoted in the wherein said second error detection computing.
20. data transmission method as claimed in claim 19, wherein said serial data is with the staggered Reed-Solomon sign indicating number form coding of a pair of.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1979671B (en) * | 2005-11-30 | 2010-09-29 | 鸿富锦精密工业（深圳）有限公司 | Error-removing device and method for optical storage apparatus |
| CN106201763A (en) * | 2015-05-22 | 2016-12-07 | 德克萨斯仪器股份有限公司 | Double mode error correcting code/writable primary memory codec |
| CN108281160A (en) * | 2018-01-12 | 2018-07-13 | 南阳师范学院 | The design method of DVD error correcting codes |
-
1998
- 1998-04-13 CN CNB981062962A patent/CN1167222C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1979671B (en) * | 2005-11-30 | 2010-09-29 | 鸿富锦精密工业（深圳）有限公司 | Error-removing device and method for optical storage apparatus |
| CN106201763A (en) * | 2015-05-22 | 2016-12-07 | 德克萨斯仪器股份有限公司 | Double mode error correcting code/writable primary memory codec |
| CN106201763B (en) * | 2015-05-22 | 2021-03-05 | 德克萨斯仪器股份有限公司 | Dual mode error correcting code/write-once memory codec |
| CN108281160A (en) * | 2018-01-12 | 2018-07-13 | 南阳师范学院 | The design method of DVD error correcting codes |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1167222C (en) | 2004-09-15 |
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