CN101452722B - Error detection code generating circuit, code circuit using the circuit and correlation method - Google Patents

Error detection code generating circuit, code circuit using the circuit and correlation method Download PDF

Info

Publication number
CN101452722B
CN101452722B CN2007101962507A CN200710196250A CN101452722B CN 101452722 B CN101452722 B CN 101452722B CN 2007101962507 A CN2007101962507 A CN 2007101962507A CN 200710196250 A CN200710196250 A CN 200710196250A CN 101452722 B CN101452722 B CN 101452722B
Authority
CN
China
Prior art keywords
error
detecting code
data
header
storage arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2007101962507A
Other languages
Chinese (zh)
Other versions
CN101452722A (en
Inventor
陈建志
郭协星
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Realtek Semiconductor Corp
Original Assignee
Realtek Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Realtek Semiconductor Corp filed Critical Realtek Semiconductor Corp
Priority to CN2007101962507A priority Critical patent/CN101452722B/en
Publication of CN101452722A publication Critical patent/CN101452722A/en
Application granted granted Critical
Publication of CN101452722B publication Critical patent/CN101452722B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

The invention relates to an error detecting code generation circuit, which comprises a memory device, the error detecting code generation circuit, a header generator and an error detecting code correction code. The error detecting code generation circuit is used for generating a first error detecting code according to at least one master data, and storing the first error detecting code to the memory device. The header generator is used for generating a header according to header information. The error detecting code correction circuit is used for reading the first error detecting code and correcting the first error detecting code according to the header, so as to generate a second error detecting code.

Description

The coding circuit and the correlation technique of error detecting code generation circuit and this circuit of use
Technical field
The present invention relates to error detecting code generation circuit and use this coding circuit that produces circuit, particularly data of optical disk error detecting code generation circuit and use this to produce the coding circuit of circuit.
Background technology
Generally speaking, a DVD CD is made up of continuous error correcting code block (Error CorrectionCode Block ECC Block), and a DVD CD contains 143,500 ECCBlock at least.Below be ECC Block synoptic diagram.Fig. 1 has illustrated the synoptic diagram of the error correcting code block 100 of DVD CD, and as shown in Figure 1, it is the individual row of 208 (192+16), the total 182Bytes (172+10) of each row that each error correcting code block is divided into.The preceding 172Bytes of each row, the usefulness that can deposit for burning data and last 10 information that Bytes deposits then are so-called PI (Parity of theInner code, inner parity code); Last 16 row as for each error correcting code block then are called PO (Parity of the Outer code, outer parity sign indicating number).In simple terms, PI, PO are in order correctly to read the CD baking data, and the check code of formulating.Generally speaking, PI, PO utilize reed-solomon code (Reed-Solomon Codes) coding and produce.
In addition, error correcting code block 100 comprises 16 sections (only illustrating the section 101,102,103 of a part).And each section all comprises master data (main data) 2048 bytes, header (header) 12 bytes and error-detecting code (error detection code, EDC) 4 bytes.Header comprises error-detecting code (IED) 2 bytes and other supplementarys (CPRMAI) 6 bytes of sector data (sector information) 1 byte, identification code of date (ID number) 3 bytes, identification code of date usually.
Generally speaking, the optical disc encoding system can comprise a storage arrangement, a bus, a transmission interface, a scrambler, a header generator, an error detecting code generation device and a scrambler, and wherein transmission interface, scrambler, header generator, error detecting code generation device and scrambler are coupled to storage arrangement respectively by bus.Transmission interface can be ATAPI (Advanced Technology Attachment/ATA Packet Interface, the X3T1Q work group of ANSI defines).Transmission interface is in order to receive master data and to import storage arrangement into, scrambler (Scrambler) is handled in order to master data is carried out scrambling, the header generator is in order to receive header information to produce header, the error detecting code generation device is in order to produce error-detecting code according to master data and header, and scrambler is encoded to carry out the PI/PO coding according to header, master data and error-detecting code.The shortcoming of this type systematic is that scrambler must be read the data of whole section again and writes back, expends very much frequency range.In addition, according to the structure of optical disc encoding system, the error detecting code generation device also need be read whole section to produce the error-detecting code that 4 bytes are only arranged, and is quite inefficent.
In order to improve the problems referred to above, known technology has proposed corresponding invention, it utilized scrambler that master data is carried out scrambling and handles and utilize the error detecting code generation device to produce error-detecting code before header and master data deposit storage arrangement in, therefore can avoid above-mentioned problem.Yet because master data is from host computer, header information is from the firmware in the chip, both source differences.Therefore both need have the coordination system when transmitting, and for example must suspend the transmission of master data earlier when transmitting stem, or use the buffer buffers host data.And the transmission speed of transmission interface is subjected to the specification standard usually, if both coordinate improper or the firmware flow process wrong, can cause impact damper fully loaded, easily cause the transmission interface bust this.And writing of firmware, the flow process of transmission interface and stem generator is collocation mutually, can't be considered as two independently flow processs.
Summary of the invention
Therefore, a purpose of the present invention is to propose a kind of error detecting code generation circuit, and it independently under the situation, also can save the frequency range of EDC at transmission interface and header generator.
Therefore, a purpose of the present invention is to propose a kind of coding circuit, and it independently under the situation, can carry out encoding operation to data of optical disk by minimum EDC frequency range at transmission interface and header generator.
Embodiments of the invention disclose a kind of error detecting code generation circuit, comprise: a storage arrangement; One error detecting code generation circuit is coupled to this storage arrangement, in order to producing one first error-detecting code according at least one master data, and this first error-detecting code is stored to this storage arrangement; One header generator is coupled to this storage arrangement, in order to produce this header according to header information; And error-detecting code positive circuit more, be coupled to this storage arrangement, in order to read this first error-detecting code and to correct this first error-detecting code to produce one second error-detecting code in this storage arrangement certainly according to this header.
Embodiments of the invention also disclose a kind of coding circuit, desire to write to the data of optical disk of a CD in order to coding, comprise: a storage arrangement; One error detecting code generation circuit is coupled to this storage arrangement, in order to producing one first error-detecting code according at least one master data, and this first error-detecting code is stored to this storage arrangement; One scrambler is coupled to this storage arrangement, is used for producing master data after the scrambling according to this master data, and master data after this scrambling is stored to this storage arrangement; One header generator is coupled to this storage arrangement, in order to produce this header according to header information; One error-detecting code is positive circuit more, is coupled to this storage arrangement, in order to read this first error-detecting code and to correct this first error-detecting code to produce one second error-detecting code according to this header in this storage arrangement certainly; And a scrambler, be coupled to this storage arrangement, in order to this data of optical disk of encoding according to master data after this second error-detecting code and this scrambling.
Embodiments of the invention also disclose a kind of error detecting code generation method, comprise: produce one first error-detecting code according at least one master data; Produce this header according to header information; And correct this first error-detecting code to produce one second error-detecting code according to this header.
Embodiments of the invention also disclose a kind of coding method, desire to write to the data of optical disk of a CD in order to coding, comprise: produce one first error-detecting code according at least one master data; Produce master data after the scrambling according to this master data; Produce this header according to header information; Correct this first error-detecting code to produce one second error-detecting code according to this header; And according to this data of optical disk of encoding of master data after this second error-detecting code and this scrambling.
In the above-described embodiment, master data and header are separated to handle, and therefore do not have the problem of above-mentioned hamony, and error detecting code generation circuit must not read all data in storage arrangement, can save the required frequency range of reading of data.
Description of drawings
Fig. 1 has illustrated the synoptic diagram of the error correcting code block 100 of DVD CD.
Fig. 2 has illustrated the data of optical disk error detecting code generation circuit according to the first embodiment of the present invention.
Fig. 3 has illustrated data of optical disk error detecting code generation circuit according to a second embodiment of the present invention.
Fig. 4 has illustrated data of optical disk error detecting code generation method according to an embodiment of the invention.
Fig. 5 has illustrated the data of optical disk coding circuit according to the first embodiment of the present invention.
Fig. 6 has illustrated data of optical disk coding circuit according to a second embodiment of the present invention.
Fig. 7 has illustrated data of optical disk coding circuit according to a preferred embodiment of the invention.
Fig. 8 data of optical disk coding method according to an embodiment of the invention.
[main element symbol description]
100 error correcting code blocks
101,102,103 sections
201,301 storage arrangements
202,302 buses
205,305 transmission interfaces
501,601 scramblers
207,307,309 header generators
503,603,703 scramblers
200,300 error detecting code generation circuit
203,303,701 error detecting code generation circuit
209 error-detecting codes are positive circuit more
500,600,700 coding circuits
Embodiment
In the middle of instructions and claims, used some vocabulary to censure specific element.Those skilled in the art should understand, and hardware manufacturer may be called same element with different nouns.This specification and claims book is not used as distinguishing the mode of element with the difference of title, but the criterion that is used as distinguishing with the difference of element on function.Be an open term mentioned " comprising " in the middle of instructions and claims in the whole text, so should be construed to " comprise but be not limited to ".In addition, " couple " speech and comprise any indirect means that are electrically connected that directly reach at this.Therefore, be coupled to one second device, then represent this first device can directly be electrically connected in this second device, or be electrically connected to this second device indirectly through other devices or connection means if describe one first device in the literary composition.
Fig. 2 has illustrated the data of optical disk error detecting code generation circuit 200 according to the first embodiment of the present invention.As shown in Figure 2, data of optical disk error detecting code generation circuit 200 comprises a storage arrangement 201, a bus 202, an error detecting code generation circuit 203, a transmission interface 205 (for example, ATAPI), a header generator 207 and error-detecting code positive circuit 209 more.Transmission interface 205 is in order to receive master data MD (main data).Error detecting code generation circuit 203 sees through bus 202 and is coupled to storage arrangement 201, in order to produce one first error-detecting code EDC according at least one master data MD 1, and with the first error-detecting code EDC 1Be stored to storage arrangement 201.Header generator 207 is coupled to storage arrangement 201, in order to produce header H according to header information HI.Error-detecting code more positive circuit 209 is coupled to storage arrangement 201, in order to read the first error-detecting code EDC in storage arrangement 201 1And correct the first error-detecting code EDC according to header H 1To produce one second error-detecting code EDC 2
Except that aforesaid operations, error detecting code generation circuit 203 can be in addition produces one first data in conjunction with the alternate data Z of master data MD and header H, and foundation first data produce the first error-detecting code EDC 1And error-detecting code more positive circuit 209 produces one second data in conjunction with header H and alternate data Z in addition, and corrects the first error-detecting code EDC according to second data 1To produce the second error-detecting code EDC2.If this alternate data Z is at 0 o'clock, just is equal to and does not add alternate data.
Below will utilize arithmetic expression to cooperate Fig. 2 to be described in more detail the mode of operation of data of optical disk error detecting code generation circuit 200, it is noted that, following arithmetic expression is only in order to explanation, be not in order to limit the present invention, those skilled in the art work as can be under notion of the present invention, the any content of change arithmetic expression and obtain the result of same spirit, it also should be within the scope of the present invention.
F(x)=main_data(x)
Figure 2007101962507_0
header(x)
M(X)=z(x)
Figure 2007101962507_1
main_data(x)
H(x)=z(x)
Figure 2007101962507_2
header(x)
F(x)=M(x)
Figure 2007101962507_3
H(X)
EDC(x)=F(x)modP(x)=(M(x)
Figure 2007101962507_4
H(x))modP(x)=[M(x)modP(x)] [H(x)modP(x)]=EDC_m(x)
Figure 2007101962507_6
EDC_h(x)
In this arithmetic expression, suppose that F (x) is that desire is carried out EDC coded data polynomial expression, can be divided into main_data (x) (master data MD), and header (x) two parts (header H), when the correct header of the unknown, error detecting code generation circuit 203 is filled any z (x) (being alternate data Z) and is calculated EDC_m (x) (the i.e. first error-detecting code EDC divided by a predetermined polynomial expression P (x) (to firm:EDC operation with data divided by a specific polynomial expression to obtain EDC) with correct main_data (x) part earlier 1), and be stored to storage arrangement 201.And after header generator 207 obtains correct header H (header (x)) according to header information HI, header (x) by error-detecting code more positive circuit 209 also add behind the same alternate data z (x) divided by predetermined polynomial expression P (x) to obtain EDC_h (x).Again EDC_m (x) and EDC_h (x) are done the operation of XOR at last, known as those skilled in the art, the meeting that influences of z (x) is offset by the operation of XOR, so after the operation of EDC_m (x) and EDC_h (x) execution XOR, can produce correct EDC (x) (is EDC 2).When the data z that fills arbitrarily (x) is 0, H (x)=header (x), M (x)=main_data (x) can treat as and not add z (x).
By this structure, can make transmission interface 205 and 207 parallelizations of header generator running, and interface can adopt DMA port, helps the IPization design.And error detecting code generation circuit 203 must not read whole data (2060 byte), only need read ID field (12Bytes), read EDC_m (x) (4Bytes), write back correct EDC (x) again (4Bytes) after revising, therefore can save the accessing operation of 2044Bytes.
Fig. 3 has illustrated data of optical disk error detecting code generation circuit 300 according to a second embodiment of the present invention.Data of optical disk error detecting code generation circuit 300 comprises a storage arrangement 301, a bus 302, an error detecting code generation circuit 303, a transmission interface 305 (for example, ATAPI), a header generator 307 and error-detecting code positive circuit 309 more.Be that with Fig. 2 difference the header generator 307 of data of optical disk error detecting code generation circuit 300 is connected to more positive circuit 309 of error-detecting code in addition, therefore error-detecting code more positive circuit 309 can directly receive header H from header generator 309, and revise the first error-detecting code EDC according to header H 1To produce the second error-detecting code EDC 2The practice by this can shorten computing execution time of header generator 309.
Data of optical disk error detecting code generation circuit 200 and 300 the mode of operation whole step shown in Figure 4 that is of can uniting.Fig. 4 has illustrated the data of optical disk error detecting code generation method according to one embodiment of the invention.The method comprises:
Step 401
Produce one first error-detecting code according at least one master data.
Step 403
Produce header according to header information.
Step 405
Correct first error-detecting code to produce one second error-detecting code according to header.
Because the method corresponds to data of optical disk error detecting code generation circuit 200 and 300, so its detail characteristic can be learnt by foregoing description, so do not repeat them here.
Fig. 5 has illustrated the data of optical disk coding circuit 500 according to the first embodiment of the present invention.Data of optical disk coding circuit 500 corresponds to the data of optical disk error detecting code generation circuit 200 of Fig. 2.Data of optical disk coding circuit 500 is except the data of optical disk error detecting code generation circuit 200 that comprises Fig. 2, and other comprises a scrambler (scrambler) 501 and a scrambler 503.After scrambler 501 received master data MD, just scrambling master data MD was to produce after the scrambling master data DMD and to be stored into storage arrangement 201.And scrambler 503 is according to master data DMD, header H after the scrambling and the second error correcting code EDC 2Encode to produce PI, PO.
Fig. 6 has illustrated data of optical disk coding circuit 600 according to a second embodiment of the present invention.Data of optical disk coding circuit 600 corresponds to the data of optical disk error detecting code generation circuit 300 of Fig. 3.Same, data of optical disk coding circuit 600 is that with the difference of the data of optical disk error detecting code generation circuit 300 of Fig. 3 data of optical disk coding circuit 600 also comprises a scrambler (scrambler) 601 and a scrambler 603.After scrambler 601 received master data MD, just scrambling master data MD was to produce after the scrambling master data DMD and to be stored into storage arrangement 301.And scrambler 603 is according to master data DMD, header H after the scrambling and the second error correcting code EDC 2Encode to produce PI, PO.
Fig. 7 has illustrated the data of optical disk coding circuit 700 of a third embodiment in accordance with the invention.Data of optical disk coding circuit 700 has and data of optical disk coding circuit 500 and data of optical disk coding circuit 600 components identical, and its difference is ways of connecting.As shown in Figure 7, error-detecting code more positive circuit 701 be connected to scrambler 703.Therefore, in this embodiment, the first error correcting code EDC 1Be stored in storage arrangement 705 with header H, then error-detecting code more positive circuit 701 read the first error correcting code EDC from storage arrangement 705 1With header H, and revise the first error correcting code EDC according to header H 1To produce the second error correcting code EDC 2Scrambler 703 is according to master data DMD, header H after the scrambling and the second error correcting code EDC 2Encode to produce PI, PO.Note that in this embodiment error-detecting code more positive circuit 701 must be utilized the second error correcting code EDC at scrambler 703 2Carry out the operation that the PI/PO coding is finished the corrigendum sign indicating number of righting the wrong before.Fig. 8 is according to the data of optical disk coding method of one embodiment of the invention, and the method corresponds to Fig. 5 to circuit shown in Figure 7.The method comprises:
Step 801
Produce one first error-detecting code according at least one master data.
Step 803
Produce master data after the scrambling according to this master data.
Step 805
Produce header according to header information.
Step 807
Correct first error-detecting code to produce one second error-detecting code according to header.
Step 809
According to master data coding data of optical disk after second error-detecting code and the scrambling.
Because the method corresponds to data of optical disk coding circuit 500,600 and 700, so its detail characteristic can be learnt by foregoing description, so do not repeat them here.
In the above-described embodiment, utilize an alternate data Z (also can be considered temporary transient one of the correct header that substitutes and substitute header) temporarily to replace correct header, to produce a temporary transient EDC, wait to obtain after the correct header, the influence of eliminating this alternative header again is to produce correct EDC, because master data and header adopt the mode of parallel processing, so do not have the problem of hamony in the prior art, and, error detecting code generation circuit must not read all data in storage arrangement, can save the required frequency range of reading of data.Be noted that, though the foregoing description explains with the DVD data of optical disk, be not that circuit disclosed in this invention and method are when the data of optical disk that can utilize in other specifications in order to qualification the present invention, also can use on non-data of optical disk, it also should be within the scope of the present invention.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claims of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims (10)

1. data of optical disk error detecting code generation circuit comprises:
One storage arrangement;
One error detecting code generation circuit is coupled to this storage arrangement, in order to producing one first error-detecting code according at least one master data, and this first error-detecting code is stored to this storage arrangement;
One header generator is coupled to this storage arrangement, in order to produce a header according to header information; And
One error-detecting code is positive circuit more, is coupled to this storage arrangement, in order to read this first error-detecting code and to correct this first error-detecting code to produce one second error-detecting code according to this header in this storage arrangement certainly.
2. data of optical disk error detecting code generation circuit as claimed in claim 1, wherein this error detecting code generation circuit produces one first data according to an alternate data of this master data and this header in addition, and produce this first error-detecting code according to these first data, and this error-detecting code more positive circuit produces one second data according to this header and this alternate data, and corrects this first error-detecting code to produce this second error-detecting code according to these second data.
3. data of optical disk error detecting code generation circuit as claimed in claim 1, wherein this header generator system is coupled to this storage arrangement, and this header is stored in this storage arrangement, and this error-detecting code more positive circuit system reads this header from this storage arrangement, and corrects this first error-detecting code to produce second error-detecting code according to this header.
4. data of optical disk error detecting code generation circuit as claimed in claim 1, wherein this error-detecting code more positive circuit more be coupled to this header generator, and this error-detecting code more positive circuit system receives this header from this header generator, and corrects this first error-detecting code to produce this second error-detecting code according to this header.
5. data of optical disk error detecting code generation circuit as claimed in claim 1, wherein this error detecting code generation circuit sees through a bus and is coupled to this storage arrangement.
6. coding circuit comprises:
One storage arrangement;
One error detecting code generation circuit is coupled to this storage arrangement, in order to producing one first error-detecting code according at least one master data, and this first error-detecting code is stored to this storage arrangement;
One scrambler is coupled to this storage arrangement, is used for producing master data after the scrambling according to this master data, and master data after this scrambling is stored to this storage arrangement;
One header generator is coupled to this storage arrangement, in order to produce a header according to header information;
One error-detecting code is positive circuit more, is coupled to this storage arrangement, in order to read this first error-detecting code and to correct this first error-detecting code to produce one second error-detecting code according to this header in this storage arrangement certainly; And
One scrambler is coupled to this storage arrangement, in order to the data of optical disk of encoding according to master data after this second error-detecting code and this scrambling.
7. coding circuit as claimed in claim 6, wherein this coding circuit system this data of optical disk of coding is to write to a CD with this data of optical disk.
8. coding circuit as claimed in claim 6, wherein this error detecting code generation circuit produces one first data in conjunction with an alternate data of this master data and this header in addition, and produces this first error-detecting code according to these first data.
9. coding circuit as claimed in claim 8, wherein this error-detecting code more positive circuit in addition produce one second data in conjunction with this header and this alternate data, and correct this first error-detecting code to produce this second error-detecting code according to these second data.
10. coding circuit as claimed in claim 6, wherein this header generator is stored to this storage arrangement with this header, and this scrambler more is coupled to more positive circuit of this error-detecting code, in order to this storage arrangement certainly read after this scrambling master data and this header and certainly this error-detecting code more positive circuit receive this second error-detecting code, and produce a coded data according to master data, this header and this second error-detecting code after this scrambling.
CN2007101962507A 2007-11-30 2007-11-30 Error detection code generating circuit, code circuit using the circuit and correlation method Active CN101452722B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2007101962507A CN101452722B (en) 2007-11-30 2007-11-30 Error detection code generating circuit, code circuit using the circuit and correlation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2007101962507A CN101452722B (en) 2007-11-30 2007-11-30 Error detection code generating circuit, code circuit using the circuit and correlation method

Publications (2)

Publication Number Publication Date
CN101452722A CN101452722A (en) 2009-06-10
CN101452722B true CN101452722B (en) 2011-08-31

Family

ID=40734917

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007101962507A Active CN101452722B (en) 2007-11-30 2007-11-30 Error detection code generating circuit, code circuit using the circuit and correlation method

Country Status (1)

Country Link
CN (1) CN101452722B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8984373B2 (en) * 2012-02-22 2015-03-17 Silicon Motion, Inc. Method for accessing flash memory and associated flash memory controller
TWI677876B (en) 2018-10-12 2019-11-21 慧榮科技股份有限公司 Encoder built-in self-test circuit applied in flash memory controller and associated method
TWI782341B (en) * 2018-11-14 2022-11-01 慧榮科技股份有限公司 Flash memory controller and encoding circuit within flash memory controller
TWI712268B (en) * 2018-11-14 2020-12-01 慧榮科技股份有限公司 Flash memory controller and encoding circuit and decoding circuit within flash memory controller

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6721917B2 (en) * 2000-06-16 2004-04-13 Acer Laboratories, Inc. Method and system for optical disk decoding
CN1525478A (en) * 2003-09-15 2004-09-01 威盛电子股份有限公司 Data reading apparatus and method
CN1534622A (en) * 2003-03-11 2004-10-06 ��ʢ���ӹɷ����޹�˾ Error detecting code producton method and method of producing error detecting code in multiple sections
CN1707441A (en) * 2004-05-21 2005-12-14 三洋电机株式会社 Circuit and method for encoding data and data recorder
CN1755819A (en) * 2004-10-01 2006-04-05 其乐达科技股份有限公司 Real-time cyclic redundanty check code generation and scrambling in DVD storage devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6721917B2 (en) * 2000-06-16 2004-04-13 Acer Laboratories, Inc. Method and system for optical disk decoding
CN1534622A (en) * 2003-03-11 2004-10-06 ��ʢ���ӹɷ����޹�˾ Error detecting code producton method and method of producing error detecting code in multiple sections
CN1525478A (en) * 2003-09-15 2004-09-01 威盛电子股份有限公司 Data reading apparatus and method
CN1707441A (en) * 2004-05-21 2005-12-14 三洋电机株式会社 Circuit and method for encoding data and data recorder
CN1755819A (en) * 2004-10-01 2006-04-05 其乐达科技股份有限公司 Real-time cyclic redundanty check code generation and scrambling in DVD storage devices

Also Published As

Publication number Publication date
CN101452722A (en) 2009-06-10

Similar Documents

Publication Publication Date Title
CN101635158B (en) Methods, apparatuses, systems, and architectures for quickly and reliably encoding and/or decoding system data
US5805799A (en) Data integrity and cross-check code with logical block address
US8726140B2 (en) Dummy data padding and error code correcting memory controller, data processing method thereof, and memory system including the same
CN101609418B (en) The system of data and data mask position is transmitted in the common frame with shared error code
JP3234130B2 (en) Error correction code decoding method and circuit using this method
CN101276627B (en) Techniques for correcting errors using iterative decoding
US5477551A (en) Apparatus and method for optimal error correcting code to parity conversion
CN102017425B (en) System and method for performing concatenated error correction
US7836379B1 (en) Method for computing buffer ECC
CN107918571B (en) Method for testing storage unit and device using same
JP2003507985A (en) System and method for detecting 2-bit errors and correcting errors due to component failure
US7418645B2 (en) Error correction/detection code adjustment for known data pattern substitution
US8638515B2 (en) Writing data to a storage medium
CN101281788A (en) Flash memory system as well as control method thereof
CN101452722B (en) Error detection code generating circuit, code circuit using the circuit and correlation method
CN111124741B (en) Enhanced type checking and error correcting device facing memory characteristics
CN103631670A (en) Storage device of storage, storage controller and data processing method
CN104733051A (en) Decoding method of parity check code, memory storage apparatus and control circuit unit
JP4819843B2 (en) ECC code generation method for memory device
JP2003501916A (en) Mechanism for decoding linear shift codes to facilitate correction of bit errors due to component failure
CN106528437B (en) Data storage system and related method thereof
TWI536749B (en) Decoding method, memory storage device and memory controlling circuit unit
CN100399462C (en) Optical disk data read out method with error treatment
CN112133362A (en) Memory storage device and memory testing method thereof
CN112306733B (en) Memory device, memory controller and data access method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant