CN1231547A

CN1231547A - Low power input buffer

Info

Publication number: CN1231547A
Application number: CN 98106227
Authority: CN
Inventors: 刘汉城; 卢裕阶; 胡耀达
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 1998-04-07
Filing date: 1998-04-07
Publication date: 1999-10-13

Abstract

The low power TTL-to-CMOS input buffer for buffering electronic signal from TTL to CMOS at least contains voltage shifting-down circuit for producing the first output signal inverted with TTL signal according to the TTL signal, and according to the TTL signal and said the first output signal a reference shifting-up circuit can produce the second output signal which is identical to the TTL signal in logic state and meets the CMOS voltage reference.

Description

Low-power input buffer

The present invention relates to a kind of buffer that is used for electronic system, particularly relate to a kind of low-power TTL to CMOS input buffer, be used for buffer transistor-transistor logic (TTL) electronic signal to CMOS (Complementary Metal Oxide Semiconductor) (CMOS) electronic signal.

Digital circuit can be divided into bipolarity (bipolar) circuit and unipolarity (unipolar) circuit according to its manufacturing technology.(transistor-transistor logic TTL) is the most generally use in the bipolar circuit wherein a kind of to transistor-transistor logic circuit.The power source voltage Vcc of TTL circuit fixes on 5 volts usually, and the definition of its logical one voltage V (1) and logical zero voltage V (0) then is shown in Fig. 1, and wherein voltage V (0) is between 0.0 and 0.8 volt, and voltage V (1) is between 2.2 and 5 volts.

CMOS (Complementary Metal Oxide Semiconductor) (CMOS) is one of technology of the most normal use in the unipolarity circuit.Different with the fixed power source voltage of TTL circuit is, CMOS can work in in a big way the voltage range, and wherein logical zero voltage is defined in 30% the supply voltage (promptly less than 30%V _Dd) voltage range in, and logical one voltage is defined in supply voltage greater than 70% (promptly greater than 70%V _Dd) voltage range in.Supply voltage value is bigger, and then the immunity to interference of electronic noise (immunity) is then bigger.

Compare with the TTL circuit, the power consumption of cmos circuit is less, and the current densities of cmos circuit is big than TTL.Yet the advantage of TTL circuit is to be suitable for high-speed circuit design.

Because TTL and cmos circuit respectively have its advantage, so both all are used for general electronic system simultaneously, for example are used for the additional card (add-on cards) and the computer main board of PC.Therefore, needing badly to provide a signal buffer between TTL and cmos circuit, so that entire circuit can operate as normal.

Fig. 2 A shows a traditional TTL-to-CMOS input buffer, and it comprises the

inverter

20 and 22 of two series connection, in order to the TTL reference voltage is converted to the CMOS reference voltage.Inverter 20 comprises N type MOS field-effect transistor 201 and P type MOS field-effect transistor 203, and its drain electrode and grid are connected to each other respectively, and wherein transistor 201 is as driver, and transistor 203 is then as load.

Consult Fig. 1, wherein, voltage is for 2.2 volts to be 1 the poorest situation at the TTL logic voltage.Suppose the critical voltage V of transistor 201 and transistor 203 _ThBe 1 volt, and at the input voltage V of an A _InIt is 2.2 volts, because the grid of transistor 201 is to source voltage V _GsnGreater than its critical voltage V _Th, so transistor 201 is conductings.Moreover, because the grid of transistor 203 is to source voltage V _GspBe-2.8 volts of (V _In-V _Dd=2.2-5.0=-2.8), its absolute value is greater than its critical voltage V _Th, so transistor 203 also is conducting.Because transistor 201 and transistor 203 equal conductings, make power supply V _DdWith ground connection V _SsBetween form a DC channel, thereby consumed very big power.

Another traditional TTL-to-CMOS input buffer shown in Fig. 2 B, it is published in " IEEE solid-state circuit magazine (IEEE Journal of Solid-State Circuits) ", 30 volumes, 5 phases, May nineteen ninety-five, 616-620 page or leaf.The transistorized critical voltage Vth of same hypothesis is 1 volt, and at the input voltage V of a B _InBe 2.2 volts of voltages of poor situation, then N type MOS field-effect transistor 241 is switched on, and P type MOS field-effect transistor 243 since its grid to source voltage V _GspFor-5 volts (it is zero supposing to drain to the conducting voltage of source electrode), therefore also be conducting.Also in conducting state, so transistor 247 grids are to source voltage V as load for transistor 245 _GspBe-2.8 volts of (V _InB-V _Dd=2.2-5.0=-2.8), its absolute value is greater than its critical voltage V _Th, so transistor 247 also is conducting.Because transistor 241 and transistor 247 are conducting, thereby have consumed very big power.

In view of many shortcomings that conventional buffer produced in the foregoing invention background, main purpose of the present invention is to provide a kind of TTL-to-CMOS input buffer, be used for buffer transistor-transistor logic (TTL) electronic signal to CMOS (Complementary Metal Oxide Semiconductor) (CMOS) electronic signal, and reduce power consumption.The present invention comprises shift circuit under the voltage at least, be used for according to the TTL signal produce one with first output signal of TTL signal inversion.Also comprise reference shifting-up circuit, be used for producing one identical with the logic state of TTL signal and meet second output signal of cmos voltage benchmark according to TTL signal and first output signal.

With reference to the detailed description of accompanying drawing to the embodiment of the invention, it is clearer that above-mentioned purpose of the present invention, advantage and feature will become, in the accompanying drawing:

Fig. 1 shows the logical one voltage V (1) and the logical zero voltage V (0) of TTL circuit;

Fig. 2 A shows that a traditional TTL-is to-CMOS input buffer;

Fig. 2 B shows that another traditional TTL-is to-CMOS input buffer;

Fig. 3 A shows the circuit diagram of one embodiment of the invention; With

Fig. 3 B shows the circuit diagram of another embodiment of the present invention.

Fig. 3 A shows one of embodiment of the invention, and wherein transistor T 4, T5 and T6 form shift circuit 30 under the voltage.N transistor npn npn T6 and P transistor npn npn T5 are as an inverter, and wherein transistor T 6 is a driver, and transistor T 5 is load.Transistor T 6 and transistor T 5 are cascaded, and its drain electrode is continuous, and its output is then pulled out from a d.The grid of transistor T 6 and transistor T 5 links to each other, and input signal TTL-in then is connected to its public grid.The grid of transistor T 4 links to each other with drain electrode, with the load as transistor T 6 and transistor T 5.The source electrode of transistor T 4 is connected to the source electrode of transistor T 5, and the drain electrode of transistor T 4 is connected to voltage source V _Dd(being 3.0 volts in the present embodiment).

Transistor T 1, T2, T3 and T7 form a reference shifting-up circuit, so that the voltage reference of signal TTL-in rises to specific cmos voltage benchmark.The grid of N transistor npn npn T3 is connected to the public grid of transistor T 5 and T6, and the grid of transistor T 7 is connected to the output point d of transistor T 5 and T6.Transistor T 1 and T2 connect with transistor T 3 and T7 respectively, and its grid of interconnection and drain electrode, as shown in Figure 3A.

The critical voltage V of all crystals pipe T1 to T7 _ThAll be assumed to be 1 volt.Therefore, be conducting state as the transistor T 4 of load always, and ignore the draining of its conducting to source voltage V _DsWhen the voltage of input signal TTL-in is 0.8 volt or during less than 0.8 volt, transistor T 3 and T6 conducting, and the grid of transistor T 5 is to source voltage V _GspBe-2.2 volts (0.8-3=-2.2) that its absolute value is greater than its critical voltage V _Th, so transistor T 5 is conductings.The voltage of point d is 2 volts of (V _Dd-V _Th=30-1.0=2), so conducting transistor T 7.The output signal output of entire circuit is pulled out by the drain electrode of transistor T 2, because transistor T 7 is conducting, so output signal output is pulled to the ground connection reference voltage.Moreover the voltage of this output signal output is subjected to the transistor T 1 of conducting and the effect of the transistor T 2 of closing and being held.

When input signal TTL-in is logical one (2.2 volts or greater than 2.2 volts), transistor T 3 and T6 are switched on, and the grid of transistor T 5 is to source voltage V _GspBe-0.8 volt (2.2-3=-0.8) that its absolute value is less than its critical voltage V _Th, so transistor T 5 is closed.The attention of value be that input signal TTL-in is under 2.2 volts of the poorest situations, because its grid is to source voltage V _GspBe-0 8 volt (2.2-3=-0.8) that its absolute value is less than its critical voltage V _Th, therefore having only transistor T 6 is conductings, has therefore avoided the problem of a plurality of transistors conducting simultaneously in traditional input buffer.The transistor T 6 that the voltage of some d is switched on is pulled to V _Ss(being 0 volt in the present embodiment), thereby closed transistor T 7.

Because transistor T 3 is conducting, thereby the voltage of some a is pulled to V _Ss(being 0 volt in the present embodiment), thus conducting transistor T 2.Therefore, output voltage output is promoted to V _Dd, and by means of the transistor T 2 of conducting and the transistor T 1 of closing and maintain voltage.

Fig. 3 B shows another embodiment of the present invention, and this circuit is to have 5 volts of V _DdTTL-to-cmos buffer device.Therefore the circuit of the syndeton of this circuit and operation principle and Fig. 3 A repeats no more much at one.Maximum difference be in, the circuit of Fig. 3 B uses two load transistor T4 ' and T8 ', and does not resemble the one-transistor T4 of Fig. 3 A.Input signal TTL-in is under 2.2 volts of the poorest situations, because its grid is to source voltage V _GspFor-08 volt (2.2-3=-0.8), identical with the situation of Fig. 3 A, guarantee that it is a closed condition.For other particular power source voltage V _Dd, the number of this load transistor also can change thereupon.

The above is the preferred embodiments of the present invention only, is not to be used to limit scope of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the claims.

Claims

1. a buffer unit is used to cushion a transistor-transistor logic (TTL) electronic signal to a CMOS (Complementary Metal Oxide Semiconductor) (CMOS) electronic signal, and this device comprises at least:

Moving device under the voltage, be used for according to described TTL signal produce one with first output signal of described TTL signal inversion; And

Moving device on the benchmark is used for producing according to described TTL signal and described first output signal one identical with the logic state of described TTL signal and meet second output signal of cmos voltage benchmark.

2. buffer unit as claimed in claim 1, moving device comprises an inverter at least under the wherein said voltage, and described TTL signal is connected to an input of described inverter, and described first output signal is connected to an output of described inverter.

3. buffer unit as claimed in claim 2, wherein said inverter comprises the complementary transistor of one group of series connection at least, the drain electrode of described complementary transistor links to each other and is connected to described first output signal, and the grid of described complementary transistor links to each other and is connected to described TTL signal.

4. buffer unit as claimed in claim 2 also comprises at least one load transistor, and the source electrode of described load transistor is connected to described inverter, and one of them the drain electrode of described load transistor is connected to a voltage source.

5. buffer unit as claimed in claim 4, the number of wherein said load transistor are one, and the current potential of described voltage source is approximately 3 volts.

6. buffer unit as claimed in claim 4, the number of wherein said load transistor are two, and the current potential of described voltage source is approximately 5 volts.

7 buffer units as claimed in claim 1, moving device comprises at least on the wherein said benchmark:

One input transistors, its grid are connected to described TTL signal; And

One output transistor, its grid are connected to described first output signal, and its drain electrode is connected to described second output signal.

8. buffer unit as claimed in claim 7 also comprises:

One input displacement transistor, described input displacement transistor and described input transistors complementation, described input displacement transistor drain is connected to the drain electrode of described input transistors, and the described input transistorized grid that is shifted is connected to the drain electrode of described output transistor; And

One output displacement transistor, described output displacement transistor and described output transistor complementation, described output displacement transistor drain is connected to the drain electrode of described output transistor, and the described output transistorized grid that is shifted is connected to the drain electrode of described input transistors.

9. a buffer unit is used to cushion a transistor-transistor logic (TTL) electronic signal to a CMOS (Complementary Metal Oxide Semiconductor) (CMOS) electronic signal, and this device comprises at least:

One inverter, the complementary transistor that it comprises at least one group of series connection, be used to produce one with first output signal of described TTL signal inversion;

At least one load transistor, the source electrode of described load transistor is connected to described inverter, and the grid of described load transistor links to each other with drain electrode, and one of them the drain electrode of described load transistor is connected to a voltage source; And

One reference shifting-up circuit is used for producing according to described TTL signal and described first output signal one identical with the logic state of described TTL signal and meet second output signal of cmos voltage benchmark, and described reference shifting-up circuit comprises at least:

(a) elm goes into transistor, and its grid is connected to described TTL signal;

(b) output transistor, its grid are connected to described first output signal, and its drain electrode is connected to described second output signal;

(c) an input displacement transistor, described input displacement transistor and described input transistors complementation, described input displacement transistor drain is connected to the drain electrode of described input transistors, and the described input transistorized grid that is shifted is connected to the drain electrode of described output transistor; And

(d) an output displacement transistor, described output displacement transistor and described output transistor complementation, described output displacement transistor drain is connected to the drain electrode of described output transistor, and the described output transistorized grid that is shifted is connected to the drain electrode of described input transistors.

10. buffer unit as claimed in claim 9, the drain electrode of wherein said complementary transistor link to each other and are connected to described first output signal, and the grid of described complementary transistor links to each other and is connected to described ttl signal.

11. buffer unit as claimed in claim 9, the number of wherein said load transistor are one, and the current potential of described voltage source is approximately 3 volts.

12. buffer unit as claimed in claim 9, the number of wherein said load transistor are two, and the current potential of described voltage source is approximately 5 volts.