CN1228710C - Frequency divider in non-integer time - Google Patents

Abstract

The present invention relates to a frequency divider in non-integer time. An input clock signal is used for dividing a non-integral number to provide various clock signals required by a system board. The present invention comprises that a plurality of first edge signals are generated by a first clock signal edge generating circuit according to an input clock, a plurality of second edge signals are generated by a second clock signal edge generating circuit according to an input clock with a phase difference, and a target clock signal is generated by a clock signal composite circuit according to first edge signals and the second edge signals. Because the used input clock signal frequency is low, the difficulty of a designed high frequency phase lock loop is greatly reduced. Because the low frequency phase lock loop has low noise and less consumed power, the outside has small influence to the whole circuit performance.

Description

Frequency divider in non-integer time

Technical field

The present invention relates to a kind of frequency divider in non-integer time, and particularly relate to a kind of with the input clock divided by non-integer to obtain the frequency divider in non-integer time of the required various clocks of circuit board.

Background technology

Because semiconductor technology is significantly progressive, make that the running speed of computing machine in modern age is more and more faster, CPU (central processing unit) (central process unit, CPU) be personal computer (personalcomputer, PC) heart, and clock (clock) be CPU (central processing unit) can normal operation key.Having several different clocks in personal computer simultaneously, is very likely, also is present standard simultaneously, and each clock all has its different purposes.

Wherein foremost clock is the internal clocking of CPU (central processing unit).This is the 266MHz (or 300MHz, 350MHz, 400MHz and 450MHz etc.) that often hears.It has represented the running speed of the fastest assembly in the personal computer.In today, except the CPU (central processing unit) internal core operates with this speed, almost there is not other assembly under this speed, to operate.

Bus from the CPU (central processing unit) to the primary memory (bus), the part with the CPU (central processing unit) clock is operating usually.That is to say that the clock circuit of working control speed is on the motherboard of CPU (central processing unit) outside (motherboard), CPU (central processing unit) is then carried out work with the several times speed synchronization of external clock.

CPU (central processing unit) must just can be connected with the peripheral device in the external world by input/output bus (I/O bus) in motherboard, and general industry construction standard (ISA) input/output bus also can't be to be higher than the speed running of 8.33MHz.This signal be by identical clock 66MHz with primary memory divided by 8 obtain, the ISA clock speed need be with this speed slowly, with the running of guaranteeing that all old ISA expansion boards are can be on up-to-date personal computer correct.

More than one expansion I/O bus that present personal computer is many again, and the speed of these buses is fast more a lot of than isa bus, but still can't compare with the speed of primary memory, in the personal computer of today, peripheral device interconnection (peripheral component interconnection, PCI) bus can operate under the speed of 33MHz, just half of primary memory clock speed or 1/3rd.

All have on the integrated circuit now (IC) phase-locked loop (phase-lock loop, PLL), to provide personal computer required various frequency clocks.Again because the complexity of circuit nowadays, the complexity during operation, the various clocks during operation may not be the relations of integral multiple, for example, may need to use 66MHz, 100MHz, the clock of 133MHz in same the integrated circuit (IC).Using phase-locked loop to produce the interior required various frequency clocks of integrated circuit is most economical methods, just passes through the action of frequency elimination, phase-locked loop is shaken in fixed frequency, and obtain a plurality of clocks outputs.

(Advanced Graphic Port, AGP) in the integrated circuit of 4X pattern, the requirement of clock is from 266MHz supporting advanced drawing port at present.If make with the integer frequency elimination, then phase-locked loop must shake at 800MHz, to obtain 266MHz (800MHz/3=266MHz) simultaneously, 200MHz (800MHz/4), 133MHz (800MHz/6), 100MHz (800MHz/8) and 66MHz (800MHz/12).So will improve the degree of difficulty of design high frequency phase-locked loop, and power consumption can increase also.

Summary of the invention

The invention provides a kind of with input clock signal divided by non-integral frequency divider in non-integer time, phase-locked loop is shaken to obtain the clock of above-mentioned various frequencies at 400MHz, as 266MHz (400MHz/1.5=266MHz), 200MHz (400MHz/2), 133MHz (400MHz/3), 100MHz (400MHz/4) and 66MHz (400MHz/6) etc., greatly reduce the degree of difficulty of design high frequency phase-locked loop, and because of the phase-locked loop noise ratio of low frequency less, the power that consumes is also less, and the usefulness of integrated circuit (performance) is subjected to the degree of ectocine also less.

The invention provides a kind of frequency divider in non-integer time, it comprises that at least three kinds of outputs go into clock, is respectively the input clock and target clock (target clock) signal of input clock, phase shift (phase shift).This kind frequency divider in non-integer time comprises at least: the first clock signal edge (edge) produces circuit, second counting circuit and clock signal combiner circuit.First counting circuit is to produce a plurality of first count signals according to input clock, and it comprises at least: the signals such as falling edge (falling edge) af of the signal A that ring-like counter produced that rising edge (rising edge) ar of the signal A that ring-like counter produced that positive edge triggers and negative edge trigger.

Second counting circuit that this kind frequency divider in non-integer time is included, its output is connected to the clock signal combiner circuit, its input is connected to the input clock of phase shift, this second counting circuit is to produce a plurality of second count signals according to the input phase shifted clock, and it comprises at least: the signals such as negative edge (falling edge) bf of the signal B that ring-like counter produced that rising edge (rising edge) br of the signal B that ring-like counter produced that positive edge triggers and negative edge trigger.

The clock signal combiner circuit that this kind frequency divider in non-integer time is included, its input signal is connected to the output signal of first counting circuit and second counting circuit, it comprises at least: first " XOR " door, be connected to first counting circuit, the rising edge ar of basis signal A and the negative edge bf of signal B produce first work period (duty cycle) signal of target clock; Second " XOR " door, be connected to second counting circuit, the falling edge af of basis signal A and the rising edge br of signal B produce second working period signal of target clock; And OR-gate, be connected to first " XOR " door is with second " XOR " output terminal of door, according to first " XOR " first working period signal and second of door " XOR " second working period signal synthesize target clock signal.

Owing to use a kind of frequency divider in non-integer time of the present invention, the phase-locked loop of motherboard can use lower 400MHz clock signal can obtain the clock of various frequencies, as 266MHz, 200MHz, 133MHz, 100MHz and 66MHz etc., greatly reduce the degree of difficulty of design high frequency phase-locked loop, and less because of the phase-locked loop noise ratio of low frequency, the power of consumption is also less, and the usefulness of integrated circuit (performance) is subjected to the degree of ectocine also less.

According to a preferred embodiment of the present invention, provide a kind of with input clock signal divided by non-integral clock generation circuit, comprising: oscillator, first counting circuit, second counting circuit and clock signal combiner circuit.Wherein oscillator produces a plurality of phase shifted clock signals of input clock signal and same frequency; First counting circuit wherein produces a plurality of first count signals according to input clock signal.Second counting circuit wherein produces a plurality of second count signals according to one of a plurality of phase shifted clock signals.Clock signal combiner circuit wherein is according to a plurality of first count signals of first counting circuit generation and the synthetic target clock signal of a plurality of second count signals of second counting circuit generation.

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:

Description of drawings:

A kind of frequency divider in non-integer time that Fig. 1 illustrates according to a preferred embodiment of the present invention uses oscillator to produce the block diagram of phase shift input clock;

A kind of frequency divider in non-integer time that Fig. 2 illustrates according to a preferred embodiment of the present invention uses phase-shift circuit to produce the block diagram of phase shift input clock;

Fig. 3 illustrates the target clock signal sequential chart according to a kind of frequency divider in non-integer time of a preferred embodiment of the present invention;

Fig. 4 illustrates the wiring schematic diagram according to the oscillator of a kind of frequency divider in non-integer time of a preferred embodiment of the present invention;

The positive edge that Fig. 5 illustrates according to first counting circuit of a kind of frequency divider in non-integer time of a preferred embodiment of the present invention triggers ring-like counter wiring schematic diagram;

Fig. 6 illustrates the sequential chart that triggers a plurality of count signals of ring-like counter according to the positive edge of first counting circuit of a kind of frequency divider in non-integer time of a preferred embodiment of the present invention;

The negative edge that Fig. 7 illustrates according to first counting circuit of a kind of frequency divider in non-integer time of a preferred embodiment of the present invention triggers ring-like counter wiring schematic diagram;

Fig. 8 illustrates the sequential chart that triggers a plurality of count signals of ring-like counter according to the negative edge of first counting circuit of a kind of frequency divider in non-integer time of a preferred embodiment of the present invention;

Fig. 9 illustrates according to first counting circuit of a kind of frequency divider in non-integer time of a preferred embodiment of the present invention and the second counting circuit wiring schematic diagram;

Figure 10 illustrates according to a plurality of count signals of a kind of frequency divider in non-integer time of a preferred embodiment of the present invention and the correlation timing figure of clock signal synthesis circuit;

Figure 11 illustrates the clock signal combiner circuit wiring schematic diagram according to a kind of frequency divider in non-integer time of a preferred embodiment of the present invention; And

Figure 12 illustrates according to a kind of frequency divider in non-integer time of another preferred embodiment of the present invention divided by 4/3 target clock signal sequential chart.

Embodiment

Shown in Figure 1, its a kind of frequency divider in non-integer time that illustrates according to a preferred embodiment of the present invention uses oscillator to produce the block diagram of phase shift input clock.Please refer to Fig. 1, a kind of frequency divider in non-integer time provided by the present invention is the synthetic target clock signal of a plurality of second count signals that a plurality of first count signals that produced according to first counting circuit 15 and second counting circuit 20 are produced.Use this kind frequency divider in non-integer time, the phase-locked loop of motherboard can use lower 400MHz clock signal can obtain the clock of various frequencies, as 266MHz, 200MHz, 133MHz, 100MHz and 66MHz etc., greatly reduce the degree of difficulty of design high frequency phase-locked loop, and less because of the phase-locked loop noise ratio of low frequency, the power of consumption is also less, and the usefulness of integrated circuit (peformance) is subjected to the degree of ectocine also less.

As shown in Figure 1, a kind of frequency divider in non-integer time of the present invention includes oscillator 13, first counting circuit 15, second counting circuit 20 and clock signal synthesis circuit 30.First counting circuit 15 wherein is connected to input clock signal, produces a plurality of first count signals to clock signal combiner circuit 30 via the ring-like counter of edge-triggered.It is identical but have the clock signal of different phase shifts that oscillator 13 wherein produces input clock signals and a plurality of frequency; Second counting circuit 20 is connected to oscillator 13, according to one of a plurality of phase shifted clock signals, produces a plurality of second count signals to clock signal combiner circuit 30 via the ring-like counter of edge-triggered.Clock signal combiner circuit 30 wherein is connected to first counting circuit 15 and second counting circuit 20, via " XOR " door and the synthetic target clock signal of OR-gate.

As shown in Figure 2, it illustrates a kind of frequency divider in non-integer time of the present invention and uses phase-shift circuit to produce the block diagram of phase shift input clock, includes phase-shift circuit 14, first counting circuit 15, second counting circuit 20 and clock signal synthesis circuit 30.First counting circuit 15 wherein is connected to input clock signal, produces a plurality of first count signals to clock signal combiner circuit 30 via the ring-like counter of edge-triggered.Phase-shift circuit 14 wherein produces the clock signal of various phase shifts according to input clock signal; Second counting circuit 20 is connected to phase-shift circuit 14, according to the input clock signal of phase shift, produces a plurality of second count signals to clock signal combiner circuit 30 via the ring-like counter of edge-triggered.Clock signal combiner circuit 30 wherein is connected to first counting circuit 15 and second counting circuit 20, via " XOR " door (XOR) and the synthetic target clock signal of OR-gate (OR).

Shown in Figure 3, it illustrates the target clock signal sequential chart according to a kind of frequency divider in non-integer time of a preferred embodiment of the present invention.Please refer to Fig. 3, a kind of frequency divider in non-integer time provided by the present invention is to be that frequency is that 400MHz input clock signal synthetic one-period of the input clock signal of 400MHz and phase shift 90 degree is to be that frequency is the target clock signal of 266MHz 3.75 nanoseconds (ns) 2.5 nanoseconds (ns) according to the cycle.

Shown in Figure 4, it illustrates the block diagram according to the oscillator of a kind of frequency divider in non-integer time of a preferred embodiment of the present invention.It comprises a plurality of phase inverters, each phase inverter all has the basic phase shift of 180 degree and adds desired phase shift, for example, 4 phase inverters 131 are arranged among Fig. 3,132,133,134, each phase inverter provides the phase shift of 180 degree, always has the phase shift of 720 degree, as desires to reach the purpose of vibration, then total phase shift is necessary for the multiple of 360 degree, therefore total phase shift is 1080 degree (720 degree are inapplicable), deducts 720 of 4 phase inverters and is outside one's consideration, and each phase inverter must provide the phase shift of 90 degree just can reach the purpose of vibration again.If the phase shifts of desiring to provide 60 degree, 120 degree then this oscillator 13 must have 3 phase inverters to be serially connected, 3 phase inverters provide the phase shift of 540 degree, 180 remaining degree are then respectively provided the phase shift of 60 degree by each phase inverter, therefore can obtain phase shift 60 degree clock signals at the output terminal of first phase inverter, obtain phase shift 120 degree clock signals at the output terminal of second phase inverter.

The positive edge that Fig. 5 illustrates according to first counting circuit of a kind of frequency divider in non-integer time of a preferred embodiment of the present invention triggers ring-like counter wiring schematic diagram; Please refer to Fig. 5, it is the partial circuit of first counting circuit that this positive edge triggers ring-like counter 16, trigger D flip-flops 161,162 and 163 and phase inverter 164 comprising 3 positive edge, originally be divided by 3 circuit, but, trigger 163 triggers D flip-flop 161 because being fed back to the 1st positive edge via phase inverter 164, therefore just can be again behind 6 clocks from newly beginning next positive period, so it becomes one divided by 6 circuit.Please cooperate with reference to Fig. 6, the output terminal of all D flip-flops is all electronegative potential when initial, the output terminal that triggers D flip-flop 161 at the 1st positive edge when the 1st clock signal of input can obtain the noble potential value, the output terminal of the 2nd positive edge triggering D flip-flop 162 can obtain the noble potential value when next clock signal, the output terminal that the 3rd positive edge triggers D flip-flop 163 during next again clock signal can obtain the noble potential value, become electronegative potential through trigger 164 after oppositely, therefore need be through just obtaining the output of noble potential after 3 clock signals again, so can obtain input clock signal divided by 6 clock signal.

Shown in Figure 7, its negative edge that illustrates according to first counting circuit of a kind of frequency divider in non-integer time of a preferred embodiment of the present invention triggers ring-like counter wiring schematic diagram; Please refer to Fig. 7, it is the partial circuit of first counting circuit that this negative edge triggers ring-like counter 17, trigger D flip-flops 171,172 and 173 and phase inverter 174 comprising 3 negative edge, wherein the normal state output terminal (Q) of the 3rd negative edge triggering D flip-flop 173 is fed back to the 1st positive edge via phase inverter 174 and triggers D flip-flop 171, and it also is the circuit divided by 6 as mentioned above.Please cooperate with reference to Fig. 8, the output terminal of all D flip-flops is all electronegative potential when initial, can obtain the noble potential value during falling edge of the output terminal that triggers D flip-flop 171 at the 1st negative edge during the 1st clock signal when input at input clock signal, the output terminal of the 2nd positive edge triggering D flip-flop 172 can obtain the noble potential value when the falling edge of input clock signal when next clock signal, the output terminal that the 3rd positive edge triggers D flip-flop 173 during next again clock signal can obtain the noble potential value when the falling edge of input clock signal, after phase inverter 174 is anti-phase, become electronegative potential, therefore need so can obtain with input clock signal phase shift 180 degree and divided by 6 clock signal through the output that just can obtain noble potential after 3 clock signals again.

Shown in Figure 9, it illustrates according to first counting circuit of a kind of frequency divider in non-integer time of a preferred embodiment of the present invention and the second counting circuit wiring schematic diagram; Please refer to Fig. 9, wherein first counting circuit 15 comprises that positive edge triggers ring-like counter 16 and negative edge triggers ring-like counter 17.Second counting circuit 20 wherein comprises that positive edge triggers ring-like counter 21 and negative edge triggers ring-like counter 22, and wherein positive edge triggers that principle of work that ring-like counter 21 and negative edge trigger ring-like counter 22 triggers ring-like counter 16 with the correlation timing signal that is produced with above-mentioned positive edge and negative edge triggers ring-like counter 17.

Shown in Figure 10, it illustrates according to a plurality of count signals of a kind of frequency divider in non-integer time of a preferred embodiment of the present invention and the correlation timing figure of clock signal synthesis circuit.Please refer to Figure 10, wherein signal A is the input clock signal of 400MHz, and signal B is the 400MHz input clock signal by phase shift 90 degree of oscillator 13 or phase-shift circuit 14 outputs.A plurality of count signals wherein comprise output signal ar, the output signal af of D flip-flop 172, the output signal br of D flip-flop 213 and the output signal bf of D flip-flop 221 of D flip-flop 161.The output signal ar of above-mentioned D flip-flop 161 and the output signal bf of D flip-flop 221 are inputed to " XOR " 31 first working period signal with generation 400MHz/1.5=266MHz target clock signal.

Shown in Figure 11, it illustrates the clock signal combiner circuit wiring schematic diagram according to a kind of frequency divider in non-integer time of a preferred embodiment of the present invention.Please refer to Figure 11, the output signal af of the D flip-flop among Fig. 9 172 and the output signal br of D flip-flop 213 inputed to " XOR " 32 second working period signal with generation 400MHz/1.5=266MHz target clock signal.First above-mentioned working period signal and second working period signal are connected to OR-gate 33 can obtain target clock signal divided by 1.5 266MHz.

Shown in Figure 12, its illustrate another kind of frequency divider in non-integer time of the present invention with input clock signal divided by 4/3 sequential chart.Desire divided by 4/3, that is obtains 3 target clock signal cycles at 4 input clock signals with input clock signal in the cycle, so its ring-like counter that need have 4 triggers is to obtain the clock signal divided by 4; Other needs oscillator 13 or phase-shift circuit 14 that the phase shifted clock signal of phase shift 60 degree and 120 degree is provided.As previously mentioned, the oscillator 13 that this provides the phase shifted clock signal of phase shift 60 degree and 120 degree needs 3 phase inverters to form, so that required phase shifted clock signal to be provided.Need one in addition by 3 " XOR " a clock signal combiner circuit of being formed 30, first working period signal that a plurality of count signals that clock signal produced of spending according to input clock signal and phase shift 60 synthesize target clock signal.The 3rd working period signal that a plurality of count signals that clock signal produced of second working period signal of the synthetic target clock signal of a plurality of count signals that clock signal produced of input clock signal and phase shift 120 degree and the clock signal of phase shift 60 degree and phase shift 120 degree synthesize target clock signal.So can be with input clock signal divided by non-integer 4/3, to obtain required target clock.

Can learn by above-mentioned two embodiment, a kind of frequency divider in non-integer time that this case provided, be converted to target clock signal in order to a plurality of input clock signals that frequency is identical, the m of these an input clock signals cycle equal this target clock signal n cycle (for example among first embodiment divided by 3/2, m=3 then, n=2), wherein n and m are positive integer and the m＞n greater than 0, the phase differential of these input clock signals is that the integral multiple of 360 °/2n (for example needs 90 degree phase shifts among first embodiment, because of n=2, so the 360/4=90 degree), this frequency divider in non-integer time comprises: a plurality of counting circuits, produce a plurality of count signals according to a plurality of input clock signals, the cycle of these count signals equals 2m the cycle of these input clock signals, and the rising edge of any these count signal and falling edge are synchronized with one of them rising edge and falling edge of these input clock signals; And the clock signal combiner circuit, be coupled to a plurality of counting circuits, in order to synthesize target clock signal according to a plurality of count signals.

Wherein the clock signal combiner circuit comprises: n " XOR " door, be coupled to a plurality of counting circuits, in order to produce n working period signal; And an OR-gate, have n input end, be coupled to a plurality of working period signal, with synthetic this target clock signal.

A plurality of counting circuits wherein comprise that a plurality of positive edge trigger ring-like counter and a plurality of negative edge triggers ring-like counter.Wherein these a plurality of positive edge trigger ring-like counter and comprise: phase inverter; And m D flip-flop, these D flip-flops are positive edge triggered flip-flop, and its input end of clock is connected in parallel to one of a plurality of input clock signals, the Q output terminal of these a plurality of D flip-flops is connected in series to the D input end of the D flip-flop of next stage, the Q output terminal of the D flip-flop of afterbody is coupled to the input end of phase inverter, and the output terminal of this phase inverter is coupled to the D input end of the D flip-flop of the first order.

Wherein a plurality of negative edge trigger ring-like counter and comprise: phase inverter; And m D flip-flop, these D flip-flops are negative edge triggered flip-flop, and its input end of clock is connected in parallel to one of a plurality of input clock signals, the Q output terminal of these D flip-flops is connected in series to the D input end of the D flip-flop of next stage, the Q output terminal of the D flip-flop of afterbody is coupled to the input end of phase inverter, and the output terminal of this phase inverter is coupled to the D input end of the D flip-flop of the first order.

In sum, of the present invention a kind of with input clock signal divided by having following advantage and effect under non-integral clock generation circuit and the known art at least:

Therefore known technology if will obtain the clock signal of 266MHz, then need use the 800MHz clock signal of upper frequency because use the integer frequency eliminator.And according to a kind of frequency divider in non-integer time of the present invention, its clock signal 400MHz that can use lower frequency is divided by a non-integer, for example be 1.5, to obtain the required various clock signals of motherboard, as 266MHz, 200MHz, 133MHz, 100MHz and 66MHz etc., so greatly reduce the degree of difficulty of design high frequency phase-locked loop, and because of the phase-locked loop noise ratio of low frequency less, the power that consumes is also less, and the usefulness of integrated circuit (performance) is subjected to the degree of ectocine also less.

In sum; though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the claim person of defining of the present invention.

Claims (16)

1. frequency divider in non-integer time, be converted to a target clock signal in order to a plurality of input clock signals that frequency is identical, the m of these an input clock signals cycle equals n the cycle of this target clock signal, wherein n and m are positive integer and the m＞n greater than 0, the phase differential of these input clock signals is the integral multiple of 360 °/2n, it is characterized in that this frequency divider in non-integer time comprises:

A plurality of counting circuits, in order to produce a plurality of count signals according to these input clock signals, the cycle of these count signals equals 2m the cycle of these input clock signals, and the rising edge of any these count signal and falling edge are synchronized with one of them rising edge and falling edge of these input clock signals; And

One clock signal synthesis circuit is coupled to these counting circuits, in order to synthesize this target clock signal according to these count signals.

2. frequency divider in non-integer time as claimed in claim 1 is characterized in that, this clock signal combiner circuit comprises:

N partial sum gate is coupled to these counting circuits, in order to produce n working period signal; And

One OR-gate has n input end, is coupled to these working period signal, with synthetic this target clock signal.

3. frequency divider in non-integer time as claimed in claim 1 is characterized in that, these counting circuits comprise that a plurality of positive edge trigger ring-like counter and a plurality of negative edge triggers ring-like counter.

4. frequency divider in non-integer time as claimed in claim 3 is characterized in that, these positive edge trigger ring-like counter and comprise:

One phase inverter; And

M D flip-flop, these D flip-flops are positive edge triggered flip-flop, and its input end of clock is connected in parallel to one of these input clock signals, the Q output terminal of the positive edge D flip-flop of upper level is connected in series to the D input end of the positive edge D flip-flop of next stage, the Q output terminal of the D flip-flop of afterbody is coupled to the input end of this phase inverter, and the output terminal of this phase inverter is coupled to the D input end of the D flip-flop of the first order.

5. frequency divider in non-integer time as claimed in claim 3 is characterized in that, these negative edge trigger ring-like counter and comprise:

One phase inverter; And

M D flip-flop, these D flip-flops are negative edge triggered flip-flop, and its input end of clock is connected in parallel to one of these input clock signals, the Q output terminal of the negative edge D flip-flop of upper level is connected in series to the D input end of the negative edge D flip-flop of next stage, the Q output terminal of the D flip-flop of afterbody is coupled to the input end of this phase inverter, and the output terminal of this phase inverter is coupled to the D input end of the D flip-flop of the first order.

6. frequency divider in non-integer time, in order to an input clock signal is converted to a target clock signal, 3 cycles of this input clock signal equal 2 cycles of this target clock signal, it is characterized in that this frequency divider in non-integer time comprises:

One phase-shift circuit produces a required phase shift 90 degree clock signals according to this input clock signal;

One first counting circuit produces a plurality of first count signals according to this input clock signal;

One second counting circuit produces a plurality of second count signals according to these phase shift 90 degree clock signals; And

One clock signal synthesis circuit is coupled to this first and second counting circuit, according to synthetic this target clock signal of these first and second count signals.

7. frequency divider in non-integer time as claimed in claim 6, it is characterized in that, this first counting circuit comprises that one first positive edge triggers ring-like counter and one first negative edge triggers ring-like counter, and this second counting circuit comprises that one second positive edge triggers ring-like counter and one second negative edge triggers ring-like counter.

8. frequency divider in non-integer time as claimed in claim 7 is characterized in that, this first positive edge triggers ring-like counter and this second positive edge and triggers ring-like counter and comprise:

One phase inverter; And

3 D flip-flops, these D flip-flops are positive edge triggered flip-flop, and its input end of clock is connected in parallel, the input end of clock that this first positive edge triggers ring-like counter is connected to this input clock, and the input end of clock that this second positive edge triggers ring-like counter is connected to this phase shift 90 degree clock signals, the Q output terminal of the positive edge D flip-flop of upper level is connected in series to the D input end of the positive edge D flip-flop of next stage, the Q output terminal of the D flip-flop of afterbody is coupled to the input end of this phase inverter, and the output terminal of this phase inverter is coupled to the D input end of the D flip-flop of the first order.

9. frequency divider in non-integer time as claimed in claim 7 is characterized in that, this first negative edge triggers ring-like counter and this second negative edge and triggers ring-like counter and comprise:

One phase inverter; And

3 D flip-flops, these D flip-flops are negative edge triggered flip-flop, and its input end of clock is connected in parallel, the input end of clock that this first negative edge triggers ring-like counter is connected to this input clock, and the input end of clock that this second negative edge triggers ring-like counter is connected to this phase shift 90 degree clock signals, the Q output terminal of the negative edge D flip-flop of upper level is connected in series to the D input end of the negative edge D flip-flop of next stage, the Q output terminal of the D flip-flop of afterbody is coupled to the input end of this phase inverter, and the output terminal of this phase inverter is coupled to the D input end of the D flip-flop of the first order.

10. frequency divider in non-integer time as claimed in claim 6 is characterized in that, this clock signal combiner circuit comprises:

One first " XOR " door, be coupled to this first counting circuit, this second counting circuit, according to one first working period signal of synthetic this target clock signal of these first and second count signals;

One second " XOR " door, be coupled to this first counting circuit, this second counting circuit, according to one second working period signal of synthetic this target clock signal of these first and second count signals; And

One OR-gate, be coupled to this first and second " XOR " door, according to synthetic this target clock signal of this first working period signal and second working period signal.

11. frequency divider in non-integer time, in order to spend clock signals with an input clock mark of oscillator output and with a phase shift 90 of these input clock signal phase differential 90 degree, be converted to a target clock signal, 3 cycles of this input clock signal equal 2 cycles of this target clock signal, it is characterized in that this frequency divider in non-integer time comprises:

One first counting circuit produces a plurality of first count signals according to this input clock signal;

One second counting circuit produces a plurality of second count signals according to these phase shift 90 degree clock signals; And

One clock signal synthesis circuit is coupled to this first and second counting circuit, according to synthetic this target clock signal of these first and second count signals.

12. frequency divider in non-integer time as claimed in claim 11 is characterized in that, this oscillator is connected in series institute mutually by a plurality of phase inverters to be formed, and the output terminal of last phase inverter of these phase inverters is feedback again to the input end of first phase inverter.

13. frequency divider in non-integer time as claimed in claim 11, it is characterized in that, this first counting circuit comprises that one first positive edge triggers ring-like counter and one first negative edge triggers ring-like counter, and this second counting circuit comprises that one second positive edge triggers ring-like counter and one second negative edge triggers ring-like counter.

14. frequency divider in non-integer time as claimed in claim 13 is characterized in that, this first positive edge triggers ring-like counter and this second positive edge and triggers ring-like counter and comprise:

One phase inverter; And

3 D flip-flops, these D flip-flops are positive edge triggered flip-flop, and its input end of clock is connected in parallel, the input end of clock that this first positive edge triggers ring-like counter is connected to this input clock, and the input end of clock that this second positive edge triggers ring-like counter is connected to this phase shift 90 degree clock signals, the Q output terminal of the positive edge D flip-flop of upper level is connected in series to the D input end of the positive edge D flip-flop of next stage, the Q output terminal of the D flip-flop of afterbody is coupled to the input end of this phase inverter, and the output terminal of this phase inverter is coupled to the D input end of the D flip-flop of the first order.

15. frequency divider in non-integer time as claimed in claim 13 is characterized in that, this first negative edge triggers ring-like counter and this second negative edge and triggers ring-like counter and comprise:

One phase inverter; And

3 D flip-flops, these D flip-flops are negative edge triggered flip-flop, and its input end of clock is connected in parallel, the input end of clock that this first negative edge triggers ring-like counter is connected to this input clock, and the input end of clock that this second negative edge triggers ring-like counter is connected to this phase shift 90 degree clock signals, the Q output terminal of the negative edge D flip-flop of upper level is connected in series to the D input end of the negative edge D flip-flop of next stage, the Q output terminal of the D flip-flop of afterbody is coupled to the input end of this phase inverter, and the output terminal of this phase inverter is coupled to the D input end of the D flip-flop of the first order.

16. frequency divider in non-integer time as claimed in claim 11 is characterized in that, this clock signal combiner circuit comprises:

One first " XOR " door, be coupled to this first counting circuit, this second counting circuit, according to one first working period signal of synthetic this target clock signal of these first and second count signals;

One second " XOR " door, be coupled to this first counting circuit, this second counting circuit, according to one second working period signal of synthetic this target clock signal of these first and second count signals; And

One OR-gate, be coupled to this first and second " XOR " door, according to synthetic this target clock signal of this first working period signal and second working period signal.

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