CN1225784C - Ballgrid array parkaging body - Google Patents
Ballgrid array parkaging body Download PDFInfo
- Publication number
- CN1225784C CN1225784C CN 03101578 CN03101578A CN1225784C CN 1225784 C CN1225784 C CN 1225784C CN 03101578 CN03101578 CN 03101578 CN 03101578 A CN03101578 A CN 03101578A CN 1225784 C CN1225784 C CN 1225784C
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- China
- Prior art keywords
- grid array
- package body
- chip
- array package
- spherical grid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48233—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a potential ring of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Connecting Device With Holders (AREA)
- Tests Of Electronic Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The present invention discloses a leading wire bonding ball grid array package body which is characterized in that a power ring which is arranged on a basal plate and corresponds to a core circuit of a chip is arranged at the power ring inner side of an input/output circuit which corresponds to the chip; therefore, when the chip is changed into an inverted package mode from a leading wire package mode, corresponding power pins can be applicable to a circuit board which is originally used for assembling the leading wire bonding ball grid array package body. Besides, the present invention also discloses an inverted bonding ball grid array package body which is characterized in that a basal plate power ring which is arranged on a basal plate and corresponds to a core circuit of a chip is arranged at the power ring outer side of an input/output circuit which corresponds to the chip; therefore, when the chip is changed into a leading wire package mode from an inverted package mode, corresponding power pins can be applicable to a circuit board which is originally used for assembling the leading wire bonding ball grid array package body.
Description
Technical field
The present invention relates to a kind of spherical grid array package body, relate to the spherical grid array package body that a kind of available same power pin is disposed at lead packages and reviewing encapsulation especially.
Background technology
In the information-intensive society in modern times, by microprocessor system that integrated circuit constituted already by widespread each aspect in life.The electrical home appliances of every automation, mobile communication equipment, PC do not have the trace of invisible integrated circuit, and the main body of integrated circuit, the chip (die) that utilizes existing semiconductor technology to produce exactly.Making the process of chip, is by producing a wafer (wafer) beginning, marking off a plurality of zones on a wafer, and on each zone, utilize semiconductor technology to form various circuit, last, again each zone cutting on the wafer is formed each chip.After obtaining chip, also must pass through certain mode, chip is electrically connected to a circuit board, as a printed circuit board (PCB) (printed circuit board, PCB), like this, chip just can obtain required operating voltage to carry out a predetermined operation by this circuit board, for instance, this chip is a coding circuit (encodercircuit), after the required voltage of this coding circuit work was provided, this chip can be at the data-signal that this circuit board the is imported computing of encoding, and last outupt coded signal is to this circuit board.Generally speaking, the mode that chip is electrically connected to circuit board can be nude film (bare chip) collocation method that chip directly is electrically connected to circuit board, or after chip is packaged in a packaging body (package) earlier, be electrically connected to circuit board to receive power supply and transmission signals by the circuit in the packaging body again.
The major function of packaging body is to provide signal transmission interface and the protection chip between chip and the circuit board; in addition; because at present electronic product is gradually towards the trend development of compact and high arithmetic speed; therefore cause the desired I/O pin count of packaging body (package pin count) also to increase thereupon; thickness must be more and more thinner simultaneously; and area also must be more and more littler; adopt pin to insert (pin through hole in the past; PTH) encapsulation technology is owing to be subjected to the size restriction of corresponding patchhole on the circuit board; therefore the size of packaging body can't be dwindled further; and the I/O pin count also is restricted simultaneously; so surface encapsulation (surface mount technology; SMT) encapsulation technology just replaces the encapsulation technology of this pin insertion gradually to reduce the size of packaging body; yet the encapsulation technology that above-mentioned pin inserts with surface encapsulation all belongs to the packaged type that periphery is arranged (peripheral), therefore still has its restriction of the sky earlier in the increase of the reduction of packaging body volume and I/O pin count.For instance, encapsulation technology for surface encapsulation, when the pin count of periphery arrangement increases, correspondingly, distance between the adjacent pin (pitch) also shortens thereupon, therefore when being installed on circuit board, packaging body can cause packaging qualification rate not good because the distance between the adjacent pin is too short, so the encapsulation technology of face matrix form (areaarray) is just arisen at the historic moment, sphere grid array (ball grid array for example, BGA) packaging body, it is because the I/O pin is converted to face arranged mode by peripheral arrangement mode, distance between the not only adjacent pin can enlarge the packaging qualification rate when improving packaging body and be installed in circuit board, and the pin count of I/O simultaneously also can significantly increase.According to the electric connection mode of chip, spherical grid array package body mainly can be divided into wire-bonded (wire bonding) spherical grid array package body and engage spherical grid array package body with reviewing (flip chip).
See also Fig. 1, Fig. 1 is first schematic diagram of existing wire-bonded spherical grid array package body 10.Wire-bonded spherical grid array package body 10 includes a chip (die) 11, and a substrate (substrate) 12.Chip 11 includes a core circuit (core circuit) 13 and is used for carrying out a predetermined operation, a plurality of input/output circuitry 14a, 14b, 14c are used for controlling each signal input and this core circuit 13 of output, and a plurality of weld pad (bonding pad) 18 is used for being electrically connected chip 11 and substrate 12.Substrate 12 is provided with a plurality of power rings (power ring) 20a, 20b, 20c, 20d are used to provide different operating voltages respectively, and a plurality of pads 22, and power ring 20a, 20b, 20c, 20d and pad 22 are arranged on same first wiring layer 28.For instance, when packaging body 10 is the north bridge chips (north bridge chip) of a computer system, 11 of chips are the signal transmission that is used for controlling between a high-speed peripheral device (for example memory and display card) and the microprocessor, promptly carry out above-mentioned functions by core circuit 13, in addition, input/output circuitry 14a, 14b, 14c then is used for controlling a memory respectively, signal between one display card and a microprocessor and the core circuit 13 receives and transmits, because memory, display card, and the operating voltage of microprocessor and inconsistent, for example the operating voltage of memory is 2.6 volts, display card uses accelerated graphics port (accelerated graphics port, AGP) and it need use 1.5 volts of operating voltages, and the operating voltage of microprocessor is 1.2 volts, also be that on behalf of accurate position of high logic " 1 " and earthed voltage, memory represent the low accurate position of logic " 0 " with 2.6 volts, therefore corresponding input/output circuitry 14a also must use 2.6 volts to come as its operating voltage so that judge rightly and determine the logic standard of signal, and successfully sends a signal to the signal that memory and reception memorizer are exported.Similarly, input/output circuitry 14b also must use 1.5 volts to come as its operating voltage to judge and the accurate position of the logic of decision signal, and correctly send a signal to display card and receive the signal that display card is exported, and input/output circuitry 14c also must use 1.2 volts to come as its operating voltage judging and the accurate position of the logic of decision signal, and correctly sends a signal to microprocessor and receive the signal that microprocessor is exported.In addition, the operating voltage of core circuit 13 also may be different with input/output circuitry 14a, 14b, 14c, therefore must provide its required operating voltage (for example 2.5 volts) by substrate 12.Power ring 20a, 20b, 20c, 20d are the operating voltages that is used to provide input/output circuitry 14a, 14b, 14c and core circuit 13 respectively, please note, weld pad 18 can be used to transmission signals and transmits power supply corresponding to input/output circuitry 14a, 14b, 14c and core circuit 13.In Fig. 1, sealing wire 16a, 16b, 16c, 16d be used for connecting weld pad 18 and power ring 20a, 20b, 20c, 20d with input voltage respectively to input/output circuitry 14a, 14b, 14c and core circuit 13, in addition, sealing wire 16e connection weld pad 18 and pad 22 are to be used for transmission signals, for ease of explanation, Fig. 1 and not shown all sealing wire are connected with pad (sloder joint) 22.So, utilizing the auxiliary of sealing wire 16a, 16b, 16c, 16d, 16e, chip 11 can obtain required operating voltage from substrate 12, and can transmit signal mutually between chip 11 and the substrate 12.
See also Fig. 2 and Fig. 3, Fig. 2 is second schematic diagram of wire-bonded spherical grid array package body 10 shown in Figure 1, and Fig. 3 is wire-bonded spherical grid array package body 10 a shown in Figure 1 sectional view along tangent line 3-3 '.Packaging body 10 includes a plurality of pins 24, it is that mode with matrix is arranged on one second wiring layer 30, wherein include a plurality of conductive area 26a, 26b, 26c, 26d on this second wiring layer 30, pin 24 on each conductive area 26a, 26b, 26c, the 26d is used for connecting a circuit board respectively with to input/output circuitry 14a, 14b, 14c and core circuit 13 supply powers, as shown in Figure 3, first wiring layer 28 and second wiring layer 30 are separately positioned on the two-layer up and down of wire-bonded spherical grid array package body 10.Please note, Fig. 1 and Fig. 2 are vertical view, so conductive area 26a, 26b, 26c, 26d and corresponding power ring 20a, 20b, 20c, be interconnected between the 20d by through hole (via) 32, so when packaging body 10 is installed in a circuit board via its bottom solder ball (solder ball) 34, pin 24 that should solder ball just is electrically connected to this circuit board, therefore when importing a voltage by this circuit board, this voltage is then via solder ball 34, pin 24, through hole 32, power ring 20a, 20b, 20c, 20d, sealing wire 16a, 16b, 16c, 16d, and weld pad 18 and drive input/output circuitry 14a respectively, 14b, 14c and core circuit 13, similarly, when importing a signal by this circuit board, this signal is then via solder ball 34, pin 24, through hole 32, pad 22, sealing wire 16e, and weld pad 18 and input to input/output circuitry 14a, 14b, 14c, and by input/output circuitry 14a, 14b, when 14c exports a signal, this signal is then via weld pad 18, sealing wire 16e, pad 22, through hole 32, pin 24, and solder ball 34 and export this circuit board to.
See also Fig. 4, Fig. 5 and Fig. 6, Fig. 4 engages first schematic diagram of spherical grid array package body 40 for existing reviewing, and Fig. 5 be second schematic diagram that reviewing shown in Figure 4 engages spherical grid array package body 40, and Fig. 6 is reviewing joint spherical grid array package body 40 a shown in Figure 4 sectional view along tangent line 6-6 '.Reviewing engages spherical grid array package body 40 and includes a chip 41 and a substrate 42, this chip 41 includes a core circuit 43 and a plurality of input/output circuitry 44a, 44b, 44c, substrate 42 is provided with a plurality of power ring 50a, 50b, 50c, 50d, be used to provide different operating voltages respectively, and power ring 50a, 50b, 50c, 50d are arranged on same first wiring layer 58.Core circuit 43, input/output circuitry 44a, 44b, 44c, and the work of power ring 50a, 50b, 50c, 50d is identical with the element of the same name of above-mentioned wire-bonded spherical grid array package body 10, therefore no longer repeats to give unnecessary details.Packaging body 40 includes a plurality of pins 54 as shown in Figure 5, it is that mode with matrix is arranged on one second wiring layer 60, wherein this second wiring layer 60 includes a plurality of conductive area 56a, 56b, 56c, 56d, and the pin 54 on each conductive area 56a, 56b, 56c, the 56d is to be used for connecting a circuit board respectively to import the operating voltage of this input/output circuitry 44a, 44b, 44c and core circuit 43.Reviewing engages that the topmost different chips 41 that are are the states after chip 11 (as shown in Figure 1) reverses between spherical grid array package body 40 and the wire-bonded spherical grid array package body 10, it is the upper surface that weld pad 18 (as shown in Figure 3) on the chip 11 is positioned at chip 11, and the weld pad 48 (as shown in Figure 6) on the chip 41 is positioned at the lower surface of chip 41, and form metal coupling (bump) 66 on this weld pad 48, for example Solder Bumps (solder bump) or golden projection (gold bump) are so that be connected with weld pad 68 on first wiring layer 58 of substrate 42.In addition, power ring 50a, 50b, 50c, 50d all is connected one the 3rd wiring layer 70 via through hole (via) 62 with weld pad 68 (that is first wiring layer 58), and by suitably wiring (trace) on the 3rd wiring layer 70, make power ring 50a, 50b, 50c, 50d can give core circuit 43 and input/output circuitry 44a via corresponding weld pad 68 output services voltages, 44b, 44c, similarly, the 3rd wiring layer 70 also is electrically connected mutually via through hole 62 with second wiring layer 60, therefore, pin 62 can be used to transmission signals and power supply to chip 41, as wire-bonded spherical grid array package body 10, reviewing engages spherical grid array package body 40 and also uses tin shot 64 to connect this circuit board.
See also Fig. 1 and Fig. 4, wire-bonded spherical grid array package body 10 engages spherical grid array package body 40 corresponding different power rings configurations with reviewing, with wire-bonded spherical grid array package body 10, corresponding input/output circuitry 14a, 14b, the power ring 20a of 14c, 20b, 20c is arranged on the inboard of the power ring 20d of corresponding core circuit 13, on the contrary, for reviewing engages spherical grid array package body 40, corresponding input/output circuitry 44a, 44b, the power ring 50a of 44c, 50b, 50c is arranged on the outside of the power ring 50d of corresponding core circuit 43, therefore cause wire-bonded spherical grid array package body 10 and reviewing to engage the corresponding different position configuration of power pin (as Fig. 2 and shown in Figure 5) of spherical grid array package body 40, in other words, when the chip of same function uses different encapsulation technologies and when corresponding wire-bonded spherical grid array package body 10 engages the structure of spherical grid array package body 40 with reviewing respectively, because the power supply pin configuration is different, package lead joint spherical grid array package body 10 engages spherical grid array package body 40 with reviewing so must use different circuit board (having different circuit layouts) to come respectively.When encapsulation technology changes, for example change into reviewing and engage spherical grid array package body 40 by wire-bonded spherical grid array package body 10, because the configuration of pin position is incompatible each other, so causing reviewing to engage spherical grid array package body 40 can't be applied to originally be applicable on the circuit board of wire-bonded spherical grid array package body 10, if the circuit board supplier changes the design of circuit board and engages the cost raising that 40 of spherical grid array package bodies can make the circuit board supplier with the assembling reviewing, on the contrary, if the circuit board supplier does not change the design of original circuit board, because the reviewing that the packaging body supplier is produced engages spherical grid array package body 40 and can't be used by buying, packaging body supplier's production cost is improved.
Summary of the invention
Therefore main task of the present invention is to provide the wire-bonded spherical grid array package body of corresponding same power pin configuration to engage spherical grid array package body with reviewing, to address the above problem.
For this reason, the invention provides a kind of wire-bonded spherical grid array package body with power supply pin of reviewing packaged type, it includes: one has the substrate of a first surface and a second surface, it includes: one first power ring, be arranged on the first surface of a substrate, be used for transmitting one first operating voltage; One second source ring is arranged on the first surface of this substrate, is used for transmitting one second operating voltage; A plurality of first pins are used for assembling the circuit board of this spherical grid array package body, import this first operating voltage by this circuit board, and these a plurality of first pins are set on this second surface of this substrate, and are electrically connected this first power ring; And a plurality of second pins, be used for assembling the circuit board of this spherical grid array package body, import this second operating voltage by this circuit board, these a plurality of second pins are set on the second surface of this substrate, and are electrically connected this second source ring; And a chip, being arranged on the first surface of this substrate, it includes: a core circuit is used for carrying out a predetermined operation; With at least one input/output circuitry, be electrically connected this core circuit, be used for control signal input and this core circuit of output; And wherein, this first power ring and this second source ring are soldered to the I/O circuit of core circuit and chip respectively; Wherein this first power ring is set between this second source ring and this chip; Wherein be set at inboard corresponding to second pin of second source ring corresponding to first pin of first power ring.
The present invention also provides a kind of wire-bonded spherical grid array package body with power supply pin of reviewing packaged type, it includes: one has the substrate of a first surface and a second surface, it includes: one first power ring, be arranged on the first surface of a substrate, be used for transmitting one first operating voltage; One second source ring is arranged on the first surface of this substrate, is used for transmitting one second operating voltage; A plurality of first pins are used for assembling the circuit board of this spherical grid array package body, import this first operating voltage by this circuit board, and these a plurality of first pins are arranged on the second surface of this substrate, and are electrically connected this first power ring; A plurality of second pins are used for assembling the circuit board of this spherical grid array package body, import this second operating voltage by this circuit board, and these a plurality of second pins are arranged on the second surface of this substrate, and are electrically connected this second source ring; And a chip, it includes: a core circuit is used for carrying out a predetermined operation; At least one input/output circuitry is electrically connected this core circuit, is used for control signal input and this core circuit of output; And wherein, this first power ring and this second source ring are soldered to the I/O circuit of core circuit and chip respectively; Wherein this second source ring is arranged on the inboard of this first power ring; Wherein be set at inboard corresponding to first pin of first power ring corresponding to second pin of second source ring.
(it includes a substrate (substrate) and a chip (die) for ball grid array, BGA) packaging body (package) to the invention provides a kind of sphere grid array.This substrate includes one first power ring (first power ring), is arranged on first wiring layer of this substrate, is used for transmitting one first operating voltage; One second source ring (second power ring) is arranged on this first wiring layer, is used for transmitting one second operating voltage; A plurality of first pins (first ballout), be used for assembling the circuit board of this spherical grid array package body to import this first operating voltage by this circuit board, these a plurality of first pins are arranged on first conductive area of second wiring layer of this substrate, and this first conductive area is electrically connected this first power ring via at least one first through hole (first via); And a plurality of second pins (secondballout), be used for assembling the circuit board of this spherical grid array package body to import this second operating voltage by this circuit board, these a plurality of second pins are arranged on second conductive area of this second wiring layer, and this second conductive area is electrically connected this second source ring via at least one second through hole (second via).This chip is arranged on first wiring layer of this substrate, and it includes a core circuit (core circuit), is used for carrying out a predetermined operation; (input/output circuit I/Ocircuit), is electrically connected this core circuit at least one input/output circuitry, is used for control signal input and this core circuit of output; And a plurality of weld pads (bonding pad), be arranged on the surface of this chip, connect this first, second power ring via many sealing wires (bonding wire) respectively, to transmit this first operating voltage respectively to this core circuit and transmit this second operating voltage to this input/output circuitry.In addition, this first power ring is arranged between this second source ring and this chip.
The present invention provides a kind of sphere grid array in addition, and (it comprises a substrate (substrate) and a chip (die) for ball grid array, BGA) packaging body (package).This substrate comprises one first power ring (firstpower ring), is arranged on one first wiring layer, is used for transmitting one first operating voltage; One second source ring (second power ring) is arranged on this first wiring layer, is used for transmitting one second operating voltage; A plurality of contacts are arranged on this first wiring layer, and are electrically connected this first and second power ring via the 3rd wiring layer between this first wiring layer and this second wiring layer respectively; A plurality of first pins (first ballout), be used for assembling the circuit board of this spherical grid array package body, to import this first operating voltage by this circuit board, these a plurality of first pins are arranged on first conductive area of one second wiring layer, and this first conductive area is to be electrically connected this first power ring via at least one first through hole (first via); And a plurality of second pins (second ballout), be used for assembling the circuit board of this spherical grid array package body, to import this second operating voltage by this circuit board, these a plurality of second pins are arranged on second conductive area of this second wiring layer, and this second conductive area is to be electrically connected this second source ring via at least one second through hole (second via).This chip includes a core circuit (corecircuit), is used for carrying out a predetermined operation; (input/output circuit I/Ocircuit), is electrically connected this core circuit at least one input/output circuitry, is used for control signal input and this core circuit of output; And a plurality of weld pads (bonding pad), being arranged on the surface of this chip, these a plurality of weld pads connect this a plurality of contacts respectively, are used for transmitting this first operating voltage to this core circuit and transmit this second operating voltage to this input/output circuitry.In addition, this second source ring is arranged on the inboard of this first power ring.
Description of drawings
Fig. 1 is first schematic diagram of existing wire-bonded spherical grid array package body.
Fig. 2 is second schematic diagram of wire-bonded spherical grid array package body shown in Figure 1.
Fig. 3 is a wire-bonded spherical grid array package body shown in Figure 1 sectional view along tangent line 3-3 '.
Fig. 4 engages first schematic diagram of spherical grid array package body for existing reviewing.
Fig. 5 is second schematic diagram that reviewing shown in Figure 4 engages spherical grid array package body.
Fig. 6 is that reviewing shown in Figure 4 engages the sectional view of spherical grid array package body along tangent line 6-6 '.
Fig. 7 is first schematic diagram of wire-bonded spherical grid array package body of the present invention.
Fig. 8 is second schematic diagram of wire-bonded spherical grid array package body shown in Figure 7.
Fig. 9 is a wire-bonded spherical grid array package body shown in Figure 7 sectional view along tangent line 9-9 '.
Figure 10 engages first schematic diagram of spherical grid array package body for reviewing of the present invention.
Figure 11 is second schematic diagram that reviewing shown in Figure 10 engages spherical grid array package body.
Figure 12 is that reviewing shown in Figure 10 engages the sectional view of spherical grid array package body along tangent line 12-12 '.
The explanation of Reference numeral
10,80 is the wire-bonded spherical grid array package body;
12,42,82,112 is substrate;
14a, 14b, 14c, 44a, 44b, 44c, 84a, 84b, 84c, 114a, 114b, 114c are input/output circuitry;
18,48,68,88,128 is weld pad;
22,92 is pad;
26a, 26b, 26c, 26d, 56a, 56b, 56c, 56d, 96a, 96b, 96c, 96d, 126a, 126b, 126c, 126d are conductive area;
30,60,100,130 is second wiring layer;
34,64,104,134 is solder ball;
66,136 is metal coupling;
11,41,81,11 is chip;
13,43,83,113 is core circuit;
16a, 16b, 16c, 16d, 86a, 86b, 86c, 86d are sealing wire;
20a, 20b, 20c, 20d, 50a, 50b, 50c, 50d, 90a, 90b, 90c, 90d, 120a, 120b, 120c, 120d are power ring;
24,54,94,124 is pin;
28,58,98,128 is first wiring layer;
32,62,102,132 is through hole;
40,110 are reviewing joint spherical grid array package body; And
70,140 is the 3rd wiring layer.
Embodiment
See also Fig. 7, Fig. 7 is first schematic diagram of wire-bonded spherical grid array package body 80 of the present invention.Packaging body 80 includes a chip 81 and a substrate 82, chip 81 includes a core circuit 83 and is used for carrying out a predetermined operation, a plurality of input/ output circuitry 84a, 84b, 84c are used for control signal input and output core circuit 83, and a plurality of weld pad 88 is used for being electrically connected chip 81 and substrate 82.First wiring layer 98 of substrate 82 is provided with a plurality of power ring 90a, 90b, 90c, 90d and is used to provide the required operating voltage of chip 81 work and a plurality of pad 92 and is used for transmission signals, in addition, be electrically connected mutually via a plurality of sealing wire 86a, 86b, 86c, 86d between chip 81 and the substrate 82, wherein sealing wire 86a, 86b, 86c connect power ring 90a, 90b, 90c, 90d respectively transmitting different voltage to chip 81, and sealing wire 86e is connected between pad 92 and the corresponding weld pad 88 to transmit signal.For instance, if packaging body 80 is north bridge chips of a computer system, chip 81 is used for controlling the signal transmission between a high-speed peripheral device (for example memory and display card) and the microprocessor (for example central processing unit (CPU)), and promptly the core circuit 83 of chip 81 is used for carrying out above-mentioned functions.On the other hand, input/ output circuitry 84a, 84b, 84c then are used for controlling a memory respectively, a display card, and the signal between CPU and the core circuit 83 transmits.As previously mentioned, input/output circuitry 84a is corresponding to memory, and input/output circuitry 84b is corresponding to display card, and input/output circuitry 84c is corresponding to microprocessor, and core circuit 13 needs different operating voltages to come operate as normal.Therefore need power ring 90a, 90b, 90c, 90d to provide required operating voltage respectively to input/ output circuitry 84a, 84b, 84c and core circuit 83.Note that is not influencing under the disclosed condition of the technology of the present invention, and for convenience of explanation, Fig. 7 and not shown all sealing wire 86 are connected with pad 92.Weld pad 88 can be used to transmission signals and transmits voltage corresponding to input/ output circuitry 84a, 84b, 84c and core circuit 83.In Fig. 7, sealing wire 86a, 86b, 86c, 86d are used for connecting weld pad 88 and power ring 90a, 90b, 90c, 90d respectively, to distinguish input voltage to input/ output circuitry 84a, 84b, 84c and core circuit 83.In addition, sealing wire 86e connects weld pad 88 and pad 92, to be used for transmission signals.So, utilizing the auxiliary of sealing wire 86a, 86b, 86c, 86d, 86e, chip 81 can obtain required operating voltage from substrate 82, and can transmit signal mutually between chip 81 and the substrate 82.
See also Fig. 8 and Fig. 9, Fig. 8 is second schematic diagram of wire-bonded spherical grid array package body 80 shown in Figure 7, and Fig. 9 is wire-bonded spherical grid array package body 80 a shown in Figure 7 sectional view along tangent line 9-9 '.BGA packaging body 80 includes a plurality of pins 94, it is that mode with matrix is arranged on one second wiring layer 100, wherein this second wiring layer 100 includes a plurality of conductive area 96a, 96b, 96c, 96d, and the pin 94 on each conductive area 96a, 96b, 96c, the 96d is to be used for connecting a circuit board respectively to import the suitable operating voltage of this input/ output circuitry 84a, 84b, 84c and core circuit 83.As shown in Figure 9, first wiring layer 98 and second wiring layer 100 are separately positioned on the two-layer up and down of wire-bonded spherical grid array package body 80.Please note, Fig. 7 and Fig. 8 are vertical view, therefore be to be connected to each other between conductive area 96a, 96b, 96c, 96d and corresponding power ring 90a, 90b, 90c, the 90d by through hole (via) 102, therefore when the metallic conduction ball of BGA packaging body 80 via its bottom, when for example solder ball (solder ball) 104 was installed on a circuit board, the pin 94 of corresponding solder ball 104 just was electrically connected to this circuit board.Therefore when by this circuit board when this BGA packaging body 80 is imported a voltage, the voltage of this input is then via solder ball 104, pin 94, through hole 102, power ring 90a, 90b, 90c, 90d, sealing wire 86a, 86b, 86c, 86d, and weld pad 88 and drive input/ output circuitry 84a, 84b, 84c and core circuit 83 respectively.Similarly, when by this circuit board when input/ output circuitry 84a, 84b, 84c import a signal, this signal is then via solder ball 104, pin 94, through hole 102, pad 92, sealing wire 86e, and weld pad 88 and be sent to this input/ output circuitry 84a, 84b, 84c.When exporting a signal by input/ output circuitry 84a, 84b, 84c, this signal is then via weld pad 88, sealing wire 86e, pad 92, through hole 102, pin 94, and solder ball 104 and be transferred into this circuit board.
By Fig. 7,8 can find out significantly, in the present embodiment, power ring 90d is on first wiring layer, be arranged on power ring 90a, 90b, between 90c and the chip 81, therefore the power pin of corresponding power ring 90d just is configured in power ring 90a, 90b, the inboard of the corresponding power pin of 90c, therefore engage the circuit board of spherical grid array package body 80 corresponding to being used for package lead, its solder joint corresponding to the pin of power ring 90d also is arranged on corresponding to power ring 90a, 90b, the inboard of the pin of 90c is so that stick together joint smoothly, when chip 81 changes its packaged type, for example encapsulate in the reviewing mode, as Fig. 4, shown in 5, it is identical with wire-bonded spherical grid array package body of the present invention 80 that existing reviewing engages the power ring configuration of spherical grid array package body 40 and the configuration of corresponding pin position, so after chip 81 encapsulates in the reviewing mode, the relevant pin position that is used to provide chip 81 operating voltages similarly engaged the circuit board of spherical grid array package body 80 applicable to originally being used for package lead, therefore for the manufacturer of supply packaging body 80, can promote its product competitiveness, and provide the manufacturer of circuit board needn't significantly change the circuit layout of circuit board.
See also Figure 10, Figure 11 and Figure 12, Figure 10 engages first schematic diagram of spherical grid array package body 110 for reviewing of the present invention, Figure 11 is second schematic diagram that reviewing shown in Figure 10 engages spherical grid array package body 110, and Figure 12 be reviewing joint spherical grid array package body 110 a shown in Figure 10 sectional view along tangent line 12-12 '.Reviewing engages spherical grid array package body 110 and includes a chip 111 and a substrate 112, this chip 111 includes a core circuit 113 and a plurality of input/output circuitry 114a, 114b, 114c, substrate 112 is provided with a plurality of power rings (power ring) 120a, 120b, 120c, 120d, be used to provide different operating voltages respectively, and power ring 120a, 120b, 120c, 120d are arranged on same first wiring layer 128.Core circuit 113, input/output circuitry 114a, 114b, 144c, and the work of power ring 120a, 120b, 120c, 120d is identical with the element of the same name of aforementioned wire-bonded spherical grid array package body 80 of the present invention, therefore no longer repeats to give unnecessary details.Packaging body 110 includes a plurality of pins 124 as shown in Figure 11, it is that mode with matrix is arranged on one second wiring layer 130, wherein this second wiring layer includes a plurality of conductive area 126a, 126b, 126c, 126d, pin 124 on each conductive area 126a, 126b, 126c, the 126d is used for connecting a circuit board respectively, to import the operating voltage of this input/output circuitry 114a, 114b, 114c and core circuit 113.Reviewing engages that the topmost different chips 111 that are are the states after chip 81 reverses between spherical grid array package body 110 and the wire-bonded spherical grid array package body 80, be that weld pad 48 (as shown in figure 12) on the chip 111 is positioned at the lower surface of chip 111 but not weld pad 88 shown in Figure 7 is positioned at the upper surface of chip 81, in the present embodiment, form metal coupling (bump) 136 on this weld pad 118, for example Solder Bumps (solderbump) or golden projection (gold bump) are so that be connected with corresponding weld pad 138 on first wiring layer 128 of substrate 112.In addition, power ring 120a, 120b, 120c, 120d and weld pad 188 (i.e. first wiring layer 58) all are connected to one the 3rd wiring layer 140 via through hole (via) 132, and via the wiring (trace) on the 3rd wiring layer 140, make power ring 120a, 120b, 120c, 120d can give core circuit 113 and input/output circuitry 114a via suitable weld pad 138 output services voltages, 114b, 114c, similarly, the 3rd wiring layer 140 also is electrically connected mutually via through hole 132 with second wiring layer 130, therefore, pin 124 can be used to transmission signals and power supply to chip 111, as wire-bonded spherical grid array package body 80, reviewing engages spherical grid array package body 110 and also uses the metallic conduction ball of tin shot 134 and so on to connect this circuit board.
By Figure 10,11 can learn, in the present embodiment, power ring 120a, 120b, 120c is on first wiring layer 128, be arranged between the weld pad 138 of power ring 120d and corresponding chip 111, therefore the power pin of corresponding power ring 90d just is configured in power ring 90a, 90b, the outside of the corresponding power pin of 90c, so for being used for assembling the circuit board that reviewing engages spherical grid array package body 110, its solder joint corresponding to the power pin of power ring 90d also is arranged on corresponding to power ring 90a, 90b, the outside of the pin of 90c is so that both stick together joint smoothly, when chip 111 changes its original packaged type, for example encapsulate in the lead-in wire mode, as Fig. 1, shown in 2, the power ring configuration of existing wire-bonded spherical grid array package body 10 and the configuration of corresponding pin position are identical with reviewing joint spherical grid array package body 110 of the present invention, so after chip 111 encapsulates in the lead-in wire mode, the relevant pin position that is used to provide chip 111 operating voltages engaged contact on the circuit board of spherical grid array package body 80 applicable to originally being used for package lead, therefore for the manufacturer of supply packaging body 110, can promote its product competitiveness, and provide the manufacturer of circuit board needn't significantly change the circuit layout of circuit board.
Compared with prior art, the invention discloses a kind of wire-bonded spherical grid array package body, wherein, the power ring of the core circuit of a corresponding chip is arranged on the inboard to the power ring of input/output circuitry that should chip on one substrate, therefore when this chip changes the reviewing packaged type into by the lead packages mode, the relevant pin position that is used to provide this chip operating voltage engaged the circuit board of spherical grid array package body applicable to originally being used for package lead, similarly, the invention also discloses a kind of reviewing and engage spherical grid array package body, wherein, the power ring of the core circuit of a corresponding chip is arranged on the outside to the power ring of input/output circuitry that should chip on one substrate, therefore when this chip changed the lead packages mode into by the reviewing packaged type, the relevant pin position that is used to provide this chip operating voltage was applicable to originally being used for assembling the circuit board that reviewing engages spherical grid array package body.When the manufacturer of the above-mentioned packaging body of supply changes the original packaged type of this chip because cost own or other factors are considered, provide the manufacturer of circuit board can change circuit layout on the circuit board significantly, therefore for the packaging body of using different packaged types, it all uses same pin position configuration and is applicable to corresponding contact on the same circuit board, so that can significantly promote the product competitiveness of this packaging body.In addition, for this circuit board and the pairing electronic product of this packaging body, because the circuit board of same power pin configuration is applicable to packaging body that different encapsulation technology produced, therefore in the manufacture process of this electronic product, the integral production cost can not adopt different encapsulation technologies because of the packaging body of one of element and sharp rise, therefore compared with prior art, the present invention can reduce whole one-tenth production originally.
The above only is the preferred embodiments of the present invention, and every adjustment and change that belongs to claim scope of the present invention should belong within the scope of the present invention.
Claims (10)
1. wire-bonded spherical grid array package body with power supply pin of reviewing packaged type, it includes:
One has the substrate of a first surface and a second surface, and it includes:
One first power ring is arranged on the first surface of a substrate, is used for transmitting one first operating voltage;
One second source ring is arranged on the first surface of this substrate, is used for transmitting one second operating voltage;
A plurality of first pins are used for assembling the circuit board of this spherical grid array package body, import this first operating voltage by this circuit board, and these a plurality of first pins are set on this second surface of this substrate, and are electrically connected this first power ring; And
A plurality of second pins are used for assembling the circuit board of this spherical grid array package body, import this second operating voltage by this circuit board, and these a plurality of second pins are set on the second surface of this substrate, and are electrically connected this second source ring; And
One chip is arranged on the first surface of this substrate, and it includes:
One core circuit is used for carrying out a predetermined operation; With
At least one input/output circuitry is electrically connected this core circuit, is used for control signal input and this core circuit of output; And
Wherein, this first power ring and this second source ring are soldered to the I/O circuit of core circuit and chip respectively; Wherein this first power ring is set between this second source ring and this chip;
Wherein be set at inboard corresponding to second pin of second source ring corresponding to first pin of first power ring.
2. spherical grid array package body as claimed in claim 1, wherein these a plurality of first pins are connected this circuit board with these a plurality of second pins via the metallic conduction ball.
3. spherical grid array package body as claimed in claim 1, wherein, this chip is a wirebonded packages body or a reviewing packaging body.
4. spherical grid array package body as claimed in claim 1 also is included in lip-deep a plurality of weld pads of chip.
5. wire-bonded spherical grid array package body with power supply pin of reviewing packaged type, it includes:
One has the substrate of a first surface and a second surface, and it includes:
One first power ring is arranged on the first surface of a substrate, is used for transmitting one first operating voltage;
One second source ring is arranged on the first surface of this substrate, is used for transmitting one second operating voltage;
A plurality of first pins are used for assembling the circuit board of this spherical grid array package body, import this first operating voltage by this circuit board, and these a plurality of first pins are arranged on the second surface of this substrate, and are electrically connected this first power ring;
A plurality of second pins are used for assembling the circuit board of this spherical grid array package body, import this second operating voltage by this circuit board, and these a plurality of second pins are arranged on the second surface of this substrate, and are electrically connected this second source ring; And
One chip, it includes:
One core circuit is used for carrying out a predetermined operation;
At least one input/output circuitry is electrically connected this core circuit, is used for control signal input and this core circuit of output; And
Wherein, this first power ring and this second source ring are soldered to the I/O circuit of core circuit and chip respectively; Wherein this second source ring is arranged on the inboard of this first power ring;
Wherein be set at inboard corresponding to first pin of first power ring corresponding to second pin of second source ring.
6. spherical grid array package body as claimed in claim 5, wherein this first pin is connected this circuit board with this second pin via the metallic conduction ball.
7. spherical grid array package body as claimed in claim 5, wherein, this chip includes a plurality of metal couplings in addition, is formed at respectively on these a plurality of weld pads, is used for connecting these a plurality of weld pads and these a plurality of contacts.
8. spherical grid array package body as claimed in claim 5, wherein, this chip is a wirebonded packages body or a reviewing packaging body.
9. spherical grid array package body as claimed in claim 5 also comprises a plurality of contacts that are arranged on first wiring layer, and those contacts are electrically connected to this first and second power ring by one the 3rd wiring layer between this first and second wiring layer.
10. spherical grid array package body as claimed in claim 5 also is included in lip-deep a plurality of weld pads of chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03101578 CN1225784C (en) | 2003-01-15 | 2003-01-15 | Ballgrid array parkaging body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03101578 CN1225784C (en) | 2003-01-15 | 2003-01-15 | Ballgrid array parkaging body |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1430267A CN1430267A (en) | 2003-07-16 |
| CN1225784C true CN1225784C (en) | 2005-11-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03101578 Expired - Lifetime CN1225784C (en) | 2003-01-15 | 2003-01-15 | Ballgrid array parkaging body |
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| Country | Link |
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| CN (1) | CN1225784C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1300844C (en) * | 2003-10-10 | 2007-02-14 | 威盛电子股份有限公司 | Ball gate array packaging and printed circuit board using same |
| US7683607B2 (en) * | 2007-09-25 | 2010-03-23 | Himax Display, Inc. | Connection testing apparatus and method and chip using the same |
| CN101599480B (en) * | 2008-06-03 | 2011-06-15 | 慧国(上海)软件科技有限公司 | Semiconductor chip encapsulating structure |
| CN102522339B (en) * | 2011-12-12 | 2014-10-22 | 清华大学 | Method for designing general packaging substrate |
| CN108415320B (en) * | 2018-02-13 | 2021-06-29 | 深圳比特微电子科技有限公司 | Power supply circuit, circuit board and virtual digital coin ore digging machine |
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2003
- 2003-01-15 CN CN 03101578 patent/CN1225784C/en not_active Expired - Lifetime
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|---|---|
| CN1430267A (en) | 2003-07-16 |
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