CN1215196A

CN1215196A - Multi-image processing device

Info

Publication number: CN1215196A
Application number: CN98119671A
Authority: CN
Inventors: 田炳焕
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1997-09-29
Filing date: 1998-09-21
Publication date: 1999-04-28
Also published as: KR19990027317A; JPH11175708A

Abstract

A multiple image processor of the invention is sued for synchronously processing image data which have different technic specification and transmiting the processed image date to a common input/output bus. Respective image interfaces and image RAMs are provided between respective image data transmitting channels and the common buss. Respective image interfaces convert image signals from the corresponding transmission channels into digital image data. Respective image RAMs store data from the corresponding image interfaces or a host controller in specified address areas and transmit stored image data to a common input/output bus according to the timing control signal or the input address.

Description

Multi-image processing device

The present invention relates to multi-image processing device, be used for handling simultaneously picture signal with different technologies specification.

The automatic monitor system that robotization is used in handling can be used a plurality of video cameras.For example, can be with a video camera inspected object position check the shape of making article with another video camera.These video cameras can have the different technologies specification as processing speed and so on.Therefore, need a kind of multi-image processing device to handle various picture signals simultaneously.

In the multi-image processing device of routine, the concentrated area is gathered and is handled through the picture signal of passage input separately.The multi-image processing device of this routine is described in No. 050 United States Patent (USP) the 5th, 526.

Referring to Fig. 1, conventional multi-image processing device comprises acquisition system 12 and pixel memory buffer 16.Acquisition system 12 is handled each picture signal and is produced packet (packet) data.Packet data from acquisition system 12 temporarily is stored in the pixel memory buffer 16, is classified, is stored in the mass storage 20 then by address generator 44.

Acquisition system 12 comprises each image interface 22, first in first out (FIFO) memory buffer 14, reaches packet manipulater 26.Each image interface 22 connection is stored corresponding fifo buffer memory 24 into from the picture signal of respective image passage 14 and these picture signals.Each fifo buffer memory 24 exports the view data of storage to packet manipulater 26.Packet manipulater 26 is checked the output that is stored in the image data amount in each impact damper 24 and controls input image data.Here, the operation of packet manipulater 26 and clock signal of system 40 are synchronous.

Picture signal 34 from each image channel 14 is the simulating signals with pixel data information.Each image interface 22 is transformed into digital signal to this simulating signal and produces a series of images acquisition controlling signal 36.Image acquisition control signal 36 comprises horizontal reset signal, vertical reset signal, field signal, written allowance signal and pixel clock signal.From the picture signal of each image interface 22 output are serial pixel datas, and they are the information that unit keeps each pixel with 8 bits.

In packet manipulater 26, have the pixel counter 28 relative with each fifo buffer memory 24.Pixel counter 28 countings and supervision are from the number of the pixel signal of each fifo buffer memory 24.This moment, each pixel counter 28 was with regard to the calculating pixel time clock when the image interface 22 from correspondence applies written allowance signal.

Packet counter 30 countings that are equipped with in packet manipulater 26 also monitor from the number of the image data packets of each fifo buffer memory 24 input.For example, when the number of pixel signal was 32, the number of packet was 1.Packet manipulater 26 outputs to the unit of image pixel memory buffer 16 as packet to 32 pixel signals by output bus 42.

The received image signal of image pixel memory buffer 16 temporary transient these packet unit of storage.Produce the address that be ready to use in storage described picture signal from image address generator 44 this moment.Image address generator 44 is subjected to pattern pulse string (image burst) signal 46 from packet manipulater 26 and the control of video microinterrupt (VUI) signal 48.The type and the channel information of 48 pairs of data packet signals of VUI signal are encoded.Here, channel information is meant the passage number corresponding with each packet data.By image acquisition control signal 36 codings are obtained type information.

The data that are stored in the image pixel memory buffer 16 are stored in the mass storage 20 by output bus 50 and 52.At this moment, storer timing generator 18 produces suitable timing signal and makes data from output bus 52 be stored in the address location of appointment of mass storage 20.

In the combination picture treating apparatus of above-mentioned routine, because the picture signal of importing by image channel is separately concentrated collection and processing, the hardware and software structure all is complicated.

The purpose of this invention is to provide a kind of combination picture treating apparatus, the structure of this device makes to being undertaken respectively by the picture signal of each image channel input and directly handling.

For achieving the above object, a kind of combination picture treating apparatus is provided, be used for handling picture signal simultaneously, and be used for the signal after handling is sent to shared input and output (I/O) bus with different technologies specification.This device comprise separately image interface and image RAM (random access memory) separately.Image interface separately is coming the signal transformation of self-corresponding transmission channel image to become Digital Image Data.Image RAM separately is according to timing controling signal and Input Address, and data from the address area that the image interface or the console controller of correspondence stores appointment into, perhaps are sent to shared I/O bus to the view data of having stored.

Because store or transmit relevant picture signal with Input Address according to timing controling signal, so can handle the picture signal of importing by image channel separately respectively according to image RAM separately of the present invention.

Preferably this combination picture treating apparatus further comprises separately address generator, first multiplexer separately, timing generator separately and second multiplexer separately.The step-by-step counting of the pixel clock signal that address generator separately provides the image interface from correspondence.First multiplexer is separately selected from the address of corresponding address generator and the Input Address of coming autonomous controller (host controller) by shared I/O bus selection, and selected address is input to corresponding image RAM.Timing generator is separately counted, is handled count results and produce timing controling signal according to the expectant control logic the pulse of the pixel clock signal that the image interface by correspondence provides.Second multiplexer is separately selected timing controling signal and is selected the incoming timing control signal by shared I/O bus from master controller from the timing generator of correspondence, and selected control signal is input to corresponding image RAM.

Image RAM preferably includes memory cell array (cell array), serial data input part, parallel data input and output portion, address input part and control part.The image data storage of coming self-corresponding image interface or shared I/O bus in memory cell array.The serial data input part view data of self-corresponding image interface in the future is transformed into serial data and converted data is input to memory cell array.The parallel data input and output portion that has the common parallel port is coming the data of autonomous controller to be input to memory cell array or the data that are stored in the memory cell array are outputed to shared I/O bus.The address input part makes the data of memory cell array select according to Input Address.Control part is controlled the time sequential routine of serial data input part, parallel data input and output portion and address input part according to the timing controling signal of input.

To the detailed description of preferential embodiment of the present invention, it is more obvious that above-mentioned purpose of the present invention and advantage thereof will become by with reference to the accompanying drawings.

Fig. 1 is the block scheme of the conventional combination picture treating apparatus of expression;

Fig. 2 is the block scheme of expression combination picture treating apparatus of the present invention;

Fig. 3 is the interior block diagram of 8 bit to 16 bit transducers of presentation graphs 2 devices;

Fig. 4 is the interior block diagram of the image RAM of presentation graphs 2 devices.

With reference to Fig. 2, handle the picture signal of different technologies specification when forming combination picture treating apparatus of the present invention and these picture signals are sent to 64 I/O buses of shared input and output (I/O) bus.64 I/O buses and picture signal separately for example separately the correspondence of video camera transmit between the

passage

61,62 and 63 and have image interface 71 and image RAM75.Image interface 71 separately becomes Digital Image Data transmit the image signal transformation of

passage

61,62 with 63 from correspondence.Picture signal from image interface 71 is 8 bit parallel data, so it is transformed into 16 bit parallel data by 8 to 16 bit changers 72.Image RAM 75 separately is according to the 5 Bit Timing Control signals and 9 bit address of input, from 8 to 16 bit changers or come autonomous controller, for example the picture signal of CPU (central processing unit) (CPU) 65 stores in the address area of appointment, perhaps by 64 I/O buses the view data of storage is sent to high capacity dynamic ram 64.

In addition, between the

correspondence transmission passage

61,62 and 63 of 64 I/O buses and picture signal separately, have address generator 73, first multiplexer 76, timing generator 74 and second multiplexer 77.The step-by-step counting of the pixel clock signal that 73 pairs of address generators are supplied with from image interface 71 also produces 9 bit address.First multiplexer 76 is selected to be input to image RAM 75 from 9 bit address of address generator 73 with by 64 I/O buses from 9 bit address of CPU 65 inputs and these 9 bit address.The pixel clock signal step-by-step counting that 74 pairs of timing generators are provided by image interface 71, according to this result of expectant control logical process and produce 5 Bit Timing Control signals.Second multiplexer 77 is selected from 5 Bit Timing Control signals of timing generator 74 and the 5 Bit Timing Control signals of importing by 64 I/O buses, and these 5 Bit Timing Control signals are input to image RAM75.

When importing simultaneously from 9 bit address of address generator 73 with by 9 bit address that 64 I/O buses are imported from CPU 65, first multiplexer is at first exported by 9 bit address of 64 I/O buses from the CPU65 input.When importing simultaneously from 5 Bit Timing Control signals of timing generator 74 with by the 5 Bit Timing Control signals that 64 I/O buses are imported from CPU 65, second multiplexer 77 is at first exported by the 5 Bit Timing Control signals of 64 I/O buses from CPU 65 inputs.

Referring to Fig. 3,8 latchs 721 and 722 parallelly are connected to 8 to 16 bit changers (72 among Fig. 2).When clock signal clk when low, first latch 721 is accepted 8 bit image data.On the contrary, when clock signal clk when being high, second latch 722 is accepted 8 bit image data.Therefore, form 16 bit image data from first view data of first latch 721 with from second view data of second latch 722.This 16 bit image data storage in the assigned address position of image RAM (Fig. 2 75).

Referring to Fig. 4, image RAM 75 comprises memory cell array 755, serial data input part 751, parallel data input and output portion 754, address input part 752 and control part 753.From 8 image data storage of coming to 16 bit changers (Fig. 2 72) or from 64 I/O buses memory cell array 755.Serial data input part 751 is being transformed into serial data from 8 view data to 16 figure place transducers 72 and transform data being input to memory cell array 755.754 data from the CPU 65 of Fig. 2 of parallel data input and output portion that have the common parallel port are input to memory cell array 755, perhaps the data that are stored in the memory cell array 755 are outputed to 64 I/O buses.Address input part 752 makes the data of memory cell array 755 select according to 9 bit address of input.Control part 753 is controlled the time sequential routine of serial data input part 751, parallel data input and output portion 754 and address input part 752 according to 5 Bit Timing Control signals of input.

As mentioned above, according to combination picture treating apparatus of the present invention, pass through the picture signal of image channel input separately owing to handle respectively and directly, so the structure of hardware and software is all uncomplicated.

The present invention is not limited to the foregoing description, and is self-evident, and those skilled in the art can make many modification in scope and spirit of the present invention.

Claims

1. combination picture treating apparatus is used for handling simultaneously the picture signal with different technologies specification and is used for processed signal is sent to shared input and output (I/O) bus, and described device comprises:

Image interface separately is used for becoming Digital Image Data transmitting channel image signal transformation from correspondence;

Image RAM separately is used for according to timing controling signal and Input Address, from the data storage of correspondence image interface or master controller in the address area of appointment, perhaps the view data of having stored is sent to described shared I/O bus.

2. combination picture treating apparatus as claimed in claim 1 further comprises:

Address generator separately is used for the pixel clock signal pulse that is provided by described correspondence image interface is counted, and produces the address then;

First multiplexer separately is used to select from the address of described corresponding address generator and the Input Address of coming from described master controller by described shared I/O bus, selected address is input to the image RAM of described correspondence;

Timing generator separately, the pulse that is used for described pixel clock signal that the image interface from described correspondence is provided count, handle described count results, and produce timing controling signal according to the expectant control logic; And

Second multiplexer separately, be used to select from the described timing controling signal of the timing generator of described correspondence with by the timing controling signal of described shared I/O bus, and be used for described timing controling signal is input to the image RAM of described correspondence from described master controller input.

3. combination picture treating apparatus as claimed in claim 1, wherein said image RAM comprises:

Memory cell array is used for from the image interface of described correspondence or from the image data storage of shared I/O bus therein;

The serial data input part is used for the view data from the image interface of described correspondence is transformed into serial data, and described transform data is input to described memory cell array;

Have the parallel data input and output portion of common parallel port, be used for the data from described master controller are input to described memory cell array, or be used for the data that are stored in described memory cell array are outputed to described shared I/O bus;

The address input part is used for making the data of described storage unit obtain selecting according to described Input Address; And

Control part is used for controlling described serial data input part, described parallel data input and output portion, and time sequential routine of described address input part according to described incoming timing control signal.