CN1212463A - Printed-circuit board bearing plate for ball grid array integrated circuit component - Google Patents
Printed-circuit board bearing plate for ball grid array integrated circuit component Download PDFInfo
- Publication number
- CN1212463A CN1212463A CN 97119612 CN97119612A CN1212463A CN 1212463 A CN1212463 A CN 1212463A CN 97119612 CN97119612 CN 97119612 CN 97119612 A CN97119612 A CN 97119612A CN 1212463 A CN1212463 A CN 1212463A
- Authority
- CN
- China
- Prior art keywords
- substrate
- carrier
- grid array
- row
- tellite
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The printed circuit board bearing plate for ball gridarray integrated circuit component can bear the individual tellite of ball gridarray integrated circuit component. These tellites are accepted product tellites cut out from ball gridarray tellite row, in which said bearing plate contains several tellite-receiving holes. Said bearing plate is identical to said tellite row in overall size, in which the number of tellite-receiving holes is equal to the number of tellites in said tellite row, and after these individual accepted product tellites are inserted into the tellite-receiving holes respectively, the positions of these tellites are correspondent to original identical positions of these tellites positioned in said tellite row.
Description
The present invention relates to a kind of ball grid array integrated circuit (BGAIC, Ball-Grid Array IntegratedCircuit) making of element, be particularly related in a kind of ball grid array integrated circuit component encapsulation manufacturing process, can be in order to handle the single sphere grid array tellite that reclaims, in order to avoid waste finished product, and a kind of carrier of the whole cost of reduction ball grid array integrated circuit component.
Ball grid array integrated circuit, be designated hereinafter simply as BGAIC, the high pin that is a kind of a new generation is counted IC encapsulation (packaging), its encapsulation that is applicable to now the integrated circuit of ultra-large integrated (ULSI, ultra-large scale integration) that micron resolution manufacturing is in proper order come out is used.Because the function of integrated circuit becomes increasingly complex, be that the degree of integration of circuit quantity of unit is more and more higher with the transistor, so traditional QFP (quad flat pack) or PGA (pin-grid array) do not meet requirement of actual application gradually.For example, common QFP and PGA only provide 100 to 200 IC pins, for today complicated numerical digit logic electronics IC circuit, obviously use inadequately gradually.
Widely used at present, PC based on 64 bit microprocessors, its core logic (core logic) circuit, must and microprocessor, and such as DRAM as main system memory, with as the SRAM of memory cache etc., each links with 64 full bus-bar width.Therefore, if this kind core logic is made into the IC into one chip, single just each data bus each address bus corresponding with it just must use near 200 branch connecting pins, if add other control signal, just can surpass 300 branch connecting pins easily.BGA IC encapsulation is and a kind ofly can meets the encapsulation that this kind high pin is counted requirement.
Based on a small pieces tellite (printed circuit board) of printed circuit technique, constituted the substrate (substrate) of sphere grid array encapsulation.As well known to those skilled in the art, semiconductor circuit wafer (die) after the cutting is earlier cemented on the surface of this substrate by the pick-and-place machine (pick-and-placemachines) of automation, and by bonding equipment (wire-bonding machines) the wiring pad on the circuit chip is connected on the corresponding weld pad on the sphere grid array encapsulation tellite with gold thread again.Afterwards again by the encapsulating machine with the entire circuit wafer, comprise its bonding wire and weld pad etc., all sealed.Treat after the encapsulating sclerosis that hundreds of soldered balls in the sphere grid array of substrate back are handled forming again by reflow machine (solderreflow).
Above-mentioned all make each making step of sphere grid arrays encapsulation IC elements, comprise that semiconductor wafer is got to put the binding of bonding wire, encapsulating, the formation of soldered ball, even the test of IC element etc. all are to be that the continuity tellite row's of unit form is handled with several sphere grid arrays of row.In fact, the IC element of sphere grid array encapsulation, its tellite itself promptly are to make with a form of arranging continuously several pieces during fabrication.The sphere grid array tellite of these continuous multi-discs is to link together with the printed circuit board (PCB) linking portion beyond each substrate itself.After treating that wafer package finishes, the substrate of these multi-discs can be cut apart with a knife or scissors, and forms independently ball grid array integrated circuit component.
This is a row method with continuous several units, and the tellite area that is based on each sphere grid array on the one hand is minimum for general tellite, with single processing difficulty and do not have benefit comparatively by contrast.For example, handle for the automation of sphere grid array tellite, no matter be the making of substrate itself, or the manufacturing process of IC encapsulation, all need use witness marker (fidicials), and location hole etc.This can supply to carry out pattern recognition such as television camera, and the plant of location protruded stigma, so that carry out the usefulness of automation location calibration.This type of witness marker and location hole, it can take the area of significant proportion for single sphere grid array substrate, form the waste of substrate area.
On the other hand, running is handled in the various automation in IC when encapsulation, if can be unit and handling continuously with several sphere grid arrays of row, and can be than being that the unit efficient of getting up is significantly high with each.For example, single only with regard to substrate to being written into and sending with regard to the running of automatic processor tool, carry out once obviously than carrying out an efficient for high every several substrate units every one.
But, when the substrate in a row of sphere grid array is made, because various factors is, in substrate in a row waste product appears sometimes.Since the appearance position of waste product among whole row might not, whole row's substrate of waste product appears in the therefore efficient of making for follow-up sphere grid array encapsulation, normally whole row is scrapped.At each production firm's dog-eat-dog, and environmental requirement today of coming into one's own, this kind standard of scrapping then is that the utmost point does not meet cost and environmental protection requirement.Especially, if whole several sphere grid array substrates of row only because of a waste product wherein occurring, promptly need remaining qualified product is rejected, obviously be a kind of practice of waste.
Therefore, one of purpose of the present invention provides a kind of printed-circuit board bearing plate of ball grid array integrated circuit component, and it can carry the qualified product substrate of recovery, handles to provide with the handling procedure that is same as normal substrate row, so that reduce cost.
Another object of the present invention provides a kind of printed-circuit board bearing plate of ball grid array integrated circuit component, and it can heavily cover and recycle.
For achieving the above object, the invention provides a kind of printed-circuit board bearing plate of ball grid array integrated circuit component, but the independent tellite of bearing ball grid array integrated circuit component, these substrates are the qualified product substrates that cut down on the sphere grid array substrate row, wherein include a plurality of substrate bearing holes in this carrier.Being characterized as of this carrier, the overall dimension of this carrier is identical with this substrate row, substrate bearing hole quantity wherein is identical with number of substrates among this substrate row, and its substrate bearing hole is after these independent qualified product substrates of having planted, wherein the position of substrate be with this substrate row in these substrates be in corresponding same position.
For making above-mentioned and other purposes of the present invention, feature, can more obviously being easy to understand with advantage, utilize the preferred embodiment conjunction with figs., be described in detail below.In the accompanying drawing:
Fig. 1 is a plane graph, shows that wherein multi-disc sphere grid array tellite is joined into the top view of the part surface that is a row;
Fig. 2 is a plane graph, wherein shows the plane graph of sphere grid array printed-circuit board bearing plate of the present invention; With
The perspective view of Fig. 3 shows sphere grid array board bearing plate bearing substrate of the present invention, and one side is sticked fixing situation with the stickiness film with both.
Fig. 1 is a plane graph, shows that wherein multi-disc sphere grid array tellite is joined into the top view of the part surface that is a row.Shown this substrate row 100 includes five sphere grid array substrates 110 of row among Fig. 1, because cutting and separating not as yet is to go up the linking portion that indicates with label 112 with substrate row to be connected between its two adjacent substrate 110.By contrast, utilized elongated slot 114 generally to define between the two adjacent substrates.In fact, elongated slot 114 and vertical with it elongated slot 116, both are towards the interior sidewall surface of one common peripheral around the square region central point, will form the side wall of the independent sphere grid array substrate after the cutting.
When having one or more substrate 110 appearance defective among the row of the sphere grid array tellite among Fig. 1 100, the program that can cut earlier, so that the substrate 110 of defective item is rejected, 110 of all the other qualified substrates keep to be concentrated.The qualified product substrate that remains utilizes the carrying effect of carrier of the present invention after a while, just can utilize normally, and must not rejected together with remaining defective item.
Fig. 2 is a plane graph, wherein shows the plane graph of ball grid array integrated circuit component carrier of the present invention.Sphere grid array board bearing plate 200 among Fig. 2 is to make corresponding to the row of the substrate among Fig. 1 100.Basically, carrier 200 is by making such as the sheet material that contains copper sheet or contain the alloy sheet etc. of aluminium, and it is 100 suitable that its thickness and substrate are arranged.
In the embodiment of Fig. 2, have on the carrier 200 quantity and the substrate of Fig. 1 arrange 100 identical, that is, five substrate bearing holes 210.The bore size of each sphere grid array substrate bearing hole 210 external dimensions with substrate 110 in fact is suitable, just can make substrate 110 closely but easily be inserted in the bearing hole 210.In other words, each substrate bearing hole 210 of on carrier 200, being offered, its by four segment base plates rectangular 214 and 216 center on the hollow space that forms, just can hold the insertion of the qualified product of the independent substrate 110 after the cutting.And after independent qualified product substrate inserted, its position just can be corresponding to the position of substrate 110 corresponding among the normal substrate row 100.
Be plugged with the carrier 200 of the qualified product of substrate 110; its one side can utilize the stickiness film to be attached; so that make substrate 110 and carrier 200 firmly be formed the framework of full wafer; have the rigidity that is equivalent to normal substrate row 100 among Fig. 1, make every such as getting the carrying out of putting wafer and beating making steps such as gold thread in order to aforementioned ball grid array integrated circuit component.
The perspective view of Fig. 3 shows sphere grid array board bearing plate 200 of the present invention, is plugged with substrate 110 in its substrate bearing hole 210, and one side is sticked fixing situation with stickiness film 300 with both.What Fig. 3 showed is the situation of local tangent plane, and wherein the integrated circuit (IC) wafer (not shown) has been attached on the substrate 110, and necessary gold thread links also to be finished, and has finished the step of sealing encapsulating, forms the situation of colloid 120.
Certainly, what Fig. 3 was shown is the situation that sphere grid array board bearing plate 200 of the present invention is used in the encapsulating step, but scrutable as those skilled in the art institute, it also can be used in to get such as the semiconductor circuit wafer and put, and the manufacturing process of gold thread binding etc.
After finishing making step, each sheet sphere grid array substrate 110 just can unload by carrying in the tray 200.This need tear the film layers 300 among Fig. 3 off, and will take out in the bearing hole 210 of substrate 110 by carrier 200.Removed substrate 110 carrier 200 afterwards, just can cooperate once again, repeatedly be used so that circulate with the independent qualified product substrate 100 that takes off by cutting on the substrate row 100 with defective item.
Certainly, scrutable as those skilled in the art institute, along with the substrate of different ball grid array integrated circuit components comes size, the difference of number of substrates etc. among the row, the size dative number of carrier also can be different thereupon among Fig. 2.
Though the present invention has utilized the mode of explanation preferred embodiment to disclose as above, yet these embodiment are not in order to limit the present invention.Any those skilled in the art can do some and change and variation under the situation that does not break away from spiritual category of the present invention.Therefore, protection scope of the present invention should be as the criterion with the scope that claim was defined.
Claims (6)
1. carrier, but the independent tellite of bearing ball grid array integrated circuit component, those substrates are the qualified product substrates that cut down on the sphere grid array substrate row, wherein include a plurality of substrate bearing holes in this carrier, it is characterized by
The overall dimension of this carrier is identical with this substrate row;
Substrate bearing hole quantity in this carrier is identical with number of substrates among this substrate row; And
The substrate bearing hole of this carrier after those independent qualified product substrates of having planted, wherein the position of substrate be with this substrate row in those substrates be in corresponding same position.
2. carrier as claimed in claim 1 also includes a bottom surface fixed bed.
3. carrier as claimed in claim 2, wherein this bottom surface fixed bed is a sticky glue lamella.
4. carrier as claimed in claim 1, its thickness are identical with this substrate row's thickness.
5. carrier as claimed in claim 1, wherein this carrier is to make with the copper-bearing alloy sheet material.
6. carrier as claimed in claim 1, wherein this carrier is to make with the aluminium-containing alloy sheet material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97119612A CN1080937C (en) | 1997-09-23 | 1997-09-23 | Printed-circuit board bearing plate for ball grid array integrated circuit component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97119612A CN1080937C (en) | 1997-09-23 | 1997-09-23 | Printed-circuit board bearing plate for ball grid array integrated circuit component |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1212463A true CN1212463A (en) | 1999-03-31 |
| CN1080937C CN1080937C (en) | 2002-03-13 |
Family
ID=5175469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97119612A Expired - Fee Related CN1080937C (en) | 1997-09-23 | 1997-09-23 | Printed-circuit board bearing plate for ball grid array integrated circuit component |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1080937C (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970000214B1 (en) * | 1993-11-18 | 1997-01-06 | 삼성전자 주식회사 | Semiconductor device and method of producing the same |
| JPH08162566A (en) * | 1994-12-09 | 1996-06-21 | Hitachi Ltd | Semiconductor device |
| JP3779346B2 (en) * | 1995-01-20 | 2006-05-24 | 日本発条株式会社 | LSI package socket |
| JPH08340164A (en) * | 1995-06-09 | 1996-12-24 | Fujitsu General Ltd | Surface mounting structure of bga type package |
-
1997
- 1997-09-23 CN CN97119612A patent/CN1080937C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1080937C (en) | 2002-03-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| USRE45931E1 (en) | Method of manufacturing a semiconductor device | |
| US6847220B2 (en) | Method for ball grid array chip packages having improved testing and stacking characteristics | |
| EP2362416B1 (en) | Multi-die module | |
| US20020131251A1 (en) | Semiconductor card and method of fabrication | |
| EP0392242A2 (en) | Module assembly with intergrated semiconductor chip and chip carrier | |
| KR20000023475A (en) | Method of production of semiconductor device | |
| US6853090B2 (en) | TAB tape for semiconductor package | |
| CN1080937C (en) | Printed-circuit board bearing plate for ball grid array integrated circuit component | |
| JP2546629B2 (en) | Tape carrier package for semiconductor device, manufacturing method thereof, and manufacturing method of semiconductor device | |
| US6565008B2 (en) | Module card and a method for manufacturing the same | |
| US7501701B2 (en) | Rewiring substrate strip having a plurality of semiconductor component positions | |
| EP0036907B1 (en) | Multi-lead plug-in type package for circuit element | |
| JP3154159B2 (en) | Carrier for ball grid array integrated circuit board | |
| US20010051383A1 (en) | Method for identifying defective elements in array molding of semiconductor packaging | |
| CN218388099U (en) | LGA PCB board and module, PCB mainboard | |
| EP0910113B1 (en) | Carrier for substrate of ball-grid array integrated circuit devices | |
| KR100281437B1 (en) | Carriers for Ball-Grid Array Integrated Circuit Device Boards | |
| JPH038366A (en) | Package for semiconductor device | |
| EP0698920A2 (en) | A method for assembling integrated circuits upon printed circuit boards | |
| US6838756B2 (en) | Chip-packaging substrate | |
| GB2232006A (en) | Pre-testable encapsulated semiconductor die package | |
| JPH03142895A (en) | Hybrid integrated circuit mounted board and packaging method based on film carrier technology | |
| Barnwell | Hybrid economics—A specialist manufacturer's view | |
| JPH08138988A (en) | Semiconductor device | |
| KR20030080987A (en) | Multi-layer-type semiconductor package and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: UNIMICRON ELECTRONICS CO., LTD. Free format text: FORMER OWNER: QUNCE ELECTRONIC CO., LTD. Effective date: 20011210 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20011210 Address after: Taoyuan County of Taiwan Province Patentee after: Xinxing Electronics Co., Ltd. Address before: Taipei city of Taiwan Province Patentee before: Qunce Electronic Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20020313 Termination date: 20091023 |