CN1210774C - Electrostatic protection structure with defect area inside drain and its making process - Google Patents
Electrostatic protection structure with defect area inside drain and its making process Download PDFInfo
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- CN1210774C CN1210774C CN 02103501 CN02103501A CN1210774C CN 1210774 C CN1210774 C CN 1210774C CN 02103501 CN02103501 CN 02103501 CN 02103501 A CN02103501 A CN 02103501A CN 1210774 C CN1210774 C CN 1210774C
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Abstract
The present invention relates to an electrostatic discharge protective structure with a defect region in a drain electrode, which at least comprises a semiconductor substrate, a gate electrode structure positioned on the surface of the semiconductor substrate, a source/drain electrode positioned in the semiconductor substrate on both sides of the gate electrode structure, and a defect structure region positioned in the drain electrode. The defect structure region positioned in the drain electrode can generate a large quantity of drain current, so that the effect of the electrostatic discharge protective structure can be enhanced.
Description
Technical field
The present invention is particularly to a kind of ESD-protection structure and manufacture method thereof relevant for the semiconductor integrated circuit technology, more is particularly to have in a kind of drain the ESD-protection structure and the manufacture method thereof of defect area.
Background technology
In the application of integrated circuit (ICs), materials such as conductor, semiconductor and insulating barrier have been widely used, wherein by film deposition techniques (Thin Film Deposition), above-mentioned each layers of material can be deposited on and treat combinations circle (wafer) surface, to form semiconductor subassembly such as transistor or electric capacity etc.
Yet in semiconductor device, static discharge (ESD:electrostatic discharge) is gone into pad (I/O pad) intrusion because of touching the static electrification body from the output of wafer through being everlasting under the dry environment, causes the integrated circuit damage.Especially the MOS transistor thin gate pole oxidation layer (thingate oxide) of (rupture) that breaks because of it has easily is therefore very responsive to high-voltage discharge (high voltage discharges).
As shown in Figure 1; generally have the output that internal circuit unit district 30 and electrically connects with it in the semiconductor device and go into pad 10, wherein, add an ESD-protection structure 20 between the two; with position and filtration that static discharge is rationed the power supply, avoid taking place the ESD damage.
ESD-protection structure 20 generally comprises golden oxygen half (MOS) transistor; as NMOS; PMOS; or CMOS transistor; as shown in Figure 2; in the occasion of nmos pass transistor; gate 21 and source electrode 22 ground connection; therefore; nmos pass transistor 25 not conductings when normal operation; and when static discharge takes place; then utilize built-in NPN two-carrier transistor 26 (build-in parastic npn bipolar transistor; or abbreviation BJT assembly) conducting is in advance protected internal circuit element district 30, wherein; source electrode N+ type doped region 22 forms emitter-base bandgap grading E; drain N+ type doped region 23 forms collection utmost point C, and P type silicon base 24 then forms base stage B, owing to penetrate base stage E; B ground connection; when static discharge appears at output and goes into pad 10; ESD voltage will trigger (trigger) parasitic two-carrier transistor 26, make nmos pass transistor 25 enter rebound district (snapback region) because of voltage collapse (breakdown), and conduct the ESD electric current by this.
Yet, can not be if be used as the nmos pass transistor 25 of esd protection assembly in time because of voltage collapse enters the rebound district, or can't in time a large amount of ESD conduction of current be gone out, static discharge will directly be invaded internal circuit element district 30 and be caused damage.Therefore, a kind of ESD assembly that can in real time a large amount of ESD conduction of current be gone out of development just becomes semiconductor subassembly technical one big problem.
Summary of the invention
In view of this, a purpose of the present invention provides a kind of ESD-protection structure and comprises at least: the semiconductor substrate; One gate structure is positioned at this semiconductor-based basal surface; An one source pole and a drain are positioned at the semiconductor-based end of these gate structure both sides; And a defect sturcture district, being positioned at this drain, this defect sturcture district utilizes ion disposing process to form.
The invention provides another kind of ESD-protection structure, comprise at least: the semiconductor substrate, it has first conductivity; One gate structure is positioned at this semiconductor-based basal surface; An one source pole and a drain, it has second conductivity, is positioned at the semiconductor-based end of these gate structure both sides; And a defect sturcture district, being positioned at this drain, this defect sturcture district utilizes ion disposing process to form.
In addition, one of manufacture method of ESD-protection structure provided by the invention comprises the following steps: to provide the semiconductor substrate at least; Form a gate structure in this substrate surface; Form an one source pole district and a drain area in this substrate of these gate structure both sides; And utilize ion disposing process in this drain area, to form a defect sturcture district.
Two of the manufacture method of ESD-protection structure provided by the invention comprises the following steps: to provide a substrate with first conductivity; Form a gate structure in this substrate surface; With this gate structure is the mask curtain, and the ion that will have second conductivity is implanted in this substrate, forms a light doped region; Sidewall in this gate structure forms clearance wall; With this gate structure and clearance wall is the mask curtain, and the ion that will have second conductivity is implanted this substrate, forms an one source pole district and a drain area; And utilize ion disposing process to form a defect sturcture district in this drain area.
Three of the manufacture method of ESD-protection structure provided by the invention comprises the following steps: to provide a P type substrate; Form a gate structure in substrate surface; With the gate structure is the mask curtain, and N type ion is implanted in the substrate, forms the light doped region of a N one type; Sidewall in this gate structure forms clearance wall; With this gate structure and clearance wall is the mask curtain, and N type ion is implanted substrate, forms the one source pole district and a drain area of N+ type; And utilize ion disposing process in this drain area, to form a defect sturcture district.
ESD-protection structure of the present invention owing to be positioned at this defect sturcture district of this drain, can produce a large amount of leakage currents, and the effect that can promote this ESD-protection structure.
Description of drawings
Fig. 1 shows the internal circuit unit schematic diagram of traditional tool ESD-protection structure.
The semiconductor profile of the conventional electrostatic discharge prevention structure of Fig. 2 displayed map 1.
Fig. 3 and Fig. 4 show the manufacturing process profile of ESD-protection structure of the present invention.
Fig. 5 shows ESD-protection structure of the present invention, and built-in parasitic two-carrier transistor schematic.
Embodiment
See also Fig. 3 and Fig. 4, it shows the manufacturing process profile of the embodiment of the invention.
At first see also Fig. 3, this step is to form a gate structure 310 according to the conventional semiconductors processing procedure on substrate 300 surfaces, and it comprises a gate insulation layer 312 and a gate conducting layer 314.Wherein this substrate 300 is the semiconductor material, its conductivity then has two kinds on P type and N type, and in the occasion of making CMOS (CMOS), substrate also might comprise p type wells, N type well or twin-well in addition, is example at this with P type silicon base, but and non-limiting the present invention.It forms step and then for example defines active region earlier; next utilizes a thermal oxidation processing procedure; form a field insulating layer (field insulator) (not shown) as regional oxidizing process (LOCOS), can isolate internal circuit element district (not shown), ESD-protection structure district 100 and other active region (not shown) separately by this.Yet for convenience of description, the explanation of present embodiment will only be done explanation at the part in this ESD-protection structure district 100.
See also Fig. 3, form an insulating barrier (not shown) and a conductive layer (not shown) in regular turn on these substrate 300 surfaces, therefore this insulating barrier normally forms with the thermal oxidation processing procedure under hot environment as the material of follow-up gate pole oxidation layer.And conductive layer is generally a compound crystal silicon layer, and it for example can silicomethane SiH
4Be the main reaction thing, and mat low-pressure chemical vapor deposition (LPCVD) processing procedure produces, in order to as follow-up gate electrode.Wherein, have conductivity, can use thermal diffusion method or ionic-implantation to implant phosphorus or arsenic ion, form compound crystal silicon layer through mixing for making conductive layer.Afterwards, for example can this compound crystal silicon layer 314 of micro image etching procedure step patterning, gate pole oxidation layer 312, and form a gate structure 310.
Then still seeing also Fig. 3, is the mask curtain with this gate structure 310, will form a light doped region 330 (also being called the LDD district) with in the ion of the different conductivity of substrate tool is implanted this substrate 300.For example, utilize the implanting ions program, implant N type ion such as phosphorous or contain arsenic ion to P type substrate 300, form the light doped region 330 of N-, on the whole its implant dosage is 5E13～5E19 atom/cm
3, on the whole energy then is 10～50KeV.Afterwards, can carry out a temper to this light doped region 330 certainly.
Secondly, still see also Fig. 3, this step is to form clearance wall (spacer) 320 at this gate structure sidewall, and its generation type for example is the SiO that first compliance landform precedent deposits with the CVD processing procedure in this way
2One insulating barrier (not shown) of layer is on this substrate 300 and these gate structure 310 surfaces, then through for example being that non-equal tropism's etch process of dry ecthing removes this insulating barrier of part and forms this clearance wall 320.Be noted that in addition the step that forms this clearance wall 320 is not certain necessity, that is to say, also can not influence electrostatic discharge (ESD) protection effect of the present invention even do not form this clearance wall 320.Certainly, if when not forming this clearance wall 320, the step of then aforesaid this light doped region 330 of formation can be omitted.
Still see also Fig. 3, this step is to be the mask curtain with gate structure 310 and this clearance wall 320, and ion is implanted this substrate 300, is one source pole 340, a drain 350 of dense doped region and form.Also soon implant in this substrate 300, and form dense doped region (that is source electrode and drain) with higher dosage with the ion of light doped region 330 tool identical conduction kenels.Its generation type for example can be utilized the implanting ions program, implants N type ion such as phosphorous or contain this source electrode 340, this drain 350 that arsenic ion forms the dense doped region of a N+ type, and on the whole its implant dosage is 2E20～2E21 atom/cm
3, on the whole energy then is 40～80KeV.Afterwards, can carry out a temper to this source electrode and drain 340,350 certainly.
Then see also Fig. 4; this step is to form a defect sturcture district 400 in this drain 350; it is cover curtain cover that the zone that its generation type for example will not need ion to implant earlier is used as with photoresistance (not icon); and then utilize implanting ions program 410; implant for example is that germanium (Ge) or argon (Ar) ion are in this drain 350; make the crystalline texture in this drain 350 of part be broken into zone 400 with defective; and then remove this photoresistance cover curtain (not icon), and form an ESD-protection structure 101.And on the whole the dosage of aforesaid implanting germanium be 5E14～1E16atom/cm
3, on the whole energy is 40～60KeV then, and is positioned at the scope in this defect sturcture district 400 of this drain 350, is from this substrate 300 surfaces, and extend to vertical depth on the whole be 200～400 dust parts, as shown in Figure 4.Here be stressed that any mode that can form this defect sturcture district 400 all belongs to claim of the present invention, though present embodiment is an example with implanting germanium or argon ion only, and non-limiting the present invention.
Be stressed that especially in addition; the step that forms this defect sturcture district 400 must (or claim activate to handle in the temper of this light doped region 330 and source electrode and drain 340,350; activation process) afterwards; because in order to keep the defective in this defect sturcture district 400; so this defect sturcture district 400 can produce a large amount of leakage currents and the built-in two-carrier transistor of conducting easily (turn on), and then the effect of promoting this ESD-protection structure 101.Certainly that is to say, after forming this defect sturcture district 400, can not understand the temper of the higher temperatures of the defect sturcture of destroying this defect sturcture district 400 again.
Then, see also Fig. 5, Fig. 5 shows ESD-protection structure of the present invention, and built-in parasitic two-carrier transistor schematic.The present invention also provides a kind of ESD-protection structure 101, comprising: semiconductor substrate 300, and it has first conductivity; One gate structure 310, its sidewall more can have insulating gap wall 320, is positioned at this substrate 300 surfaces; One source pole and drain 340,350, it has second conductivity, is positioned at this substrate 300 of these gate structure 310 both sides; And a defect sturcture district 400, be positioned at this drain 350.Wherein can more include LDD district 330 in this source electrode and the drain 340,350.
ESD-protection structure 101 of the present invention is characterised in that: is positioned at this defect sturcture district 400 of this drain 350, can produces a large amount of leakage currents and the built-in two-carrier transistor 500 of conducting easily, and then the effect of promoting this ESD-protection structure 101.
And the manufacture method of ESD-protection structure 101 of the present invention is then for example formed by above-mentioned manufacture method, so the material of each assembly as previously mentioned, is not described in detail in this.
Also have; ESD-protection structure 101 of the present invention; and The built-in two-carrier transistor 500 as shown in Figure 5; in the occasion of nmos pass transistor; gate structure 310 and source electrode 340 ground connection; therefore; not conducting of nmos pass transistor when normal operation; and when static discharge takes place; then utilize the conducting in advance of this built-in NPN two-carrier transistor 500, protect internal circuit element district 520, wherein; it is emitter-base bandgap grading E that source electrode 340 is used as; it is collection utmost point C that drain 350 is used as, and it is base stage B that P type silicon base 300 then is used as, owing to penetrate base stage E; B ground connection; when static discharge appears at output and goes into pad 510, ESD voltage will trigger (trigger) parasitic two-carrier transistor 500 and enter rebound district (snapback region).This moment is because the feature of ESD-protection structure 101 of the present invention: the defect sturcture district 400 that is positioned at this drain 350; can produce (induce) a large amount of leakage currents and this built-in NPN two-carrier transistor 500 of conducting easily, and then the effect of promoting this ESD-protection structure 101.And; owing to apply voltage (ESDzapping) during static discharge; feasible electronics exhaustion region 530 (depletion region) scope that is positioned at the joint (junction) of these drain 350 downsides becomes greatly and more near this defect sturcture district 400; so more impel the leakage current of static discharge to become bigger and this built-in NPN two-carrier transistor 500 of conducting more easily; and then the effect of more promoting this ESD-protection structure 101, to avoid the damage in internal circuit element district 520.
Applied material among the present invention is not limited to embodiment and quotes from, and it can and form method by the material of the appropriate characteristic of various tools and be replaced, and structure space of the present invention also is not limited to the size that embodiment quotes.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when being defined by claims.
Claims (26)
1. have the manufacture method of the ESD-protection structure of defect area in the drain, comprise the following steps:
Substrate with a gate structure is provided;
Form an one source pole district and a drain area in this substrate of these gate structure both sides; And
Utilize ion disposing process and form a defect sturcture district in this drain area.
2. have the manufacture method of the ESD-protection structure of defect area in the drain as claimed in claim 1, it is characterized in that, wherein this ion disposing process is the implanting germanium ion.
3. have the manufacture method of the ESD-protection structure of defect area in the drain as claimed in claim 2, it is characterized in that, wherein the implant dosage of this germanium ion is 5E14～1E16atom/cm
3, energy then is 40～60KeV.
4. have the manufacture method of the ESD-protection structure of defect area in the drain, comprise the following steps:
One substrate with first conductivity is provided;
Form a gate structure in this substrate surface;
With this gate structure is the mask curtain, and the ion that will have second conductivity is implanted in this substrate, forms a light doped region;
Sidewall in this flashboard structure forms clearance wall;
With this gate structure and clearance wall is the mask curtain, and the ion that will have second conductivity is implanted this substrate, forms an one source pole district and a drain area; And
Utilize ion disposing process and form a defect sturcture district in this drain area.
5. have the manufacture method of the ESD-protection structure of defect area in the drain as claimed in claim 4, it is characterized in that, wherein after forming this light doped region, more this light doped region is carried out a tempering manufacturing process.
6. have the manufacture method of the ESD-protection structure of defect area in the drain as claimed in claim 4, it is characterized in that, wherein after forming this source area and drain area, more this source area and drain area are carried out a tempering manufacturing process.
7. have the manufacture method of the ESD-protection structure of defect area in the drain as claimed in claim 4, it is characterized in that, wherein this first conductivity is the P type, and this second conductivity is the N type.
8. have the manufacture method of the ESD-protection structure of defect area in the drain as claimed in claim 4, it is characterized in that, wherein this first conductivity is the N type, and this second conductivity is the P type.
9. have the manufacture method of the ESD-protection structure of defect area in the drain as claimed in claim 4, it is characterized in that, wherein this ion disposing process is the implanting germanium ion.
10. have the manufacture method of the ESD-protection structure of defect area in the drain as claimed in claim 9, it is characterized in that, wherein, the implant dosage of this germanium ion is 5E14～1E16atom/cm
3, energy then is 40～60KeV.
11. have the manufacture method of the ESD-protection structure of defect area in the drain as claimed in claim 4, it is characterized in that wherein this light doped region is via ion disposing process N type ion to be implanted in this substrate.
12. have the manufacture method of the ESD-protection structure of defect area in the drain as claimed in claim 11, it is characterized in that wherein this N type ion comprises phosphorous and contains one of arsenic ion person, its implant dosage is 5E13～5E19atom/cm
3, energy then is 10～50KeV.
13. have the manufacture method of the ESD-protection structure of defect area in the drain as claimed in claim 4, it is characterized in that wherein, this source area and drain area are via ion disposing process N type ion to be implanted in to form the dense doped region of N+ type in this substrate.
14. have the manufacture method of the ESD-protection structure of defect area in the drain as claimed in claim 13, it is characterized in that wherein this N type ion comprises phosphorous and contains one of arsenic ion person, its implant dosage is 2E20～2E21atom/cm
3, energy then is 40～80KeV.
15. have the manufacture method of the ESD-protection structure of defect area in the drain as claimed in claim 4, it is characterized in that, after forming this defect sturcture district, need not carry out tempering manufacturing process again.
16. have the manufacture method of the ESD-protection structure of defect area in the drain, comprise the following steps:
One P type substrate is provided;
Form a gate structure in substrate surface;
With the gate structure is the mask curtain, and N type ion is implanted in the substrate, forms the light doped region of a N-type;
Sidewall in this gate structure forms clearance wall;
With this flashboard structure and clearance wall is the mask curtain, and N type ion is implanted substrate, forms the one source pole district and a drain area of N+ type; And
Utilize ion disposing process in this drain area, to form a defect sturcture district.
17. have the manufacture method of the ESD-protection structure of defect area in the drain as claimed in claim 16, it is characterized in that wherein this ion disposing process is implanting germanium or argon ion.
18. have the manufacture method of the ESD-protection structure of defect area in the drain as claimed in claim 17, it is characterized in that, after forming this defect sturcture district, need not carry out tempering manufacturing process again.
19. have the ESD-protection structure of defect area in the drain, comprise at least:
One substrate;
One gate structure is positioned at this substrate surface;
An one source pole and a drain are positioned at this substrate of these gate structure both sides; And
One defect sturcture district is positioned at this drain, and this defect sturcture district utilizes ion disposing process to form.
20. have the ESD-protection structure of defect area in the drain as claimed in claim 19, it is characterized in that this gate structure can more include insulating gap wall, is positioned on the two side of this gate structure.
21. have the ESD-protection structure of defect area in the drain as claimed in claim 19; it is characterized in that; wherein being positioned at the scope in this defect sturcture district of this drain, is from this semiconductor-based basal surface, and to extend to vertical depth be 200～400 dust parts.
22. have the ESD-protection structure of defect area in the drain, comprise at least:
The semiconductor substrate, it has first conductivity;
One gate structure is positioned at this semiconductor-based basal surface;
An one source pole and a drain, it has second conductivity, is positioned at the semiconductor-based end of these gate structure both sides; And
One defect sturcture district is positioned at this drain, and this defect sturcture district utilizes ion disposing process to form.
23. have the ESD-protection structure of defect area in the drain as claimed in claim 22, it is characterized in that wherein this first conductivity is the P type, second conductivity is the N type.
24. have the ESD-protection structure of defect area in the drain as claimed in claim 22, it is characterized in that wherein this first conductivity is the N type, second conductivity is the P type.
25. have the ESD-protection structure of defect area in the drain as claimed in claim 22; it is characterized in that; wherein being positioned at the scope in this defect sturcture district of this drain, is from this semiconductor-based basal surface, and to extend to vertical depth be 200～400 dust parts.
26. have the ESD-protection structure of defect area in the drain as claimed in claim 22, it is characterized in that wherein this gate structure can more include insulating gap wall, is positioned on the two side of this gate structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02103501 CN1210774C (en) | 2002-02-06 | 2002-02-06 | Electrostatic protection structure with defect area inside drain and its making process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02103501 CN1210774C (en) | 2002-02-06 | 2002-02-06 | Electrostatic protection structure with defect area inside drain and its making process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1437230A CN1437230A (en) | 2003-08-20 |
| CN1210774C true CN1210774C (en) | 2005-07-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02103501 Expired - Lifetime CN1210774C (en) | 2002-02-06 | 2002-02-06 | Electrostatic protection structure with defect area inside drain and its making process |
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| CN (1) | CN1210774C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI613708B (en) * | 2015-04-28 | 2018-02-01 | 新唐科技股份有限公司 | Semiconductor device and method of fabricating the same |
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- 2002-02-06 CN CN 02103501 patent/CN1210774C/en not_active Expired - Lifetime
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| CN1437230A (en) | 2003-08-20 |
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