TW548819B - Drain-doped electrostatic discharge protection circuit structure - Google Patents

Abstract

The present invention discloses a drain-doped electrostatic discharge protection circuit structure which comprises a drain, source formed in the P-well, the said drain and source comprise a heavier N-type ion doping, the conductive material is filled into the contact through hole, the insulation layer covers the whole surface. The present invention comprises lightly-doped P-type ion-doped region formed only under the drain-doped region, and is deviated with respect to the said contact through hole to reduce the breakdown voltage, so as to enhance the characteristics of the electrostatic charge protection device.

Description

548819

The invention relates to an electrostatic discharge protection circuit, in particular to a series N-type metal-oxide-semiconductor (cascade NMOS) doped on the electrode side. BACKGROUND OF THE INVENTION-Human micron process technology has been widely used to improve the performance and operating speed of integrated circuits to reduce the cost of each chip. However, the protection ability of sub-micron integrated circuit products in electrostatic discharge has been reduced due to the reduction in component size. Therefore, in terms of the technology and industry of sub-micron MOS integrated circuits that are damaged due to ESD, electrostatic discharge ⑶e ati :, Discharge; hereinafter referred to as ESD) Damage is an important factor affecting the integration of integrated circuit products. Regardless of whether it is a logic element or a circuit, during the process of making and using it, its input or output terminal 2_ volts can even reach 4,000 volts of static electricity (probably due to the damage of the components. The purpose is for the building block ^ #Cause: Caused by the inside of the integrated circuit

Pad), between the pad and the internal components: female / one-pin pad (Bonding circuit, so that the external high-voltage electrostatic discharge must be protected by electrostatic discharge protection. Before the electricity enters the internal components, it is grounded.

548819 V. Description of the invention (2) The impact of electrostatic discharge, the current industry standard must be £ SD voltage to ensure the reliability of the product. The large US patent No. 5,5 5 9, 3 5 2 discloses an electrostatic protection circuit that performs an ion doping to form an N-type ion doped region in the child and source regions. Then, the chemical vapor deposition method is used to form an oxide coating and a moss drum: to solidify the wafer surface. ㈣Using anisotropy⑽ "presents; :: After implanted on the side wall of the pole, the ion implantation technique is used to implant ions 2 = 1 4 hetero-regions, and then heat treatment is performed to facilitate the formation of lightly doped = & gt And the electrode and source regions. Ί An insulating layer is successively deposited on the above surface, and then the lithography process is used. &Amp; Net * $ 诘 Λ 妾 The important step of the first tooth contact technology is to use this contact hole to implant Ions, the ion type is ρ-type ions, and the micro-doped P-type doped regions are located below the drain and source contacts. 2 Ding Ping's structure can be seen in Figure 1 on the wafer. A gate structure 1 0 is formed on 0 0. A drain electrode 130 and a source electrode 120 are respectively formed in the P well by using an ion cloth technology. A conductive material is filled in the contact hole 5 and the insulating layer 1 4 〇 Covers the entire surface. The p-type ion doped region containing light doping is located below the drain and source doped regions, and is aligned with the contact hole 1 1 5 to reduce the junction breakdown voltage. This plant Into the lightly doped p-type ion doped regions can promote and polar source Between the substrate and Ρ - η surface ion

548819 V. Description of the invention ⑶ ------------- ‘Chen, this structure can reduce the breakdown voltage of the interface. Although p == 7, the structure can improve the characteristics of the device, but the above implantation results in the seed / wheat area being planted below the contact perforation. This method may try to increase the e, Y < In addition, the P-type ion doped region 2c 1 Λ π ° on the source side is mainly used for the electrostatic current to be grounded through the drain side through the substrate 100. Purpose and summary of the invention: The angle g is the first technique. Ions are implanted by contacting the perforated cloth so that they are formed next to each other, which may cause the phenomenon of leakage current. An object of the present invention is to provide an electrostatic discharge protection circuit including a transistor. The purpose of the present invention is to provide an ESD structure including a series-connected transistor: ajcade MOS B 'which contains a lightly ion-doped region which is only implanted below the drain electrode'. 14 The contact hole is offset, and snow is used to improve the connection. The surface capacitance reduces the surface k and increases the current through the substrate. Seven people in the static discharge protection circuit. At / g " said \ ... a Bu Qi I structure contains a first conductive plastic saddle connected in series said 々 一 一 a conductive type ion doped drain And the source is formed in the second conductivity type well, ^: t: i: Ϊ 4quality. The insulating layer covers the transistor ^ ^ av, and is filled in the contact hole formed in the insulating layer. slight

Page 6 548819 V. Description of the invention (4) ~-The doped second conductive type ion-doped region is formed only below the drain electrode and offset from the contact perforation to reduce the breakdown voltage of the interface. The concentration of the lightly doped second conductive type ion-doped region can reduce the breakdown voltage of the junction to allow more current to be discharged through this. Detailed description of the invention: The present invention discloses the structure and forming method of an electrostatic discharge protection circuit (ESD circuit 100) circuit. The invention discloses an electrostatic discharge protection circuit composed of a series-connected N-type transistor. The structure includes a cascade transistor, which has a slightly ion-doped region, which is only implanted under the drain and in contact with Perforation offset is used to increase the junction capacitance to increase the current flowing through the substrate, thereby reducing the surface current and improving the electrostatic discharge protection characteristics. In the present invention, implanting and ions are used in the above-mentioned doped region =. This method and structure can reduce the breakdown voltage and increase the electricity at the interface, thereby opening the BJT earlier. Referring to FIG. 2, a gate electrode 31 is formed on the wafer 200, and a gate oxide layer 205 is formed below the gate electrode 3 10. For example, the structure of the present invention is composed of a Cascade MOS (cascade MOS) connected in series. 2, wcascade NMOS. The drain electrode 2 3 0 and the source electrode 220 are respectively formed in the P well by using the technique. The above-mentioned electrode 230 and the source electrode 2 25 are relatively concentrated N-type ion dopants. The conductive material is filled in the contact hole, and the light-emitting layer, the light-emitting layer, and the light-emitting layer are coated on the entire surface. The main points of the present invention include: a square P-type ion doped region is formed only at the drain doped region 230 and offset from the contact via 225. The above structure can reduce the interface

548819 V. Description of the invention (5) The breakdown voltage and the acceleration of the turn-on time of the η ρ η bipolar transistor. The implanted lightly doped P-type ion doped region can increase the ion concentration at the ρ-η junction between the drain region and the substrate. This structure can reduce the breakdown voltage of the junction. It is worth noting that the structure of the present invention does not have a lightly doped P-type ion doping region located below the source. The breakdown voltage of the ρ-η junction is inversely proportional to the doping concentration of the substrate, so implanting the lightly doped P-type ion-doped regions described above can reduce the breakdown voltage (the ion concentration of the lightly-doped P-type ion-doped regions is greater than P well concentration). Can refer to the literature " Phys 1 cs and Techno logy of Semiconductor Device ", A. S.

Grove, ρp. 194-195. The decrease in the breakdown voltage of this interface can improve the characteristics of the electrostatic discharge protection circuit, mainly because it can allow more current to discharge through this component. As known to those skilled in the art, under a fixed electrostatic current, the electrostatic current is equal to the sum of the surface current and the current flowing through the substrate. Therefore, the present invention mainly uses doping boron ions on the drain side to increase the junction capacitance to reduce the junction breakdown voltage, so that the current passing through the substrate is increased and the surface current is reduced. This can improve the protection characteristics of electrostatic discharge. The formation method is as follows. Referring to FIG. 3, the semiconductor material is used as a substrate or wafer 2000. For example, a single crystal silicon having a crystal orientation of < 10 0 > can be used as the wafer 2 in the embodiment of the present invention. Then, an isolation region such as a shallow trench isolation region (STI) is first fabricated in the wafer 200 using a known technique. Generally, shallow trenches are formed in the wafer by lithography and etching, and then backfilled into the shallow trenches with a chemical vapor deposition oxide layer. In addition, other barriers can also be used

548819 V. Description of the invention (6) ^ Isolation area is produced by separation technology.

For example, an emulsification region can use LOCOS or other related field oxygen. ^ 纟 77 &,,, L. Chemical, edge, and edge regions are formed on the wafer as a component. The insulation between the fields is ArT_; 丄 um d ^ & In general, lithography silicon and oxygen porphyries can be etched by lithography and etching technology-< A wide A recognition door. After the η emulsified hard-bonded layer, a field oxidation region is formed by an oxidation process on the wafer 200 ^ L + ^ After the formation, the above silicon nitride layer is removed by hot phosphoric acid, and the oxidation is removed by hydrofluoric acid. Silicon layer. Next, a silicon oxide layer 205 is formed on the wafer 2000 as a gate oxide layer. This oxygen & silicon layer is generally formed by a thermal oxidation method, and the process temperature is about 700 to 1 1 0 0. (: After the Fu Shi Λ ΛΑ c Λ ★ The thickness of the gate y is about 50 to 200 angstroms, of course, the general technical Shikou chemical vapor deposition method below the pn Q reaches the silicon layer 2 0 5. Still see the figure -Females can also form a gate oxide structure using 1 E0S as a reactant. Using traditional technical patterns, the gate structure can include a polycrystalline stone layer on top of the Japanese yen and deposited on the stone oxide layer. On the layer 203, the polycrystalline crystalline layer 2 is formed by a chemical vapor deposition method (CVD), and the thickness is about 1000 angstroms. Other structures such as ion implantation The method of forming a doped region or a lightly doped drain (LDD) or P 糸 between sidewalls is not the focus of the present invention, so it will not be described in detail. The poles 2 3 0 and the source 2 2 0 can be implanted by ions. The technology is formed in the wafer 2000. In the case of NMOS, phosphorus or arsenic ions can be implanted into the above-mentioned doped region, with a thickness of about 1 E 丨 2 to 5 E1 5 atoms / cm 2. The implanted ions are then driven in by a heat treatment at a temperature between 700 ° C and 1000 ° C. After completion, a photoresist is applied, Then a lithography process is used to form a pattern 26 covering the surface of the wafer 2000, which includes the drain electrode 23 exposed in the opening, and avoiding the area where the contact perforation will be made. Implantation with ion implantation technology P type

Page 9 548819 V. Description of the invention ⑺ ... Ion-doped ions are implanted into the substrate through the above-mentioned openings to form a lightly doped P-type ion-doped region 2 50 located below the drain. The ion concentration in this region is appropriate (higher than that of the substrate), which is sufficient to reduce the breakdown voltage of the p-η junction. As a general example, boron can be used as a dopant at a concentration of about 1 E 12 to 5 E 1 5 atoms / cm 2. After that, the photoresist is removed 2 600.

As shown in FIG. 4, an insulating layer 2 6 5 such as an oxide layer, Bpsg, PSG, lice-forming layer, or the like is successively deposited on the transistor. For subsequent electrical contact with the transistor, one of the methods is to use-contact; a hole (ContaCt h〇1-e) 2 2 5 is used as a connection, a contact hole 225 is formed using Ξ and an etching process in In the insulating layer 265. It is worth noting that the lightly doped p-type 'ion-doped' shadows do not overlap with each other. Finally, the structure is shown in FIG. 2 as shown in FIG. 2. The structure of the power-receiving power in the contact wearer, including the transistor (cascade) above, has slight ions. It is located below the series connection and offset from the contact perforation. The area is only applied to the drain current. Please refer to Figure 5. This figure taps the surface capacitors to reduce the surface electrostatic discharge. Generally, when the human body touches and connects the instrument, it does not exceed 2KV, but for the connection of the instrument; the static electricity generated when the human body touches the body, so the Emperor ’s #electricity is not exceeded without electrostatic discharge. 〇V, the road is damaged, so it must be used to protect the internal electrician with an electric discharge protection circuit in both cases.

548819 V. Description of Invention (8) 'Circuit. The invention has the characteristics of easy implementation and improvement of electrical properties. Although the present invention is described by taking NMOS as an embodiment, those skilled in the art will know that the present invention can also be applied to PMOS by changing the above-mentioned doped ion type. Although the present invention is explained as above with a preferred embodiment, it is not intended to limit the spirit and the inventive entity of the present invention to only this embodiment, and those skilled in the art will not depart from the spirit of the present invention. When some modifications can be made, the scope of patent protection depends on the scope of the attached patent application and its equivalent fields.

Page 11 548819 Brief description of the drawings Brief description of the drawings: Figure 1 shows a sectional view of the prior art electrostatic discharge protection circuit. FIG. 2 is a cross-sectional view of an electrostatic discharge protection circuit according to the present invention. Figure 3 is a cross-sectional view of a slightly doped region formed under the electrode of the present invention. Figure 4 is a cross-sectional view of a contact via formed according to the present invention. Figure 5 shows the electrostatic discharge situation when the human body touches and connects the instrument. Drawing number comparison wafer 1 0 0 Gate 1 1 0 Contact hole 11 5 'Source 1 2 0 Drain 1 3 0 Insulating layer 1 4 0 P-type doped region 1 5 0 Wafer 2 0 0 Gate 2 1 0 Contact hole 2 2 5 Source 2 2 0 Drain 2 3 0 Insulating layer 2 4 0 P-type doped region 2 50

Page 12

Claims (1)

548819 6. Scope of patent application Patent scope of application: 1. Structure of an electrostatic discharge (ESD) protection circuit. The first conductivity type transistor includes an ion-doped drain and source electrodes having the first conductivity type. It is formed in the second conductive type well. The drain and source mentioned above contain a relatively dense ion dopant of the first conductive type. The insulating layer covers the above-mentioned transistor and includes a conductive material filled in the insulating layer. In the contact vias; a relatively lightly doped second conductive type ion-doped region is formed just below the drain electrode and is offset from the contact vias to reduce the junction breakdown voltage, the lightly doped The concentration of the ion-doped region of the second conductivity type can reduce the junction breakdown voltage to allow more current to be discharged through this. 2. The structure of the electrostatic discharge protection circuit according to item 1 of the patent application scope, wherein the first conductive type transistor described above includes NMOS. 3. For the structure of the electrostatic discharge protection circuit according to item 2 of the scope of patent application, wherein the first conductive type ions include N-type ions. 4. If the structure of the electrostatic discharge protection circuit in item 3 of the patent application scope, wherein the above N-type ions include arsenic. 5. If the structure of the electrostatic discharge protection circuit in item 3 of the patent application scope, 548819 6. Scope of patent application The above-mentioned N-type ions contain phosphorus. 6. If the structure of the electrostatic discharge protection circuit according to item 2 of the patent application scope, wherein the above-mentioned second conductive type ions include P-type ions. 7. The structure of the electrostatic discharge protection circuit according to item 6 of the patent application, wherein the above-mentioned P-type ions include boron. 8. The structure of the electrostatic discharge protection circuit according to item 1 of the patent application, wherein the first conductive type transistor mentioned above includes PMOS. 9. The structure of the electrostatic discharge protection circuit according to item 8 of the patent application, wherein the first conductive type ion includes a P-type ion. 10. The structure of the electrostatic discharge protection circuit according to item 9 of the scope of patent application, wherein the above-mentioned P-type ions include boron. 1 1. The structure of the electrostatic discharge protection circuit according to item 8 of the patent application & sect, wherein the above-mentioned second conductivity type ions include N-type ions. 1 2. The structure of the electrostatic discharge protection circuit according to item 11 of the scope of patent application, wherein the above-mentioned N-type ions include thallium. 1 3. If the structure of the electrostatic discharge protection circuit in item 11 of the scope of patent application, 548819 6. The above-mentioned N-type ions in the scope of patent application contain phosphorus. 14. The structure of the electrostatic discharge protection circuit according to item 1 of the scope of patent application, wherein the concentration of the drain ion of the first conductive type ion doping is 1 E 1 2 to 5E 15 atoms / cm 2. 15. According to the structure of the electrostatic discharge protection circuit in the first patent application scope, wherein the ion concentration in the lightly doped second conductive type ion-doped region is 1 E 1 2 to 1 E1 5 atoms / cm 2. Page 15