CN1209799C - Method of etching silicon in high ratio between depth and width - Google Patents
Method of etching silicon in high ratio between depth and width Download PDFInfo
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- CN1209799C CN1209799C CN 03104779 CN03104779A CN1209799C CN 1209799 C CN1209799 C CN 1209799C CN 03104779 CN03104779 CN 03104779 CN 03104779 A CN03104779 A CN 03104779A CN 1209799 C CN1209799 C CN 1209799C
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Abstract
The present invention relates to a method of etching silicon in high ratio between depth and width. The present invention uses a high-density plasma etching system of an STS multiplex ICP produced by an English STS company using a two way gas automatic switching function. The present invention uses the following process conditions: ion source power is 600W; the power of a table for supporting sheets is within 12 to 14W; etching gas flow rate is 95 sccm, and etching time is within 13 to 15 seconds; passivation gas flow rate is 95 sccm, and passivation time is within 9 to 11 seconds; the overlapping time of etching and passivation is 0.5 second; reaction pressure is within 18 to 36mTorr; an etching sample is a silicon slice with the diameter of 100 millimeters; an etching mask is common positive photoresist. The present invention solves the international problem that the etching speed is reduced by narrowing groove width in the process of silicon deep etching, enables a device structure of a complex picture and a comb picture to implement by the technology of the etching silicon in high ratio between depth and width, and provides an effective and feasible processing means for manufacturing MEMS devices. The present invention can be widely used in the technical field of microelectronic machinery.
Description
Technical field: the present invention relates to silicon microelectromechanical systems (MEMS) technical field, relate in particular to a kind of silicon of high aspect ratio deep etching method.
Background technology: microelectromechanical systems (MEMS) is the high-technology field that grew up in nearly ten years, and is particularly rapid based on the MEMS technical development of microelectronic technique.After the silicon of high aspect ratio lithographic technique was introduced microelectronic technique, a series of novel sensors and actuator structure were achieved, and make silicon technology become the main flow process technology of MEMS.
The silicon of all etching apparatus manufacturers manufacturings loses the hardware realization that system all is the silicon deep etching technology (ASE) of BOSCH company exploitation deeply at present.Reduce the problem of (lag effect) but the process results of all high-aspect-ratio etching systems all exists etch rate to narrow down with well width, width during less than 10 microns narrow groove structure etching problem particularly serious.For example: the STS MultiplexICP high-density plasma etching system of producing in Britain Surface Technology System company (be called for short STS company) (this model device account for global silicon lose deeply Equipment Market 80%) when using conventional deep etching technique that width is respectively 6 and 50 microns groove to carry out the degree of depth be 50 microns deep erosion, the degree of depth of 6 microns sipes has only about 40 microns, is about 20% with the depth difference of sipes.This problem has had a strong impact on the application of silicon of high aspect ratio lithographic technique, and therefore the design of a lot of micro-structurals can't realize.
Summary of the invention:
The object of the present invention is to provide and a kind ofly solve that etch rate in the silicon erosion process deeply narrows down with well width and the problem (lag effect) that reduces.
Silicon of high aspect ratio deep etching method of the present invention adopts the high-density plasma etching system with two-way gas automatic switching function, adopts following process conditions:
Ion source power: 600W wafer-supporting platform power: 12～14W
Etching gas flow: 95sccm etch period: 13～15 seconds
Passivation gas flow: 95sccm passivation time: 9～11 seconds
Etching and passivation overlapping time: 0.5 second
Reaction pressure: 18～36mTorr
Etching sample: 100 millimeters silicon chips of diameter
Etch mask: common positive photoresist.
Above-mentioned high-density plasma etching system with two-way gas automatic switching function is STS Multiplex ICP high-density plasma etching system or the ALCATEL-601 high-density plasma etching system that Britain STS company produces.
The factor that influences the etching result in ASE technology is a lot, as: ion source power, wafer-supporting platform power, gas flow, reaction pressure, etch period, passivation time, etching and passivation overlapping time etc.Because the influence of numerous factors, actual process results can greatly differ from each other with the result of conventional rational analysis usually.
The present invention is by inferring and the comparative analysis repeatedly of experimental result that through theoretical final optimization pass goes out process conditions of the present invention to above-mentioned factor.
The invention solves that etch rate in the silicon erosion process deeply narrows down with well width and this international difficult problem of reducing, the device architecture that adopts complex figure and broach figure can be realized by enough silicon of high aspect ratio lithographic techniques, for the manufacturing of MEMS device provides a kind of effective and feasible manufacturing process.
When adopting above-mentioned process conditions provided by the invention to carry out the deep erosion of 100 millimeters silicon chips of diameter, etch rate is that per minute about 1.5 microns (relevant with the aperture area of etching), groove widths are respectively less than 10 microns and 50 microns or wideer, that etching depth is etching depth when being not more than 80 microns gap less than 5%.
The effect comparison of the present invention and prior art as depicted in figs. 1 and 2.Fig. 1 is the process results photo of conventional high-aspect-ratio silicon etching, the gap about 20% of etching depth when groove width is respectively 50 microns of 6 and 50 microns, etching depth; Fig. 2 adopts the silicon of process conditions of the present invention to lose photo as a result deeply, and groove width is respectively 6 and 50 microns, when etching depth is 60 microns, and the gap of etching depth is less than 5%.
Description of drawings:
The process results photo of the conventional high-aspect-ratio silicon etching of Fig. 1
Fig. 2 adopts the silicon of process conditions of the present invention to lose photo as a result deeply
Embodiment:
Have in the high-density plasma etching system (as: ALCATEL-601) of two-way gas automatic switching function at STS Multiplex ICP high-density plasma etching system or other, the etching depth in the time of just can realizing narrow groove by condition of the present invention lowers with gap with the etching depth of the sipes under the condition.
The present invention adopts the big silicon of the first in the world to lose the STS MultiplexICP high-density plasma etching system that device fabrication merchant Britain STS company produces deeply, according to process conditions of the present invention, carry out the deep erosion of 100 millimeters silicon chips of diameter, etch rate is about 1.5 microns of per minutes (relevant with the aperture area of etching), groove width is respectively 6 and 50 microns or gap wideer, etching depth when etching depth is 60 microns less than 5%, sees Fig. 2.
Claims (3)
1, a kind of silicon deep etching method adopts the high-density plasma etching system with two-way gas automatic switching function, it is characterized in that adopting following process conditions:
Ion source power: 600W wafer-supporting platform power: 12～14W
Etching gas flow: 95sccm etch period: 13～15 seconds
Passivation gas flow: 95sccm passivation time: 9～11 seconds
Etching and passivation overlapping time: 0.5 second
Reaction pressure: 18～36mTorr
Etching sample: 100 millimeters silicon chips of diameter
Etch mask: common positive photoresist.
2, silicon deep etching method as claimed in claim 1 is characterized in that described high-density plasma etching system with two-way gas automatic switching function is the STS Multiplex ICP high-density plasma etching system that Britain STS company produces.
3, silicon deep etching method as claimed in claim 1 is characterized in that described high-density plasma etching system with two-way gas automatic switching function is an ALCATEL-601 high-density plasma etching system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03104779 CN1209799C (en) | 2003-02-28 | 2003-02-28 | Method of etching silicon in high ratio between depth and width |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03104779 CN1209799C (en) | 2003-02-28 | 2003-02-28 | Method of etching silicon in high ratio between depth and width |
Publications (2)
| Publication Number | Publication Date |
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| CN1431686A CN1431686A (en) | 2003-07-23 |
| CN1209799C true CN1209799C (en) | 2005-07-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 03104779 Expired - Fee Related CN1209799C (en) | 2003-02-28 | 2003-02-28 | Method of etching silicon in high ratio between depth and width |
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| CN (1) | CN1209799C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102800567A (en) * | 2012-08-27 | 2012-11-28 | 中国科学院苏州纳米技术与纳米仿生研究所 | Deep silicon etching method |
| CN101928941B (en) * | 2009-06-23 | 2014-09-03 | 中微半导体设备(上海)有限公司 | Reactive ion etching method for etching silicon |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3858888B2 (en) * | 2003-12-02 | 2006-12-20 | ソニー株式会社 | Etching method and semiconductor device manufacturing method |
| CN100435272C (en) * | 2005-07-01 | 2008-11-19 | 北京大学 | Method for protecting etched structure in induction coupling plasma etching |
| CN101121499B (en) * | 2006-08-09 | 2010-04-21 | 探微科技股份有限公司 | Deeply etching method |
| CN102031525B (en) * | 2009-09-29 | 2014-02-12 | 中微半导体设备(上海)有限公司 | Method for etching deep through silicon via (TSV) |
| CN102431960A (en) * | 2011-12-07 | 2012-05-02 | 华中科技大学 | Silicon through hole etching method |
| CN103950887B (en) * | 2014-04-09 | 2016-01-20 | 华中科技大学 | A kind of dark silicon etching method |
| CN111228643A (en) * | 2020-02-12 | 2020-06-05 | 成都工业学院 | Hollow microneedle array device and manufacturing method thereof |
-
2003
- 2003-02-28 CN CN 03104779 patent/CN1209799C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101928941B (en) * | 2009-06-23 | 2014-09-03 | 中微半导体设备(上海)有限公司 | Reactive ion etching method for etching silicon |
| CN102800567A (en) * | 2012-08-27 | 2012-11-28 | 中国科学院苏州纳米技术与纳米仿生研究所 | Deep silicon etching method |
| CN102800567B (en) * | 2012-08-27 | 2014-09-03 | 中国科学院苏州纳米技术与纳米仿生研究所 | Deep silicon etching method |
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| CN1431686A (en) | 2003-07-23 |
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