CN1208780C - Non-volatile memory circuit - Google Patents

Abstract

The invention provides a read-only memory with a plurality of memory cell blocks, wherein each memory cell block comprises a main bit line, a grounding bit line and a plurality of memory cells for storing data, the read-only memory at least comprises a plurality of upper selection transistors for selecting from the memory cell blocks connected to the main bit line and a plurality of lower selection transistors for selecting from the memory cell blocks connected to the grounding bit line, and the upper selection transistors and the lower selection transistors sandwich the memory cell blocks.

Description

non-volatile memory circuit

technical field

The present invention relates to a structural layout of a semiconductor integrated circuit, more particularly to a structural layout of a block selection area of a high-density non-volatile memory circuit.

Background technique

Non-volatile read-only memory is widely used in computers and microprocessor systems for permanent storage of data. For data or programs that need to be reused, the production of read-only memory often involves many complicated steps and consumes a lot of manufacturing In addition, it also requires expensive machines and materials to complete. Therefore, usually consumers will first define the data to be stored in the read-only memory, and then send it to the factory to write in the read-only memory.

Most of the read-only memories usually have little difference in structure, the main difference lies in the stored data, therefore, the general manufacturing process of read-only memory factories is that read-only memory components are usually first manufactured to the stage of writing data , and then these semi-finished products are followed by data writing and subsequent manufacturing processes after consumers decide to store data.

Traditionally, the memory cell of a read-only memory is made of a metal oxide semiconductor field-effect transistor (MOSFET), and each memory cell is used to store digital data "0" or "1". In the process of writing data in the read-only memory (Mask ROMs), first select the metal oxide semiconductor field effect transistors to be encoded, and then perform impurity ion implantation on the channel regions of these selected metal oxide semiconductor field effect transistors to change the start When adding a 5 volt bias to these transistors, the transistors that can be turned on can be assumed to represent the digital data stored as "0", while the digital data stored in the non-conductive memory cell transistors is "1" .

Referring to FIG. 1, it is a partial structure layout diagram of a read-only memory array, wherein the vertical part is a buried bit line 101, which is formed by an N-conductor type diffusion layer, and the horizontal part is a plurality of word lines 102, which are formed by polysilicon. The buried bit line 101 and the word line 102 are orthogonal to each other, and the source and drain of the memory cell transistor 103 are formed at the intersection of the bit line and the word line, and the channel region is located between the two intersections, and the memory cell transistor 103 It can be encoded according to the technology of implanting impurity ions into the channel region according to whether to store data, and then use the preset gate voltage to turn on the memory cell transistor 103, and judge whether the stored data is stored according to whether the memory cell transistor 103 is turned on or not. data of.

In addition, selection blocks 104 and 105 are also shown in this figure, wherein selection block 104 is an upper selection block and selection block 105 is a lower selection block, and each of the upper selection block and the lower selection block includes two selections. The bit lines 106, 107, 108 and 109, the upper selection bit lines 106, 107 intersect with the buried bit lines and the main bit lines 115, 116 and 117, and form the sources and drains of the upper selection transistors 110 and 112 at the intersections; The lower selection bit lines 108, 109 intersect with the buried bit line and the ground bit line 118 and 119, and form the source and drain electrodes of the lower selection transistors 113 and 114 at the intersection. When reading the data in the memory cell transistor 103, Apply a high voltage on the upper selection bit line 106 and the lower selection bit line 108 to turn on the upper selection transistor 110 and the lower selection transistor 113 to form a current path starting from the main bit line 116 through the upper selection transistor 110 and passing through the buried bit line 120 After the memory cell transistor 103 is connected, the buried bit line 121 and the lower selection transistor 113 are connected to the ground bit line 119 to complete the reading operation.

However, there is a major disadvantage in the structure layout described above, that is, impurity ion implantation in the channel region is also required in the upper selection block and the lower selection block to change the starting voltage of the unused selection transistor, Let this part of the selection transistor be always closed (non-conducting current) during operation. Referring to FIG. In the manufacture of read-only memories, P-type substrates are usually used, while the buried bit lines, main bit lines and ground bit lines are N-type, and P-type impurities are used to perform ion implantation in the channel region of the selection transistor. , Overlapping often occurs, resulting in a decrease in the N-type concentration of the drain/source of the select transistor for impurity ion implantation, and an increase in the leakage current generated by the P-type substrate, and under this structural layout, due to Part of the main bit line and the ground bit line overlap during impurity ion implantation, so that as long as the main bit line 116 has a potential, a large amount of substrate leakage current will be generated.

Contents of the invention

Along with the problems caused by the above-mentioned structural layout, the main purpose of the present invention is to provide a read-only memory with a new structural layout design. It is not involved in the implantation, so the overlay situation does not occur. In other words, the main bit line and the ground bit line will not be affected by the impurity ion implantation and cause a large increase in substrate leakage current.

In order to achieve the above-emphasized purpose, the present invention provides a non-volatile memory circuit composed of a plurality of basic memory circuit units on a semiconductor substrate. The basic memory circuit unit includes: four buried The bit lines are formed on the substrate, respectively the first, second, third and fourth; a plurality of word lines, the plurality of word lines intersect with the four parallel buried bit lines, and are arranged parallel to each other in the row direction The memory cell transistor array, the transistor source and the drain are formed at the intersections of the four parallel buried bit lines and the plurality of word lines to form the memory cell transistor array, and the intersecting points are the channel lengths of the memory cell transistors, The gate of the memory cell transistor is connected to the word line; a buried main bit line with two terminals is formed on the substrate independently of the four parallel buried bit lines, wherein the first terminal of the buried main bit line is continuous with the word line in a straight line direction The first ends of the second buried bit lines are separated by the first space, and the second ends of the buried main bit lines are connected to the first ends of the fourth buried bit lines in a straight line direction, and the second ends of the buried bit lines are separated therebetween. spaced apart; a buried ground bit line having two ends is formed on the substrate independently of the four parallel buried bit lines, wherein the first end of the buried ground bit line is continuous with the fourth buried bit line in a straight line direction The second end is separated by a third space, and the second terminal of the buried ground bit line is connected to the second end of the second buried bit line in the next non-volatile memory circuit unit, and the second end of the buried ground bit line is separated by a fourth The cells are separated from each other; two upper selection bit lines parallel to each other in the row direction are respectively the first and second, and the first upper selection bit line crosses the first cell and the third buried position in the row direction line and the buried main bit line, wherein the first end intersection of the first upper select bit line and the main bit line, and the first end cross point of the second buried bit line respectively form the source and drain of the select transistor And take the first space as the channel region; the second upper selection bit line crosses the second and third buried bit lines and the second space in a row direction, wherein the second upper selection bit line and the second space The second terminal crossing point of the main bit line and the first terminal crossing point of the fourth buried bit line respectively form the source and the drain of the selection transistor and use the second interstices as the channel region; and two rows parallel to each other The lower selected bit lines in the direction are respectively the first and the second, and the first lower selected bit line straddles the first and second buried cells in the third cell and the next non-volatile memory circuit unit in a row direction. bit line, wherein the first end intersection of the first lower selection bit line and the ground bit line, and the second end intersection of the fourth buried bit line respectively form the source and drain of the selection transistor and the third The interspace is the channel region; the second lower selection bit line crosses the ground bit line and the first buried bit line and the fourth interspace in the next non-volatile memory circuit unit in the row direction, wherein the second lower selection bit line The second end intersection of the selection bit line and the ground bit line, and the second end intersection of the second buried bit line in the next non-volatile memory circuit unit respectively form a source and a drain of a selection transistor And the fourth compartment is used as the channel area.

In the above non-volatile memory circuit, the semiconductor substrate is a P-type substrate.

In the above non-volatile memory circuit, the semiconductor substrate is an N-type substrate.

In the above non-volatile memory circuit, the buried bit line and the main bit line are made of N+ buried diffusion layer.

In the above non-volatile memory circuit, the buried bit line and the main bit line are made of P+ buried diffusion layer.

In the above non-volatile memory circuit, the upper selection bit line and the lower selection bit line are sandwiched between the memory cell transistor array.

In the above-mentioned non-volatile memory circuit, the select transistor and the memory cell transistor are both planar metal-oxide-semiconductor transistors.

In the above-mentioned non-volatile memory circuit, the address of the memory cell transistor is determined by the upper selection bit line and the lower selection bit line to determine the column address of the selected memory cell transistor, and the multiple word lines determine the column address of the selected memory cell transistor.

In the above-mentioned non-volatile memory circuit, the data stored in the memory unit transistor is recorded by implanting impurity ions into the channel region to define whether the memory unit transistor is turned on or not.

In the above non-volatile memory circuit, the word line, the upper selection bit line and the lower selection bit line are composed of polysilicon.

The present invention provides a read-only memory with a plurality of memory cell blocks, and each memory cell block includes a master bit line, a ground bit line and a plurality of memory cells for storing data, and the read-only memory including at least a plurality of upper selection transistors for selecting from a plurality of memory cell blocks connected to a main bit line, and a plurality of lower selection transistors for selecting from a plurality of memory cell blocks connected to a ground bit line , and the upper selection transistor and the lower selection transistor sandwich a plurality of memory cell blocks in the middle in the form of a sandwich, and the original selection transistor layout is rotated by 90 degrees. Through such a new circuit design layout, no need Impurity ion implantation is performed on the main bit line and the ground bit line to form circuit isolation, so that a large amount of substrate leakage current that may be generated in the previous technology can be reduced.

Description of drawings

The preferred embodiments of the present invention will be described in more detail with the help of the following figures in the following explanatory texts, wherein for the convenience of description, the same numbers shown in each figure represent the same devices.

Fig. 1 shows the circuit structure layout diagram of a traditional planar read-only memory array;

Fig. 2 shows the layout diagram of the circuit structure of the planar read-only memory array according to the present invention; and

FIG. 3 is a comparison diagram of leakage current between a conventional ROM circuit layout and the ROM circuit layout according to the present invention.

Description of drawing number comparison:

101 Buried bit lines 102 Multiple character lines

103 memory cell transistors 104, 105 selection blocks

106, 107 select the bit line 108, 109 select the bit line

110, 112 upper selection transistors 113, 114 lower selection transistors

115, 116 and 117 main bit line 118, 119 ground bit line

120 buried bit lines 130 to 137 blocks

201 and 202 upper selection bit lines 203 and 204 lower selection bit lines

206,207 select the transistor 208,209 select the transistor

220, 222 squares BL1-BLn buried bit line

WL1-WLn character line MBL1, MBL2 main bit line

GBL1, GBL2 ground ground wire

Detailed ways

Without limiting the spirit and scope of application of the present invention, the implementation of the present invention will be introduced below with an embodiment; those skilled in the art, after understanding the spirit of the present invention, can apply this method to various In the circuit structure layout of the read-only memory, with the circuit structure layout of the present invention, the main bit line and the ground bit line can not be affected by impurity ion implantation to form circuit isolation, so the substrate leakage current can be greatly reduced during circuit operation, The application of the present invention should not be limited to the embodiments described below.

FIG. 2 shows an embodiment of the present invention, which shows a layout diagram of a part of the circuit structure of a read-only memory. The layout diagram of the circuit structure at least includes a plurality of bit lines, a plurality of word lines, a plurality of main bit lines, a plurality of ground bit lines, 2 upper selection bit lines and 2 lower selection bit lines.

The read-only memory memory cell array in Fig. 2 comprises a plurality of mutually parallel and vertical placement by N-type buried bit lines BL1-BLn, a plurality of mutually parallel and horizontal placement of word lines WL1-WLn made of polysilicon, the word line WL1-WLn and the bit line BL1-BLn are perpendicular to each other. The read-only memory memory cell transistor stores data by implanting impurity ions in the channel region of the transistor. The intersection of the word line and the bit line is the source and the source of the memory cell transistor. drain. Each memory cell can be used to store digital data "0" or "1". In the process of writing data in the read-only memory (Mask ROMs), first select the metal-oxide-semiconductor field-effect transistor to be encoded, and then write these Impurity ion implantation is performed on the channel region of the selected metal-oxide-semiconductor field-effect transistors to change the starting voltage. When a bias voltage of 5 volts is added to these transistors, the transistors that can be turned on can be assumed to represent the stored digital data as "0". ", and the digital data stored in the non-conducting memory cell transistor is "1", the opposite assumption is also feasible; when reading the memory cell, first raise the word line voltage, generally 5 volts or less than 5 volts , and then the stored data can be read by sensing the bit line current.

The main bit lines are represented by MBL1-MBLn as N-type buried layers, and are parallel to the partially extended bit lines, and the two upper selection bit lines 201 and 202 are formed of polysilicon, and a plurality of upper selection transistors are formed therein and denoted by 206 and 207 represent two of them, wherein the gate of the upper selection transistor 206 is connected with the upper selection bit line 201, the gate of the upper selection transistor 207 is connected with the upper selection bit line 202, and the N-type buried layer of the main bit line is connected with the upper selection bit line 202. The drain of the upper selection transistor is formed at the intersection of the upper selection bit line formed by polysilicon, and the source of the upper selection transistor is formed at the intersection of the N-type buried layer of the bit line and the upper selection bit line formed by polysilicon. It is the channel area of the upper selection transistor; the ground bit line is represented by GBL1-GBLn as an N-type buried layer, and is parallel to the bit line extended downward, and the two lower selection bit lines 203 and 204 are formed of polysilicon, and have a lower selection Transistors are formed therein, two of which are represented by 208 and 209, wherein the gate of the lower selection transistor 208 is connected to the lower selection bit line 204, the gate of the lower selection transistor 209 is connected to the lower selection bit line 203, and the ground bit The intersection of the N-type buried layer of the line and the lower selection bit line formed by polysilicon forms the drain of the lower selection transistor, and the intersection of the N-type buried layer of the bit line and the lower selection bit line formed by polysilicon forms the source of the lower selection transistor, Between the source and the drain is the channel area of the lower selection transistor. To read the memory cell transistor 210, the signal coming in from the main bit line can enter the bit line of the memory cell array through the guidance of the upper selection transistor, and then pass through the lower selection transistor. The transistors are steered into the ground bit line, and the stored data is read out.

The regions represented by 220 and 222 in FIG. 2 are impurity ion implantation regions, which are mainly used for circuit isolation. Traditionally, P-type substrates are usually used in the manufacture of read-only memories, while buried bit lines, master bit lines and connection The status line is N-type, so P-type impurities are usually used for ion implantation in the channel region of the selection transistor. By increasing the initial voltage of the transistor, the selection transistor implanted with impurity ions will never be turned on during circuit operation. According to this The biggest difference between the invented circuit layout and the traditional circuit layout is that the impurity ion implantation area will not cover the main bit line and the ground bit line, so the main bit line and the ground bit line will not be affected by the impurity ion implantation. The impact causes the source/drain concentration of the select transistor to decrease, which causes a large increase in the substrate leakage current.

Referring to Fig. 3, it is a comparison diagram of the leakage current between the traditional ROM circuit layout and the ROM circuit layout according to the present invention. Under the operating voltage of 1.2 volts, the leakage current according to the ROM circuit layout of the present invention is only about 35 microamperes, while the leakage current of the traditional ROM circuit layout is 746 microamperes, which is about 20 times that of the present invention, so it can be clearly compared that the present invention can effectively reduce the leakage current.

The present invention is described above with a preferred embodiment, which is only used to help understand the implementation of the present invention, not to limit the spirit of the present invention, and those skilled in the art will not depart from the present invention after comprehending the spirit of the present invention Within the scope of the spirit of the present invention, some modifications and equivalent changes can be made, and the scope of patent protection should be determined by the scope of the claims of the present invention and its equivalent fields.

Claims (9)

1. one kind is positioned at the non-volatile memory circuit that combines with a plurality of basic storage circuit units on the semiconductor substrate, and wherein this basic storage circuit unit comprises:

Article four, parallel buried bit lines is formed on the substrate, and they are followed successively by the first, second, third and the 4th;

Many character line is arranged in mode parallel to each other, and wherein four parallel buried bit lines of these many character lines and this are perpendicular to one another and intersect;

The memory cell transistor array wherein forms transistor source and drain electrode on these four parallel buried bit lines and these many character line point of crossing, to form this memory cell transistor array, this memory cell transistor grid connects this character line;

Article one, the main bit line that buries that has two-end-point, it is independent of these four parallel buried bit lines and is formed on the substrate, wherein this buries between an end of main bit line and this second buried bit lines and has the first layout distance, and this buries between the other end of main bit line and the 4th buried bit lines and has the second layout distance;

Article one, what have two-end-point buries the ground connection bit line, it is independent of these four parallel buried bit lines and is formed on the substrate, wherein this buries between end of ground connection bit line and the 4th buried bit lines and has the 3rd layout distance, and this buries between the other end of ground connection bit line and second buried bit lines in the next basic storage circuit unit and has the 4th layout distance;

Article two, select bit line with parallel to each other the going up of these character lines, be followed successively by first and second, wherein this selects on first bit line to stride across this first layout, the 3rd buried bit lines and this bury main bit line, and this selects the point of crossing of bit line and this main bit line on first, form respectively with the point of crossing of this second buried bit lines and to select transistor source and drain electrode and be channel region with this first layout distance, and this selects on second bit line to stride across this second and the 3rd buried bit lines and this second layout distance, and this selects the point of crossing of bit line and this main bit line on second, form respectively with the point of crossing of the 4th buried bit lines and to select transistor source and drain electrode, and be channel region with this second layout distance; And

Article two, following selection bit line parallel to each other with these character lines, be followed successively by first and second, wherein select for this first time bit line to stride across first and second buried bit lines in the 3rd layout and next this basic storage circuit unit, select the point of crossing of bit line and this ground connection bit line this first time, form selection transistor source and drain electrode respectively with the point of crossing of the 4th buried bit lines, and be channel region with the 3rd layout distance, and select for this second time bit line to stride across first buried bit lines and the 4th layout in this ground connection bit line and next this basic storage circuit unit, select the point of crossing of bit line and this ground connection bit line this second time, form respectively with the point of crossing of this second buried bit lines in next this basic storage circuit unit and to select transistor source and drain electrode, and be channel region with the 4th layout distance.

2. non-volatile memory circuit as claimed in claim 1 is characterized in that: above-mentioned semiconductor substrate is a P type substrate.

3. non-volatile memory circuit as claimed in claim 1 is characterized in that: above-mentioned semiconductor substrate is a N type substrate.

4. non-volatile memory circuit as claimed in claim 1 is characterized in that: above-mentioned buried bit lines and main bit line are that to bury diffusion layer with N+ made.

5. non-volatile memory circuit as claimed in claim 1 is characterized in that: above-mentioned buried bit lines and main bit line are that to bury diffusion layer with P+ made.

6. non-volatile memory circuit as claimed in claim 1 is characterized in that: it is in the sandwich mode memory cell transistor array to be sandwiched in wherein with selecting bit line down that bit line is selected in above-mentioned going up.

7. non-volatile memory circuit as claimed in claim 1 is characterized in that: above-mentioned selection transistor and memory cell transistor all are the transistorized designs of plane metal-oxide semiconductor.

8. non-volatile memory circuit as claimed in claim 1, it is characterized in that: said memory cells transistor address, be to determine selected memory cell transistor craspedodrome address, and these many character lines determine selected memory cell transistor line address by selection bit line on this and the following bit line of selecting.

9. non-volatile memory circuit as claimed in claim 1 is characterized in that: above-mentioned character line, on select bit line to form by polysilicon with selecting down bit line.

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