CN1208780C - Non-volatile memory circuit - Google Patents
Non-volatile memory circuit Download PDFInfo
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- CN1208780C CN1208780C CN 01123811 CN01123811A CN1208780C CN 1208780 C CN1208780 C CN 1208780C CN 01123811 CN01123811 CN 01123811 CN 01123811 A CN01123811 A CN 01123811A CN 1208780 C CN1208780 C CN 1208780C
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Abstract
The present invention provides a read only memory which has a plurality of storage unit chunks, wherein each storage unit chunk comprises a main bit line, an earthed bit line and a plurality of storage units for storing data. The read only memory comprises at least a plurality of upper selection transistors for making selection from a plurality of storage unit chunks connected to the main bit line, and a plurality of lower selection transistors for making selection from a plurality of storage unit chunks connected to the earthed bit line, wherein the storage unit chunks are sandwiched between the upper selection transistors and the lower selection transistors.
Description
Technical field
The invention relates to a semiconductor integrated circuit structure layout, more particularly select the plot structure layout about the block of high density non-volatile memory circuit.
Background technology
Non-volatile ROM is used on computing machine and microprocessor system the usefulness as the permanent storage data widely, the data or the program that are repeated to use as need, the production ROM (read-only memory) usually comprises the step of many complexity and expends a large amount of manufacturing times, also require expensive board and material to finish in addition, therefore, usually the consumer can define the data that will be stored into ROM (read-only memory) earlier, after transfer to factory again and write in the ROM (read-only memory).
Structurally difference is little usually for most ROM (read-only memory); major different is stored data; therefore; the general flow process of making ROM (read-only memory) factory is; ROM module can be made earlier usually to the stage that writes data; these semi-manufacture then write data action and subsequent manufacturing processes again after the consumer determines required storing data then.
The storage unit of ROM (read-only memory) (memory cell) is by metal-oxide half field effect transistor (MOSFET) manufacturing traditionally, and each storage unit is used to store digital data " 0 " or " 1 ", ROM (read-only memory) (Mask ROMs) at ROM mask programmable read-only memory writes in the process of data, at first select the metal-oxide half field effect transistor that to encode, then the channel region of these selecteed metal-oxide half field effect transistors being carried out foreign ion implants to change start voltage, when 5 volts of addings are biased in these transistors, the transistor that can be unlocked can suppose to represent stored numerical data to be " 0 ", and still the stored numerical data of the memory cell transistor of not conducting is " 1 ".
With reference to figure 1 is the part-structure layout of a read-only memory array, wherein vertical component is a buried bit lines 101, be that diffusion layer by N conductor pattern is formed, horizontal component is many character lines 102, formed by polysilicon, buried bit lines 101 and character line 102 are mutually quadrature, and the source electrode of memory cell transistor 103 and drain electrode promptly are formed at bit line and character line intersection, and channel region is to be positioned between two confluces, and memory cell transistor 103 can be encoded according to the technology that whether will store data in wherein utilizing foreign ion to implant channel region, then utilize predefined grid voltage to open memory cell transistor 103, whether judge stored data according to the conducting of memory cell transistor 103.
In this figure, also show in addition and select block 104 and 105, wherein select block 104 to select block 105 for selecting block down for last selection block, last selection block respectively comprises two selection bit lines 106 with selecting block down, 107,108 and 109, on select bit line 106,107 and buried bit lines and main bit line 115,116 and 117 intersect, and form source electrode and the drain electrode of selecting transistor 110 and 112 in the confluce; Under select bit line 108,109 intersect with buried bit lines and ground connection bit line 118 and 119, and form down source electrode and the drain electrode of selecting transistor 113 and 114 in the confluce, when the data in the reading cells transistor 103, apply noble potential in last selection bit line 106 and the following bit line 108 of selecting, select transistor 110 and select transistor 113 down to open, form a current path, from the main bit line 116s by last selection transistor 110, behind buried bit lines 120 and memory cell transistor 103, again by buried bit lines 121 with select transistor 113 to be connected to ground connection bit line 119 down to finish and read action.
Yet; there is a main shortcoming in above-mentioned described topology layout; that is; last selection block with select down block also need carry out the channel region foreign ion to implant and change the selection transistor start voltage that need not use; allow the selection transistor of this part time all be (the not conducting electric current) of closing forever in operation; with reference to figure 1; square 130 to 137 among the figure is implanted the zone for impurity; promote this part and select transistorized start voltage; usually use P type substrate in the manufacturing ROM (read-only memory) traditionally; and buried bit lines; main bit line and ground connection bit line are the N type; and utilize p type impurity to select transistor channel district ion to implant; because when carrying out the foreign ion implantation; usually can cover (overlaping) situation; cause carry out selection transistor drain that foreign ion implants source electrode N type density loss; the leakage current that substrate is produced to the P type increases; and under this kind topology layout; because main bit line and ground connection bit line have part to cover (overlaping) situation when doing the foreign ion implantation; cause as long as main bit line 116 has current potential to exist, all can produce a large amount of substrate leakage currents.
Summary of the invention
The problem that is caused along with the said structure layout, fundamental purpose of the present invention provides a kind of ROM (read-only memory) of new construction topological design, under this topology layout design, main bit line and ground connection bit line do not participate in when doing the foreign ion implantation of selecting the transistor channel district, therefore covering situation does not take place, in other words, main bit line and ground connection bit line can not be subjected to the influence of foreign ion implantation and cause the substrate leakage current to roll up.
In order to reach the above-mentioned purpose of emphasizing, a kind of non-volatile memory circuit that combines with a plurality of basic storage circuit units on the semiconductor substrate that is positioned at provided by the invention, this basic storage circuit unit comprises: four buried bit lines that are parallel on the craspedodrome direction are formed on the substrate, are respectively the first, second, third and the 4th; Many character lines, four parallel buried bit lines of these many character lines and this are intersected, and are arranged on the line direction in mode parallel to each other; The memory cell transistor array, form transistor source and drain electrode with these four parallel buried bit lines and this many character line point of crossing, form this memory cell transistor array, be the channel length of this memory cell transistor between this point of crossing, this memory cell transistor grid connects this character line; Article one, the main bit line that buries that has two-end-point is independent of these four parallel buried bit lines and is formed on the substrate, wherein this first end points that buries main bit line is connected in first end points of this second buried bit lines with the craspedodrome direction, therebetween with first layout from, and this second end points that buries main bit line is connected in first end of the 4th buried bit lines with the craspedodrome direction, therebetween with second layout from; Article one, the ground connection bit line that buries that has two-end-point is independent of these four parallel buried bit lines and is formed on the substrate, wherein this first end points that buries the ground connection bit line be connected in the 4th buried bit lines with the craspedodrome direction second end therebetween with the 3rd layout from, and second end that second end points that this buries the ground connection bit line is connected in second buried bit lines in next this non-volatile memory circuit unit with the craspedodrome direction therebetween with the 4th layout from; Article two, going up on the line direction parallel to each other selected bit line, be respectively first and second, this selects on first bit line to stride across this first layout, the 3rd buried bit lines with the line direction and this buries main bit line, wherein this is selected the first end point of crossing of the first end point of crossing of bit line and this main bit line and this second buried bit lines to form respectively to select transistor source and drain electrode on first and is channel region with this first layout; This selects on second bit line to stride across this second, the 3rd buried bit lines and this second layout with the line direction, wherein this is selected the first end point of crossing of the second end point of crossing of bit line and this main bit line and the 4th buried bit lines to form respectively to select transistor source and drain electrode on second and is channel region with this second layout; And two following selection bit lines on the line direction parallel to each other, be respectively first and second, select for this first time bit line to stride across first and second buried bit lines in the 3rd layout and next this non-volatile memory circuit unit with the line direction, wherein select the second end point of crossing of the first end point of crossing of bit line and this ground connection bit line and the 4th buried bit lines to form respectively to select transistor source and drain electrode for this first time and be channel region with the 3rd layout; Select for this second time bit line to stride across first buried bit lines and the 4th layout in this ground connection bit line and next this non-volatile memory circuit unit with the line direction, wherein select this second end point of crossing of this second buried bit lines in this second end point of crossing of bit line and this ground connection bit line and this next this non-volatile memory circuit unit to form respectively to select transistor source and drain electrode for this second time and be channel region with the 4th layout.
Above-mentioned non-volatile memory circuit, wherein semiconductor substrate is a P type substrate.
Above-mentioned non-volatile memory circuit, wherein semiconductor substrate is a N type substrate.
Above-mentioned non-volatile memory circuit, wherein buried bit lines and main bit line are that to bury diffusion layer with N+ made.
Above-mentioned non-volatile memory circuit, wherein buried bit lines and main bit line are that to bury diffusion layer with P+ made.
Above-mentioned non-volatile memory circuit, wherein going up and selecting bit line is in the sandwich mode memory cell transistor array to be sandwiched in wherein with selecting bit line down.
Above-mentioned non-volatile memory circuit, wherein selecting transistor and memory cell transistor all is the transistorized designs of plane metal-oxide semiconductor.
Above-mentioned non-volatile memory circuit, wherein the memory cell transistor address be to determine selected memory cell transistor craspedodrome address by selection bit line on this and the following bit line of selecting, and these many character lines determines selected memory cell transistor line address.
Above-mentioned non-volatile memory circuit, wherein the stored data of memory cell transistor are to implant channel region via foreign ion to come define storage units transistor turns or not conducting to come record material.
Above-mentioned non-volatile memory circuit, character line wherein, on select bit line to form by polysilicon with selecting bit line down.
Provided by the invention one has a plurality of storage unit blocks, and each storage unit block comprises the ROM (read-only memory) of a main bit line and a ground connection bit line and a plurality of storage unit that are used for storing data, and this ROM (read-only memory) comprises a plurality of transistors of selecting that are used for doing from a plurality of storage unit blocks that are connected to main bit line selection at least, with a plurality of following selection transistors that are used for doing selection from a plurality of storage unit blocks that are connected to the ground connection bit line, select transistor AND gate to select transistor a plurality of storage unit blocks to be clipped in the middle down and wherein go up with the pattern of sandwich, wherein, and original selection transistor layout all revolved turn 90 degrees, via new circuit design layout like this, promptly do not need in main bit line and ground connection bit line carry out foreign ion implant to form circuit isolated, the issuable a large amount of substrate leakage currents of skill before therefore can reducing.
Description of drawings
Preferred embodiment of the present invention will be aided with following figure and do more detailed elaboration in comment backward, wherein for convenience of explanation for the purpose of, the device that the representative of same numbers shown in each figure is identical.
Figure 1 shows that traditional plane read-only memory array circuit structure layout;
Figure 2 shows that according to plane of the present invention read-only memory array circuit structure layout; And
Figure 3 shows that traditional read-only memory circuit layout with according to the leakage current comparison diagram of read-only memory circuit layout of the present invention.
Figure number is to as directed:
More than 102 character line of 101 buried bit lines
103 memory cell transistors 104,105 are selected block
Select bit line to select bit line 108,109 times on 106,107
Select transistor to select transistor 113,114 times on 110,112
115,116 and 117 main bit lines, 118,119 ground connection bit lines
120 buried bit lines, 130 to 137 squares
Select bit line 203 on 201 and 202 and select bit line 204 times
Select transistor to select transistor 208,209 times on 206,207
220,222 square BL1-BLn buried bit lines
WL1-WLn character line MBL1, the MBL2 main bit line
GBL1, GBL2 ground connection bit line
Embodiment
Do not limiting the following of spirit of the present invention and range of application, below promptly with an embodiment, introduce enforcement of the present invention; Be familiar with this field skill person, after understanding spirit of the present invention, but when adopting said method in various read-only memory circuit topology layout, by circuit structure layout of the present invention, main bit line and ground connection bit line are not implanted to form the isolated influence of circuit by foreign ion can, therefore can greatly reduce for the substrate leakage current in circuit operation, application of the present invention is as the embodiment that is not limited only to the following stated.
Shown in Figure 2 is one embodiment of the present of invention, is a part of circuit structure layout of a ROM (read-only memory) shown in the figure.This circuit structure layout comprises multiple bit lines, many character lines, many main bit lines, many ground connection bit lines, 2 last bit line and 2 following bit lines of selecting selected at least.
ROM storage unit array among Fig. 2 comprises that many are parallel to each other and vertically put by N type buried bit lines BL1-BLn, many are parallel to each other and level is put the character line WL1-WLn that is made by polysilicon, this character line WL1-WLn is mutually vertical with bit line BL1-BLn, the ROM storage unit transistor is implanted in the transistor channel district by foreign ion and stores data, and wherein the confluce of character line and bit line is the source electrode and the drain electrode of memory cell transistor.Each storage unit can be used to store digital data " 0 " or " 1 ", (Mask ROMs) writes in the process of data in ROM (read-only memory), at first select the metal-oxide half field effect transistor that to encode, then the channel region of these selecteed metal-oxide half field effect transistors being carried out foreign ion implants to change start voltage, when 5 volts of addings are biased in these transistors, the transistor that can be unlocked can suppose to represent stored numerical data to be " 0 ", and still the stored numerical data of the memory cell transistor of not conducting is " 1 ", and opposite hypothesis is also feasible; When reading memory cell, at first lift word line voltages, be generally 5 volts or be less than 5 volts, can come the stored data of interpretation by the sense bit line electric current then.
Main bit line is expressed as N type buried horizon with MBL1-MBLn, and be parallel to the upwards bit line of extension of part, article two, go up and select bit line 201 and 202 to form with polysilicon, have and a plurality ofly go up to select transistors to be formed at wherein and with wherein two of 206 and 207 representatives, wherein go up and select the grid of transistor 206 to be connected with last selection bit line 201, the grid of last selection transistor 207 is connected with last selection bit line 202, and the N type buried horizon of main bit line forms the selection transistor drain with the selection bit line confluce of going up that is formed by polysilicon, going up that the N type buried horizon of bit line and polysilicon form selects the bit line confluce to form the transistorized source electrode of selection, is between source electrode and drain electrode and selects the transistor channel district; The ground connection bit line is expressed as N type buried horizon with GBL1-GBLn, and be parallel to the bit line of part extension downwards, article two, select bit line 203 and 204 to form down with polysilicon, and select transistor to be formed under having wherein with 208 and 209 two of representing wherein, the grid of wherein selecting down transistor 208 be connected with selection bit line 204 down, select the grid of transistor 209 to be connected down with selecting bit line 203 down, and the N type buried horizon of ground connection bit line forms down the selection transistor drain with the following selection bit line confluce that is formed by polysilicon, the following selection bit line confluce that the N type buried horizon of bit line and polysilicon form forms down selects transistorized source electrode, be down between source electrode and drain electrode and select the transistor channel district, if want reading cells transistor 210, the signal of coming in from main bit line can enter the bit line of memory cell array via the transistorized guiding of last selection, again via under select transistorized guiding to enter the ground connection bit line, and read data on file.
In Fig. 2 220, the zone of 222 representatives is the foreign ion implantation region, mainly be as the isolated usefulness of circuit, usually use P type substrate in the manufacturing ROM (read-only memory) traditionally, and buried bit lines, main bit line and ground connection bit line are the N type, therefore adopt p type impurity to select transistor channel district ion to implant usually, by promoting transistorized start voltage, allow selection transistor conducting never when circuit operation of implanting via foreign ion, layout in a circuit according to the invention, can't cover main bit line and ground connection bit line with maximum different being in of traditional circuit layout in carrying out foreign ion implantation zone, therefore main bit line and ground connection bit line can not be subjected to the influence of foreign ion implantation and cause selection transistor source/drain electrode density loss, and cause the substrate leakage current to roll up.
Consult Figure 3 shows that traditional read-only memory circuit layout with according to the leakage current comparison diagram of read-only memory circuit layout of the present invention, under 1.2 volts operating voltage, leakage current according to read-only memory circuit layout of the present invention only is about 35 micromicroamperes, and the leakage current of traditional read-only memory circuit layout is 746 micromicroamperes, be about 20 times of the present invention, therefore can obviously compare the present invention can reduce leakage current effectively.
The present invention with preferred embodiment explanation as above; only be used to use and help to understand enforcement of the present invention; non-in order to limit spirit of the present invention; and be familiar with this field skill person after comprehension spirit of the present invention; in not breaking away from spiritual scope of the present invention; when the variation that can do a little change retouching and be equal to is replaced, its scope of patent protection when on claim scope of the present invention and etc. same domain decide.
Claims (9)
1. one kind is positioned at the non-volatile memory circuit that combines with a plurality of basic storage circuit units on the semiconductor substrate, and wherein this basic storage circuit unit comprises:
Article four, parallel buried bit lines is formed on the substrate, and they are followed successively by the first, second, third and the 4th;
Many character line is arranged in mode parallel to each other, and wherein four parallel buried bit lines of these many character lines and this are perpendicular to one another and intersect;
The memory cell transistor array wherein forms transistor source and drain electrode on these four parallel buried bit lines and these many character line point of crossing, to form this memory cell transistor array, this memory cell transistor grid connects this character line;
Article one, the main bit line that buries that has two-end-point, it is independent of these four parallel buried bit lines and is formed on the substrate, wherein this buries between an end of main bit line and this second buried bit lines and has the first layout distance, and this buries between the other end of main bit line and the 4th buried bit lines and has the second layout distance;
Article one, what have two-end-point buries the ground connection bit line, it is independent of these four parallel buried bit lines and is formed on the substrate, wherein this buries between end of ground connection bit line and the 4th buried bit lines and has the 3rd layout distance, and this buries between the other end of ground connection bit line and second buried bit lines in the next basic storage circuit unit and has the 4th layout distance;
Article two, select bit line with parallel to each other the going up of these character lines, be followed successively by first and second, wherein this selects on first bit line to stride across this first layout, the 3rd buried bit lines and this bury main bit line, and this selects the point of crossing of bit line and this main bit line on first, form respectively with the point of crossing of this second buried bit lines and to select transistor source and drain electrode and be channel region with this first layout distance, and this selects on second bit line to stride across this second and the 3rd buried bit lines and this second layout distance, and this selects the point of crossing of bit line and this main bit line on second, form respectively with the point of crossing of the 4th buried bit lines and to select transistor source and drain electrode, and be channel region with this second layout distance; And
Article two, following selection bit line parallel to each other with these character lines, be followed successively by first and second, wherein select for this first time bit line to stride across first and second buried bit lines in the 3rd layout and next this basic storage circuit unit, select the point of crossing of bit line and this ground connection bit line this first time, form selection transistor source and drain electrode respectively with the point of crossing of the 4th buried bit lines, and be channel region with the 3rd layout distance, and select for this second time bit line to stride across first buried bit lines and the 4th layout in this ground connection bit line and next this basic storage circuit unit, select the point of crossing of bit line and this ground connection bit line this second time, form respectively with the point of crossing of this second buried bit lines in next this basic storage circuit unit and to select transistor source and drain electrode, and be channel region with the 4th layout distance.
2. non-volatile memory circuit as claimed in claim 1 is characterized in that: above-mentioned semiconductor substrate is a P type substrate.
3. non-volatile memory circuit as claimed in claim 1 is characterized in that: above-mentioned semiconductor substrate is a N type substrate.
4. non-volatile memory circuit as claimed in claim 1 is characterized in that: above-mentioned buried bit lines and main bit line are that to bury diffusion layer with N+ made.
5. non-volatile memory circuit as claimed in claim 1 is characterized in that: above-mentioned buried bit lines and main bit line are that to bury diffusion layer with P+ made.
6. non-volatile memory circuit as claimed in claim 1 is characterized in that: it is in the sandwich mode memory cell transistor array to be sandwiched in wherein with selecting bit line down that bit line is selected in above-mentioned going up.
7. non-volatile memory circuit as claimed in claim 1 is characterized in that: above-mentioned selection transistor and memory cell transistor all are the transistorized designs of plane metal-oxide semiconductor.
8. non-volatile memory circuit as claimed in claim 1, it is characterized in that: said memory cells transistor address, be to determine selected memory cell transistor craspedodrome address, and these many character lines determine selected memory cell transistor line address by selection bit line on this and the following bit line of selecting.
9. non-volatile memory circuit as claimed in claim 1 is characterized in that: above-mentioned character line, on select bit line to form by polysilicon with selecting down bit line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01123811 CN1208780C (en) | 2001-07-30 | 2001-07-30 | Non-volatile memory circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01123811 CN1208780C (en) | 2001-07-30 | 2001-07-30 | Non-volatile memory circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1400608A CN1400608A (en) | 2003-03-05 |
| CN1208780C true CN1208780C (en) | 2005-06-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01123811 Expired - Fee Related CN1208780C (en) | 2001-07-30 | 2001-07-30 | Non-volatile memory circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1208780C (en) |
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2001
- 2001-07-30 CN CN 01123811 patent/CN1208780C/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| CN1400608A (en) | 2003-03-05 |
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Granted publication date: 20050629 Termination date: 20190730 |