CN1207784C - Cross stack type dual-chip package and its preparing process - Google Patents
Cross stack type dual-chip package and its preparing process Download PDFInfo
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- CN1207784C CN1207784C CNB011104899A CN01110489A CN1207784C CN 1207784 C CN1207784 C CN 1207784C CN B011104899 A CNB011104899 A CN B011104899A CN 01110489 A CN01110489 A CN 01110489A CN 1207784 C CN1207784 C CN 1207784C
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The present invention relates to a cross stacked type dual-chip encapsulation device and a manufacture method. Two semiconductor chips can be simultaneously encapsulated in a single encapsulation unit to provide double operating function or storage capacity. The dual-chip encapsulation technology is characterized in that a cross stacked dual-chip structure is adopted, a purpose-made lead wire frame is adopted as a chip carrier tool; the lead frame comprises a chip holder and a plurality of lead wires, wherein the chip holder is provided with a setting crystal part which is positioned on the upper part of the periphery, and a setting crystal part which is positioned on the lower part of the center; the lead wires are arranged on the side of the chip holder. The dual-chip encapsulation manufacture method has the following steps that the first semiconductor chip is arranged on the setting crystal part of the lower part of the chip holder, and thereby, the second semiconductor chip is arranged on the setting crystal part of the upper part of the chip holder. Thereby, the second semiconductor chip can form a cross stacked dual-chip architecture with the first semiconductor chip.
Description
Technical field
The present invention relates to a kind of semiconductor packaging, relate in particular to a kind of cross stack type dual-chip package and manufacture method.
Background technology
Multicore sheet encapsulation technology is in order to the semiconductor chip more than two or two be encapsulated in simultaneously among the same encapsulation unit, make single encapsulation unit can provide general single-chip package unit bigger operating function and memory capacity.General semiconductor storage, flash memory for example promptly adopts multicore sheet encapsulation technology that the memory chip more than two or two is encapsulated among the same encapsulation unit mostly, uses making single encapsulation unit that the memory capacity of several times can be provided.
Relevant patented technology for example includes United States Patent (USP) the 5th, 721, No. 452 " ANGULARLY OFFSET STACKED DIE MULTICHIP DEVICE ANDMETHOD OF MANUFACTURE ".This United States Patent (USP) technology has disclosed a kind of dual-chip package, is characterized in two semiconductor chips are placed on the lead frame with the stack manner that is an angular cross, and a pair of chip packaging unit is provided by this.
Yet above-mentioned United States Patent (USP) but has following shortcoming in practical application.First shortcoming support the bonding wire weldering tie region of the upper strata chip in the double-chip structure for it must adopt pillar (pillars), can make therefore that whole encapsulation process is rather complicated and increases manufacturing cost.Second shortcoming is not placed on the chip carrier for the upper strata chip in its double-chip structure, therefore makes chip have not good heat dissipation.The 3rd shortcoming is to paste by mucigel to be integral for two chips in its double-chip structure, therefore is easy to make chip to produce delamination, makes the encapsulation unit of finishing have not good quality and reliability.
Summary of the invention
In order to overcome the deficiencies in the prior art, the object of the present invention is to provide a kind of cross stack type dual-chip package and manufacture method, it can adopt pillar to support the bonding wire weldering tie region of the upper strata chip in the double-chip structure, use and simplify whole packaging technology, make packaging technology have more cost benefit.
Another object of the present invention is to provide a kind of cross stack type dual-chip package and manufacture method, it can make chip have better heat dissipation with chip placing on chip carrier.
Another object of the present invention is to provide a kind of cross stack type dual-chip package and manufacture method, two chips in the double-chip structure wherein can be pasted by mucigel and be integral, use the delamination problems that solves chip, make the encapsulation unit of finishing have better quality and reliability
For achieving the above object, the invention provides a kind of cross stack type dual-chip package, it comprises:
(a) lead frame, it comprises:
(a1) chip carrier, these chip carrier central authorities form a below chip-positioning part, and these relative its central authorities of chip carrier periphery upwards form a top chip-positioning part;
(a2) a plurality of lead-in wires, it is configured in the side of this chip carrier;
(b) one first semiconductor chip, it has a circuit face and an inverter circuit face; Wherein be formed with a plurality of outputs on the circuit face and go into weld pad; But not circuit face is then pasted the below chip-positioning part to this chip carrier;
(c) one second semiconductor chip, it has a circuit face and an inverter circuit face; Wherein be formed with a plurality of outputs on the circuit face and go into weld pad; But not circuit face is then pasted the top chip-positioning part to this chip carrier, makes this second semiconductor chip and this first semiconductor chip form a cross stack type dual-chip framework; And
(d) many bonding wires are electrically connected to corresponding lead-in wire respectively in order to weld pad is gone in the output on this first semiconductor chip and this second semiconductor chip.
The present invention also provides a kind of manufacture method of cross stack type dual-chip package, comprises following steps:
(1) a prefabricated lead frame, it comprises:
One chip carrier, these chip carrier central authorities form a below chip-positioning part, and these relative its central authorities of chip carrier periphery upwards form a top chip-positioning part;
A plurality of lead-in wires, it is configured in the side of this chip carrier;
(2) carry out one first and put brilliant program, use that one first semiconductor chip is placed on the below chip-positioning part of this chip carrier;
Wherein this first semiconductor chip has a circuit face and an inverter circuit face; Wherein be formed with a plurality of outputs on the circuit face and go into weld pad; But not circuit face is then pasted the below chip-positioning part to this chip carrier;
(3) carry out the first bonding wire program, use and utilize an assembly welding line that weld pad is gone in the output on this first semiconductor chip to be electrically connected to corresponding lead-in wire respectively;
(4) carry out one second and put brilliant program, use that one second semiconductor chip is placed on the top chip-positioning part of this chip carrier;
Wherein this second semiconductor chip has a circuit face and an inverter circuit face; Wherein be formed with a plurality of outputs on the circuit face and go into weld pad; But not circuit face is then pasted the top chip-positioning part to this chip carrier, makes this second semiconductor chip and this first semiconductor chip form a cross stack type dual-chip structure; And
(5) carry out the second bonding wire program, use and utilize an assembly welding line that weld pad is gone in the output on this second semiconductor chip to be electrically connected to corresponding lead-in wire respectively.
The present invention also provides the manufacture method of a cross stack type dual-chip package, comprises following steps:
(1) a prefabricated lead frame, it comprises:
One chip carrier, these chip carrier central authorities form a below chip-positioning part, and these relative its central authorities of chip carrier periphery upwards form a top chip-positioning part;
A plurality of lead-in wires, it is configured in the side of this chip carrier;
(2) form at least one below chip-positioning part that is opened on this chip carrier;
(3) carry out one first and put brilliant program, use that one first semiconductor chip is placed on the below chip-positioning part of this chip carrier;
Wherein this first semiconductor chip has a circuit face and an inverter circuit face; Wherein be formed with a plurality of outputs on the circuit face and go into weld pad; But not circuit face is then pasted the below chip-positioning part to this chip carrier;
(4) carry out the first bonding wire program, use and utilize an assembly welding line that weld pad is gone in the output on this first semiconductor chip to be electrically connected to corresponding lead-in wire respectively;
(5) carry out one second and put brilliant program, use the below chip-positioning part that one second semiconductor chip is placed in this chip carrier;
Wherein this second semiconductor chip has a circuit face and an inverter circuit face; Wherein be formed with a plurality of outputs on the circuit face and go into weld pad; But not circuit face is then pasted the top chip-positioning part to this chip carrier, makes this second semiconductor chip and this first semiconductor chip form cross stack type dual-chip knot frame; And
(6) carry out the second bonding wire program, use and utilize an assembly welding line that weld pad is gone in the output on second semiconductor chip to be electrically connected to corresponding lead-in wire respectively.
The characteristics of twin-core sheet encapsulation technology of the present invention are to adopt a kind of cross stack type dual-chip framework, and it adopts a special lead frame as chip carrier; The structure of this lead frame comprises a chip carrier and a plurality of lead-in wire; Wherein chip carrier has the below chip-positioning part that a top chip-positioning part and that is positioned at periphery is positioned at central authorities; And this lead-line configuration is at the side of chip carrier.Twin-core sheet encapsulation technology of the present invention is the below chip-positioning part that one first semiconductor chip is placed in chip carrier; And and then one second semiconductor chip is placed in the top chip-positioning part of chip carrier, forming one with first semiconductor chip intersects the double-chip structure that piles up by this.
Of the present inventionly have a mind to effect and be: dual-chip package of the present invention not be owing to need adopt pillar to support the bonding wire weldering tie region of the upper strata chip in the double-chip structure, therefore can make whole packaging technology more simplify and has a cost benefit.In addition and since the present invention with chip placing on chip carrier, therefore can and then make chip have better heat dissipation.Moreover, because two chips in the twin-core chip package of the present invention are not to paste by mucigel to be integral, therefore be difficult for producing the chip delamination, make the encapsulation unit of finishing at last have better quality and reliability.
Description of drawings
The present invention is described in detail below in conjunction with accompanying drawing:
Fig. 1 looks up structural representation, wherein shows the structure of the lead frame that the embodiment of the invention 1 is adopted;
Figure 1B shows the generalized section that lead frame shown in Figure 1 is cut open along the 1B-1B line;
Fig. 2 A looks up structural representation, and it first puts brilliant program in order to what show that the present invention carried out;
The generalized section of the packaging system shown in Fig. 2 B displayed map 2A;
Fig. 3 A looks up structural representation, and it second puts brilliant program in order to what show that the present invention carried out;
The generalized section of the packaging system shown in Fig. 3 B displayed map 3A;
Fig. 4 A looks up structural representation, its bonding wire program in order to show that the present invention carried out;
The generalized section of the packaging system shown in Fig. 4 B displayed map 4A;
Fig. 5 A looks up structural representation, shows that wherein lead frame that the embodiment of the invention 2 is adopted is equipped with semiconductor chip and finishes the structure of bonding wire;
The generalized section that embodiment shown in Fig. 5 B displayed map 5A cuts open along the 5B-5B line;
Fig. 6 looks up structural representation, shows that wherein lead frame that the embodiment of the invention 3 is adopted is equipped with semiconductor chip and finishes the structure of bonding wire;
Fig. 7 A looks up structural representation, wherein shows the structure of the lead frame that the embodiment of the invention 4 is adopted;
Fig. 7 B is the generalized section of the lead frame shown in Fig. 7 A;
Fig. 8 is the structural representation of looking up of lead frame embodiment 5 of the present invention;
Fig. 9 is the structural representation of looking up of lead frame embodiment 6 of the present invention.
Symbol description among the figure:
10 lead frames (leadframe)
11 support bars
12 chip carriers (die pad)
The top chip-positioning part of 12a chip carrier 12
The below chip-positioning part of 12b chip carrier 12
13 connecting rods
14 lead wire set
First group of lead-in wire of 14a
Second group of lead-in wire of 14b
15 openings
20,20 ', 20 " first semiconductor chips
The circuit face of 20a first semiconductor chip 20
The inverter circuit face of 20b first semiconductor chip 20
21 mucigels
22,22 ', 22 " export weld pad
30,30 ', 30 " second semiconductor chips
The circuit face of 30a second semiconductor chip 30
The inverter circuit face of 30b second semiconductor chip 30
31 mucigels
32,32 ', 32 " export weld pad
40 bonding wire groups
41 first assembly welding lines
42 second assembly welding lines
Embodiment
Below be conjunction with figs., the embodiment of detailed description twin-core sheet of the present invention encapsulation technology.What must at first note a bit is, these accompanying drawings are rough schematic view, and it only shows the assembly relevant with the present invention, and shown assembly is not to draw with actual number and dimension scale; Assembly layout during its concrete enforcement may be more complicated.
Please at first consult Fig. 1 and Figure 1B, twin-core sheet encapsulation technology of the present invention is to adopt special lead frame (leadframe) 10 as chip carrier, and its structure comprises: (i) support bar 11; The (ii) chip carrier 12 of rectangularity roughly, it has the below chip-positioning part 12b that a top chip-positioning part 12a and who is positioned at peripheral both sides is positioned at central authorities, and it is linked to support bar 11 by connecting rod 13; And a (iii) lead wire set 14, it is configured in the side of chip carrier 12, and directly is linked to support bar 11; It comprises first group of lead-in wire 14a and second group of lead-in wire 14b; Wherein first group of lead-in wire 14a is configured in the opposite end than long side of rectangular chip carrier 12, and second group of lead-in wire 14b then is configured in the opposite end of the shorter lateral sides of such of rectangular chip carrier 12.
In addition, Fig. 7 A and Fig. 7 B show another structure of lead frame 10, wherein the below chip-positioning part 12b with chip carrier 12 goes up at least one opening 15 of formation, produces delamination in order to prevent follow-up arrangement first semiconductor chip (be presented at Fig. 2 A and Fig. 2 B, its label is 20) thereon.In addition, the opening on the chip-positioning part 12b of this below also can select for use as shown in Figure 8 slotted eye 15 ', or the slotted eye group 15 who forms by a plurality of slotted eye as shown in Figure 9 ", still all can reach equal effect.
Please then consult Fig. 2 A and Fig. 2 B, next procedure is put brilliant program for carrying out one first, uses that one first semiconductor chip 20 is placed on the below chip-positioning part 12b of chip carrier 12; Wherein this first semiconductor chip 20 has a circuit face 20a and an inverter circuit face 20b; Wherein circuit face 20a is roughly rectangle, and it goes into weld pad 22 than being formed with a plurality of outputs on short side; But not circuit face 20b is then by a mucigel 21, elargol (silver epoxy) for example, and paste to the below chip-positioning part 12b of chip carrier 12.
Wherein, first semiconductor chip 20 can not be above the top chip-positioning part 12a (that is the circuit face 20a of first semiconductor chip 20 must be lower than the top chip-positioning part 12a of chip carrier 12) of chip carrier 12 with the sum total height of mucigel 21.
Then carry out the first bonding wire program (the first wire-bonding process), use and utilize the first assembly welding line 41 that weld pad 22 is gone in the output on first semiconductor chip 20 to be electrically connected in the lead wire set 14 first group lead-in wire 14a respectively.
Please then consult Fig. 3 A and Fig. 3 B, next procedure is put brilliant program for carrying out one second, uses second semiconductor chip 30 that a size is equated with first semiconductor chip 20 approximately and is placed on the top chip-positioning part 12a on the chip carrier 12; Wherein this second semiconductor chip 30 has a circuit face 30a and an inverter circuit face 30b; Wherein circuit face 30a is roughly rectangle, and it goes into weld pad 32 than being formed with a plurality of outputs on short side; But not circuit face 30b is then by a mucigel 31, elargol for example, and paste to the top chip-positioning part 12a of chip carrier 12.This puts crystal type can make second semiconductor chip 30 and first semiconductor chip 20 form the twin-core sheet framework of a cross stack type.
Above-mentioned second puts in the brilliant program, second semiconductor chip 30 wherein is roughly rectangle, and the length of its shorter lateral sides of such is less than the length of first semiconductor chip 20 than long side, but also can be shown in Fig. 5 A and Fig. 5 B second semiconductor chip 30 ' another embodiment greater than first semiconductor chip, 20 ' size, first semiconductor 20 ' be placed on the below chip-positioning part of chip carrier 12 wherein; This first semiconductor 20 ' have a circuit face and an inverter circuit face; Circuit face rectangle roughly wherein, and it is exported into weld pad 22 than being formed with several on the long side.
Please then consult Fig. 4 A and Fig. 4 B, next procedure is for carrying out one second bonding wire program (thesecond wire-bonding process), utilizes the second assembly welding line 42 to be electrically connected to second group of lead-in wire 14b in the lead wire set 14 respectively the output on second semiconductor chip 30 is gone into weld pad 32.
Shown in Fig. 5 A and Fig. 5 B, when first semiconductor chip 20 ' size less than 30 ' time of second semiconductor chip, only must reserve and can get final product at two chip chambers for the distance of 41 dozens of welderings of the first assembly welding line.And when first semiconductor chip 20 " size greater than second semiconductor chip 30 ", then can select configuration as shown in Figure 6 for use.
Follow follow-up processing step and comprise packing colloid canned program (encapsulation) and cut one way preface (singulation) that wherein the packing colloid canned program is in order to sealing semiconductor chips 20,30; Cutting the one way preface then is in order to provide other encapsulation unit with support bar 11 excisions.Because these a little processing steps are the existing technology that adopts, not therefore following will it not being described in further detail.
In addition, lead frame 10 chip form applicatory of the present invention, the square that in the various embodiments described above, is disclosed and square, rectangle and rectangle or square and the rectangular various collocation, the also collocation that can select other different geometries for use according to design, wafer cutting technique or other needs of integrated circuit.The intersection stack manner of its chip simultaneously except that the configuration shown in the various embodiments described above, also can be selected arbitrary chip wherein intersected in the mode of deflection one angle and pile up, and will still can reach equal effect.
Compared with prior art, the present invention not be owing to need adopt pillar to support the bonding wire weldering tie region of the upper strata chip in the double-chip structure, whole packaging technology is more simplified and had a cost benefit.In addition and since the present invention with chip placing on chip carrier, therefore can and then make chip have better heat dissipation.Moreover, because two chips in the twin-core chip package of the present invention are not to paste by mucigel to be integral, therefore be difficult for producing the chip delamination, make the encapsulation unit of finishing at last have better quality and reliability.
The above is preferred embodiment of the present invention only, is not in order to limit the scope of essence technology contents of the present invention.Essence technology contents of the present invention broadly is defined in claims, specification and Figure of description.Any technology entity or method that other people are finished; if with limited identical of claims of the present invention or do a kind of change of equivalence; for example opening on the chip-positioning part 12b of below or slotted eye are replaced with other difformity; or slotted eye group's arrangement position changed or the like, all will be regarded as being encompassed among protection scope of the present invention.
Claims (15)
1. a cross stack type dual-chip package, it comprises:
(a) lead frame, it comprises:
(a1) chip carrier, these chip carrier central authorities form a below chip-positioning part, and these relative its central authorities of chip carrier periphery upwards form a top chip-positioning part;
(a2) a plurality of lead-in wires, it is configured in the side of this chip carrier;
(b) one first semiconductor chip, it has a circuit face and an inverter circuit face; Wherein be formed with a plurality of outputs on the circuit face and go into weld pad; But not circuit face is then pasted the below chip-positioning part to this chip carrier;
(c) one second semiconductor chip, it has a circuit face and an inverter circuit face; Wherein be formed with a plurality of outputs on the circuit face and go into weld pad; But not circuit face is then pasted the top chip-positioning part to this chip carrier, makes this second semiconductor chip and this first semiconductor chip form a cross stack type dual-chip framework; And
(d) many bonding wires are electrically connected to corresponding lead-in wire respectively in order to weld pad is gone in the output on this first semiconductor chip and this second semiconductor chip.
2. packaging system according to claim 1 is characterized in that: the below chip-positioning part of this chip carrier is formed with at least one opening, produces delamination in order to prevent this first semiconductor chip.
3. packaging system according to claim 1 is characterized in that: the below chip-positioning part of this chip carrier is formed with at least one slotted eye, produces delamination in order to prevent this first semiconductor chip.
4. according to claim 1,2 or 3 described packaging systems, it is characterized in that: the inverter circuit face of this first semiconductor chip is to paste below chip-positioning part to this chip carrier by elargol.
5. according to claim 1,2 or described packaging system, it is characterized in that: the inverter circuit face of this second semiconductor chip is to paste top chip-positioning part to this chip carrier by elargol.
6. according to claim 1,2 or 3 described packaging systems, it is characterized in that: this bonding wire is a gold thread.
7. the manufacture method of a cross stack type dual-chip package comprises following steps:
(1) a prefabricated lead frame, it comprises:
One chip carrier, these chip carrier central authorities form a below chip-positioning part, and these relative its central authorities of chip carrier periphery upwards form a top chip-positioning part;
A plurality of lead-in wires, it is configured in the side of this chip carrier;
(2) carry out one first and put brilliant program, use that one first semiconductor chip is placed on the below chip-positioning part of this chip carrier;
Wherein this first semiconductor chip has a circuit face and an inverter circuit face; Wherein be formed with a plurality of outputs on the circuit face and go into weld pad; But not circuit face is then pasted the below chip-positioning part to this chip carrier;
(3) carry out the first bonding wire program, use and utilize an assembly welding line that weld pad is gone in the output on this first semiconductor chip to be electrically connected to corresponding lead-in wire respectively;
(4) carry out one second and put brilliant program, use that one second semiconductor chip is placed on the top chip-positioning part of this chip carrier;
Wherein this second semiconductor chip has a circuit face and an inverter circuit face; Wherein be formed with a plurality of outputs on the circuit face and go into weld pad; But not circuit face is then pasted the top chip-positioning part to this chip carrier, makes this second semiconductor chip and this first semiconductor chip form a cross stack type dual-chip structure; And
(5) carry out the second bonding wire program, use and utilize an assembly welding line that weld pad is gone in the output on this second semiconductor chip to be electrically connected to corresponding lead-in wire respectively.
8. manufacture method according to claim 7 is characterized in that: in step (2), the inverter circuit face of this first semiconductor chip is to paste below chip-positioning part to this chip carrier by elargol.
9. manufacture method according to claim 7 is characterized in that: in step (4), the inverter circuit face of this second semiconductor chip is to paste top chip-positioning part to this chip carrier by elargol.
10. manufacture method according to claim 7 is characterized in that: in step (3) and (5), this bonding wire is a gold thread.
11. the manufacture method of a cross stack type dual-chip package comprises following steps:
(1) a prefabricated lead frame, it comprises:
One chip carrier, these chip carrier central authorities form a below chip-positioning part, and these relative its central authorities of chip carrier periphery upwards form a top chip-positioning part;
A plurality of lead-in wires, it is configured in the side of this chip carrier;
(2) form at least one below chip-positioning part that is opened on this chip carrier;
(3) carry out one first and put brilliant program, use that one first semiconductor chip is placed on the below chip-positioning part of this chip carrier;
Wherein this first semiconductor chip has a circuit face and an inverter circuit face; Wherein be formed with a plurality of outputs on the circuit face and go into weld pad; But not circuit face is then pasted the below chip-positioning part to this chip carrier;
(4) carry out the first bonding wire program, use and utilize an assembly welding line that weld pad is gone in the output on this first semiconductor chip to be electrically connected to corresponding lead-in wire respectively;
(5) carry out one second and put brilliant program, use the below chip-positioning part that one second semiconductor chip is placed in this chip carrier;
Wherein this second semiconductor chip has a circuit face and an inverter circuit face; Wherein be formed with a plurality of outputs on the circuit face and go into weld pad; But not circuit face is then pasted the top chip-positioning part to this chip carrier, makes this second semiconductor chip and this first semiconductor chip form cross stack type dual-chip knot frame; And
(6) carry out the second bonding wire program, use and utilize an assembly welding line that weld pad is gone in the output on second semiconductor chip to be electrically connected to corresponding lead-in wire respectively.
12 manufacture methods according to claim 11 is characterized in that: in step (3), the inverter circuit face of this first semiconductor chip is to paste below chip-positioning part to this chip carrier by elargol.
13. manufacture method according to claim 11 is characterized in that: in step (5), the inverter circuit face of this second semiconductor chip is to paste top chip-positioning part to this chip carrier by elargol.
14. manufacture method according to claim 11 is characterized in that: in step (6), this bonding wire is a gold thread.
15. manufacture method according to claim 11 is characterized in that: the opening on the below chip-positioning part of this chip carrier is a slotted eye.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011104899A CN1207784C (en) | 2001-04-16 | 2001-04-16 | Cross stack type dual-chip package and its preparing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011104899A CN1207784C (en) | 2001-04-16 | 2001-04-16 | Cross stack type dual-chip package and its preparing process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1381892A CN1381892A (en) | 2002-11-27 |
| CN1207784C true CN1207784C (en) | 2005-06-22 |
Family
ID=4658628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011104899A Expired - Fee Related CN1207784C (en) | 2001-04-16 | 2001-04-16 | Cross stack type dual-chip package and its preparing process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1207784C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040108580A1 (en) * | 2002-12-09 | 2004-06-10 | Advanpack Solutions Pte. Ltd. | Leadless semiconductor packaging structure with inverted flip chip and methods of manufacture |
| JP3695458B2 (en) * | 2003-09-30 | 2005-09-14 | セイコーエプソン株式会社 | Semiconductor device, circuit board and electronic equipment |
| KR100904152B1 (en) * | 2006-06-30 | 2009-06-25 | 서울반도체 주식회사 | Leadframe having a heat sink supporting part, fabricating method of the light emitting diode package using the same and light emitting diode package fabricated by the method |
| US7816769B2 (en) * | 2006-08-28 | 2010-10-19 | Atmel Corporation | Stackable packages for three-dimensional packaging of semiconductor dice |
| CN102437147B (en) * | 2011-12-09 | 2014-04-30 | 天水华天科技股份有限公司 | Dense-pitch small-pad copper-line bonded intelligent card (IC) chip stacking packing piece and preparation method thereof |
| CN110120386B (en) * | 2018-02-05 | 2020-12-18 | 扬智科技股份有限公司 | Semiconductor packaging structure |
-
2001
- 2001-04-16 CN CNB011104899A patent/CN1207784C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1381892A (en) | 2002-11-27 |
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