CN1206839C - Reverse multiplexer circuit layer protecting and restoring method and device - Google Patents
Reverse multiplexer circuit layer protecting and restoring method and device Download PDFInfo
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Abstract
The present invention discloses a method and a device for protecting and restoring a reverse multiplexer circuit layer. In the method, the E1 transmission side of the reverse multiplexer generates and transmits bit error detection signals; when a calculated circuit bit error rate exceeds a given threshold, the receiving side of the E1 circuit generates circuit performance degradation information and feeds the circuit performance degradation information back to a transmission end, and the transmission end stops transmitting effective data and completely transmits the bit error detection signals; when the bit error rate obtained by the receiving side of the circuit meets the using requirement for the reverse multiplexer, the reverse multiplexer can automatically inform the transmission end to continue transmitting the effective data so as to reuse the E1 channel. The method not only can make full use of a transmission bandwidth, but also can decrease the using risk of the device and improve the transmission quality of the reverse multiplexer.
Description
Technical field:
The present invention relates to data communication technology field, particularly relate to and using many low speed passages to carry out the method and apparatus of in the long Distance Transmission of Ethernet data transmission channel being protected and being recovered.
Background technology:
Along with carrying out the increasing of information interchange demand between the great development of data communication and the computer, local area network technology develops rapidly; And Ethernet becomes most economical local area network technology easily with the various advantages of himself technology, becomes one of basic communications facility of office, school, company, group.But,, therefore only be applicable to local area network communication and can not be as the wide area network transmission because the restriction of Ethernet operation principle transmission radius can not be too big.And users are after the communication of having satisfied local area network, begin gradually to communicate with the local area network (LAN) of far-end and whole wide area network is inserted, and like this, the long Distance Transmission of Ethernet data have just been become an urgent demand of data communication.
Because the Large scale construction of synchronous digital hierarchy (SDH) network also has a large amount of E1 line resources outside the demand that has satisfied conventional digital communication.So just facilitated the generation of Ethernet, utilized existing primary group (E1) circuit to transmit Ethernet data, not only satisfied the needs of data communication but also protected the investment of SDH capital construction to E1 bridge converts device.
Flourish along with various broadband services, article 1,2 mbit/(being called for short 2M) circuit can not satisfy the bandwidth demand of data communication far away, in order to make full use of existing E1 line resource, satisfy the transmission demand of broadband ethernet, can take the inverse multiplexing technology, the E1 passage of many low speed is tied up the transmission that is used for the Fast Ethernet data.
Occur some products at present and adopted this inverse multiplexing technology.Although concrete implementation method and encapsulation mechanism have nothing in common with each other, basic operation principle has following two kinds nothing but: a kind of is to be that unit is encapsulated in the E1 circuit and transmits with whole ethernet frame, and many E1 circuits use in turn; Another kind is an ethernet frame to be divided into a plurality of parts encapsulate then and transmit in different E1 circuits.At application number is 02148951.3, and name is called " method and system of utilizing many E1 circuit transmission Ethernet datas " and discloses this inverse multiplexing technology.
The characteristics of Ethernet data are paroxysmal: Frame length is fixing, and the interval between frame and the frame is fixing, and frame structure has beginning and end mark: and the 2M data flow in the E1 passage is continuously and at the uniform velocity.Therefore utilize the E1 circuit to transmit encapsulation and conversion that Ethernet data must carry out frame format.
With whole frame Ethernet data be unit encapsulate and the basic principle of the inverse multiplexing technology transmitted as shown in Figure 1:
At the E1 of inverse multiplexer transmitting terminal, the Ethernet data that receives is that unit encapsulates and handles with a complete ethernet frame earlier through memory block (FIFO or RAM) buffer memory then.Packing forms can be various, comprise high-level data link control procedure (HDLC) or Generic Framing Procedure (GFP), even can be self-defining packing forms, the function of finishing is that Ethernet data is delimited so that receiving device can recover original Ethernet data in continuous 2M bit stream.Inverse multiplexer utilizes many E1 circuits to transmit Ethernet data, different ethernet data frames is to transmit respectively by different E1 links, because the frame length difference of Ethernet data, the propagation delay time of different E1 links also may be different, the order that arrives the ethernet frame of opposite end may be put upside down, to need to use the sequence number maker in order addressing this problem, each ethernet data frame that mails to the opposite end to be identified.In addition, the frame distribution logic can be assigned to different E1 links with continuous ethernet data frame according to the usage quantity of E1 link and get on, and guarantees the flow equalization on the different E1 links.
At receiving terminal, the frame alignment logical block receives the starting and ending sign that finds ethernet frame the next data flow from the E1 circuit, recover original ethernet frame, isolate the identifier number of this frame simultaneously, in order ethernet data frame is sent out successively then.
An ethernet frame is divided into a plurality of parts encapsulates the principle on different E1, transmitted then respectively as shown in Figure 2:
At the E1 transmitting terminal, the data Splitting Logic is divided into the ethernet data frame that receives the data block of fixed length, according to the usage quantity of E1 link these data blocks are assigned in the different E1 circuits then and transmit, the sequence number sign that the sequence number maker produces distributes to each data block so that the data recombination when receiving.The E1 sending module is sent to far-end by the E1 circuit after this serialized data block is packaged into certain frame structure.
At the E1 receiving terminal, the E1 receiver module receives from the next data flow of circuit, separate the data block that the frame rule obtains having sequence number information according to framing, sequence number checks that logic sorts to the sequence number of all data blocks, and the ethernet frame combinational logic recovers original ethernet data frame according to the result of sequence number ordering with data block combinations then.
E1 line fault detection module all can be arranged in all inverse multiplexers, detect the break-make situation of used circuit, after a certain or several circuits break, can utilize remaining circuit to work on, after circuit is communicated with, can recover use automatically this circuit.
Adopt the inverse multiplexing technology, utilize the Ethernet data of the next common transmitting high speed of many E1 circuits, can increase the transmission bandwidth of Ethernet greatly; Yet because ethernet frame does not have mechanism for correcting errors, the error code of a bit will cause the mistake of whole Frame, and the performance degradation of an E1 circuit can cause the more serious performance degradation of whole inverse multiplexer.
With 4 road E1 to the inverse multiplexer of Ethernet be example, cast aside the specific implementation method that various inverse multiplexing technology are adopted, only consider to appear at the influence of the error code of data field to data communication: it is 10 that one the error rate is arranged in 4 E1 circuits
-6The time, the Ethernet of one the 1518 byte error probability of long frame is 3 * 10
-3It is 1 * 10 that one the error rate is arranged in 4 E1 circuits
-5The time, the Ethernet error probability of long frame is 3 * 10
-2, the rest may be inferred for other.If error code appears on the delimiter byte or control byte of ethernet frame, the situation of makeing mistakes so may be more serious.As can be seen, the error code on the E1 circuit can cause the serious propagation on the ethernet frame; In addition, consider the retransmission mechanism of upper layer communication agreement, the LOF of data link layer will inevitably cause the increase greatly of descending significantly of bandwidth and transmission delay.
Summary of the invention
The present invention is in order to overcome above-mentioned defective, proposition is in the use of inverse multiplexer, if the transmission performance of certain bar E1 circuit is unexpected deterioration in some time periods, can cause the reduction greatly of whole data transmission efficiency, in this case the connection of this E1 link is cut off and utilized remaining E1 circuit to transmit, can prevent that wrong continuation propagation from keeping the normal use of equipment; After the performance recovery of circuit, automatically recover the use of this link again, not only transmission bandwidth can be utilized fully but also the application risk of equipment can be reduced.For this reason, the present invention proposes a kind of method and apparatus of protection and recovery of inverse multiplexer circuit layer.Described method comprises the steps:
Error detection signal generator module at the E1 of inverse multiplexer transmitter side produces the Error detection signal;
When circuit in order, is not received the feedback signal of link performance deterioration of far-end, send control module and can beyond sending valid data, periodically send the Error detection signal to the opposite end;
Receiver side at the E1 circuit, receiver module receives the data from link, giving the inverse multiplexing module with valid data deals with, simultaneously the Error detection Signal Separation being come out to give error code detection module goes to check, error code detection module is checked the Error detection signal, and the error code that detects counted, calculate the error rate of current circuit;
When the error rate surpassed given thresholding, inverse multiplexer thought that this link should not use, and suspended the processing of valid data and the feedback information of generation link performance deterioration, outwards sent alarm simultaneously;
Link performance deterioration information feeds back to transmitting terminal by specific bit or frame structure, the link performance of transmitting terminal feedback receiver module receives after this deterioration information that notice sends that control module stops to send valid data then all sends the Error detection signals, and the error code detection module of receiver side can continue in real time the error performance of current circuit is monitored;
When the error code detection module of the receiver side of circuit monitored that the error rate that obtains satisfies the instructions for use of inverse multiplexer, inverse multiplexer notice transmitting terminal automatically continued to send valid data, reuses this E1 passage.
Described Error detection signal can be a fixing or cycle tests/bit at random that is produced by the cycle tests generation module, and periodically be inserted into and follow valid data to send to the opposite end in the valid data, after arriving receiving terminal, receiver module is except sending valid data to inverse multiplexer processes, also cycle tests is separated and given the Error detection sequence and check and count, thereby draw the error rate of current circuit.
Described Error detection signal also can be CRC (cyclic redundancy check (CRC)) check bit/sequence signal, described CRC check bit/sequence is the CRC check bit/sequence that all contains in the frame structure of common data link layer, or in self-defining frame structure, increase check bit, at receiver side data flow is done identical calculating then, draw corresponding C RC check bit and with the CRC check that sends and comparing, draw the error rate of current circuit.
A kind of protection of inverse multiplexer circuit layer and the device of recovery, described device comprise transmission part and receiving unit, and described sending part branch comprises:
The first in first out module, the valid data that are used for receiving send sending module successively to;
Sending module under the control that sends control module, sends the signal from Error detection signal generator module and first in first out module;
Send control module, according to the transmission performance of judging link from the signal of link performance feedback receiver module, thereby control Error detection signal generator module produces the Error detection signal, and the control sending module sends;
Link performance feedback receiver module is used to receive the feedback signal about the circuit transmission performance from receiver side;
The Error detection signal generator module is used for producing the Error detection signal according to the control signal that sends control module, and sends to sending module;
Described receiving unit comprises:
Receiver module is used to receive the signal from sending module, and isolates valid data and Error detection signal;
Error code detection module, to separate from receiver module the Error detection signal check and count, draw the error rate of current link, compare with error rate threshold value then, judge the transmission quality of circuit: when the link performance deterioration, suspend the processing of valid data and provide the feedback of performance degradation, when link performance recovers, recover the processing of valid data and cancel the feedback of performance degradation;
The link performance feedback module receives the index signal from the expression link performance of error code detection module, and feeds back to the transmission part.
Described Error detection signal generator module is a cycle tests generation module, and this module produces a fixing or cycle tests/bit at random and periodically is inserted into follows valid data to send to the opposite end in the valid data; Described error code detection module is a cycle tests detection module, is used for cycle tests is checked and by counter error code counted, thereby draws the error rate of current circuit.
Described Error detection signal generator module is the CRC check computing module, and described CRC check bit/sequence is the CRC check bit/sequence that all contains in the frame structure of common data link layer, or increases check bit in self-defining frame structure; Described error code detection module is a CRC check and computing module, be used for data flow is done identical calculating, draw corresponding C RC check bit and compare with the CRC check that sends with by comparator, count by counter for the error code that occurs, draw the error rate of current circuit.
Transmission performance unexpected deterioration in some time periods of using method and apparatus of the present invention can overcome certain bar E1 circuit can cause the defective that reduces greatly of whole data transmission efficiency, the connection of this E1 link can be cut off and utilize remaining E1 circuit to transmit, can prevent that wrong continuation propagation from keeping the normal use of equipment, after the performance recovery of circuit, automatically recover the use of this link again, not only can utilize transmission bandwidth fully but also can reduce the application risk of equipment, improve the data transmission quality of inverse multiplexer.
General inverse multiplexer reaches 10 at a certain link
-4, 10
-3The error rate after, the packet loss of whole inverse multiplexer data forwarding has reached the stage that can not put up with, use the link of this performance degradation of cut-out that the inverse multiplexer after the inventive method then can be temporary transient and use remaining link to proceed transfer of data, intactly must guarantee the forwarding of data quality.
Below in conjunction with accompanying drawing the present invention is further described, can understand essence, advantage and the effect of technical scheme of the present invention better.
Description of drawings:
Fig. 1 is to be that unit encapsulates and the basic principle schematic of the inverse multiplexing technology transmitted with whole frame Ethernet data.
Fig. 2 is divided into a plurality of parts with an ethernet frame to encapsulate the principle schematic of transmitting then respectively on different E1.
Fig. 3 is that the protection of inverse multiplexer circuit layer and the device of recovery constitute schematic diagram.
Fig. 4 is the schematic diagram of first embodiment of the Error detection signal among the present invention when being the cycle tests signal.
Fig. 5 is the schematic diagram of second embodiment of the Error detection signal among the present invention when being CRC check bit/sequence signal.
Fig. 6 is the apparatus function block diagram of the protection and the recovery of inverse multiplexer circuit layer.
Fig. 7 A is the transmitter side flow chart of the protection and the recovery of inverse multiplexer circuit layer.
Fig. 7 B is the receiver side flow chart of the protection and the recovery of inverse multiplexer circuit layer.
Embodiment
Principle schematic illustrated in figures 1 and 2 is described in the background technology part, no longer repeats here.
Fig. 3 is that the protection of inverse multiplexer circuit layer and the device of recovery constitute schematic diagram.As shown in the figure, a kind of protection of inverse multiplexer circuit layer and the device of recovery, described device comprise transmission part and receiving unit, and described sending part branch comprises:
First in first out module (301), the valid data that are used for receiving send sending module (302) successively to;
Sending module (302) under the control that sends control module (304), sends the signal from Error detection signal generator module (303) and first in first out module (301);
Send control module (304), judge the transmission performance of link, produce the Error detection signal thereby control Error detection signal generator module (303), and control sending module (302) sends according to the signal that comes from link performance feedback receiver module (305);
Link performance feedback receiver module (305) is used to receive the feedback signal about the circuit transmission performance from receiver side;
Error detection signal generator module (303) is used for producing the Error detection signal according to the control signal that sends control module (304), and sends to sending module (302);
Described receiving unit comprises:
Receiver module (306) is used for receiving the signal from sending module (302), and isolates valid data and Error detection signal;
Error code detection module (308), to separate from receiver module (306) the Error detection signal check and count, draw the error rate of current link, compare with error rate threshold value then, judge the transmission quality of circuit: when the link performance deterioration, suspend the processing of valid data and provide the feedback of performance degradation, when link performance recovers, recover the processing of valid data and cancel the feedback of performance degradation;
Link performance feedback module (309) receives the index signal from the expression link performance of error code detection module (308), and feeds back to the transmission part.
Fig. 4 is the schematic diagram of first embodiment of the Error detection signal among the present invention when being the cycle tests signal.As shown in the figure, in Fig. 4, changed a cycle tests generation module (403) at the Error detection signal generator module (303) shown in Fig. 3, this module produces a fixing or cycle tests/bit at random and periodically is inserted into follows valid data to send to receiving terminal in the valid data, at receiving terminal, error code detection module shown in Fig. 3 (308) has changed cycle tests detection module (407) in Fig. 4, be used for cycle tests is checked and by counter (406) error code counted, thereby draw the error rate of current circuit.
Fig. 5 is the schematic diagram of second embodiment of the Error detection signal among the present invention when being CRC check bit/sequence signal.As shown in the figure, a CRC check and computing module (503) in Fig. 5, have been changed at the Error detection signal generator module (303) shown in Fig. 3, be used for that the data that will send are carried out CRC check and calculate, be inserted into then and deliver to sending module in the active traffic and send; At receiving terminal, by same CRC check and computing module (507), to carrying out CRC check and calculating in the data that receive, and the CRC check that transmits in result that will calculate and the data flow and compare by comparator (508), by counter (506) error code is counted then, thereby drawn the error rate of current circuit.
Fig. 6 is the apparatus function block diagram of the protection and the recovery of inverse multiplexer circuit layer.As shown in Figure 6, increase the partial logic circuit at existing 4E1 to the periphery of ethernet bridge transducer RC7210 and realized the performance monitoring of circuit, the protection and the recovery of passage.Have CRC check and bit in the E1 frame structure of inverse multiplexer RC7210; also can carry out CRC check at receiving terminal to data stream; provide the crc error alarm; but it can not be accepted or rejected this link according to the situation of the circuit error rate; and be merely able to accept or reject according to the on/off situation of circuit, so just must increase protection and the recovery that certain logical circuit is realized passage in the periphery of RC7210.Processing method with an E1 link of RC7210 is an example, functional block diagram is as shown in Figure 6: the supposition line conditions is good under the initial condition, the logical circuit that increases can not done any processing and only is to be in pass-through state the data flow of dealing, if at this moment the transmission performance of circuit is really good, RC7210 detects less than crc error, increase the error rate that the error rate detection module of logical circuit obtains so and be lower than appointed threshold, data flow continues straight-through.
If circuit transmission quality deterioration, straight-through data flow to A point RC7210 has error code to exist, RC7210 (600) can detect and provide the CRC alarm so, error code computing module (603) can calculate the error rate according to the quantity of CRC alarm, if being higher than the appointed threshold value, the error rate thinks that this link should not continue secured transmission of payload data, it can be notified and receive the reception valid data that RC7210 is mail in control logic (605) cut-out, informs this link transmission quality deterioration of RC7210 (600) by the particular frame structure; It can send specific frame structure by sending the logical circuit of control logic (604) control transmission selector (602) to the opposite end simultaneously, notice opposite end this link direction of logical circuit has problem, and received frame structure decision logic (607) enters the Error detection state then.
After the received frame structure decision logic (609) that B is ordered receives the particular frame structure of indication link performance deterioration, know that this link direction has problem, can stop paying out valid data by notice RC7210 (601), send the error code testing sequence by sending control module (613) notice transmission selector (615) to the A end simultaneously, so just finished the cut-out work of this link of RC7210.
At this moment, the received frame structure decision logic (607) of A end is in the error code monitored state, by cycle tests error code detection module (606) the error code testing sequence that the B end sends is carried out real-time monitoring, if the transmission performance of link is recovered, less than error code, think then that this link can reuse at the monitoring in time of a fixed length.Circuit error monitoring module (606) can notice reception control logic (605) discharge link again then, make link data straight-through to RC7210 (600), simultaneously by sending control logic (604) and sending the transmission performance recovery of the newly-increased logical circuit link that selector (602) notice B orders, allow RC7210 (601) to continue to send valid data, finish resuming work of link.
Newly-increased logical circuit comprises transmission part and receiving unit, and wherein the sending part branch comprises:
Send selector (602), under the control that sends control logic (604), select to send different data contents: when circuit just often sends the valid data that inverse multiplexer RC7210 (600) comes to the opposite end to the opposite end; Under the control that is sending control logic (604) after the line degradation, send the particular frame structure that is used to notify the opposite end to cut off and recovers to the opposite end earlier and continue to send the Error detection sequence then.
Error code computing module (603), the CRC alarm signal of utilizing RC7210 (600) to produce calculates the error rate of current circuit, and notice sends control module (604) and reception control module (605) is made corresponding control.
Send control module (604), the error rate result who obtains according to error code computing module (603) and cycle tests error code detection module (606) judges, and notice sends the different data content of selector (602) transmission.
Receive control module (605), the error rate result who obtains according to error code computing module (603) and cycle tests error code detection module (606) judges, and notice receives selector (608) to the different data content of RC7210 (600) transmission.
Cycle tests error code detection module (606), after line degradation, transmit on the circuit all be the Error detection sequence time, the data that send from received frame structure decision logic (607) are carried out Error detection, draw the corresponding error rate and notice transmission control module (604) and receive control module (605) and make corresponding control.
Received frame structure decision logic (607) receives the data of coming from circuit, and judgement is normal valid data, lasting Error detection sequence or the particular frame structure that is used to refer to link circuit condition.If normal valid data directly send to and receive selector (608) and straight-through to RC7210 (600); If when receiving the frame structure of indication link circuit condition, it can pass through cycle tests error code detection module (607), receives control logic (605) and receive selector (608) to cut off the valid data that lead to RC7210 (600); If receive lasting Error detection sequence, it can be delivered to cycle tests error code detection module (606) with the Error detection sequence that receives and do Error detection.
Receive selector (608), under the control that receives control logic (605), select to send different data contents to RC7210 (600); When link performance is good, send normal valid data; When the link performance deterioration, send specific frame structure and make RC7210 (600) cut off the reception of this link.
In the newly-increased logical circuit that B is ordered, corresponding module operation principle is identical.
Fig. 7 A is the flow chart of the E1 transmitter side of the protection of inverse multiplexer circuit layer and recovery.Shown in Fig. 7 A, when system's power-up initializing, the transmission control logic of E1 transmitter side is default thinks that the transmission performance of this link is good, sending module can send valid data to the opposite end, periodically interleaves the Error detection sequence simultaneously and for receiving terminal the error rate of circuit is carried out real-time monitoring.Next, whether the transmission control logic will be fed back the transmission performance of judging this link according to the link performance that receives good: if the link performance that this link is sent to is good, then send logic and can send valid data, can periodically insert the Error detection sequence simultaneously to the opposite end; If judge performance degradation on this link sending direction according to performance feedback, the transmission of the data of then ceasing to have effect then all send the error monitoring sequences recovers up to the transmission performance of link.
Fig. 7 B is the flow chart of the E1 receiver side of the protection of inverse multiplexer circuit layer and recovery.Shown in Fig. 7 B, the E1 receiver side of system is when power-up initializing, the link performance status register is default thinks that the transmission performance of current link is good, receiver module is separated valid data from receive the data of coming and is given inverse multiplexer and process, and simultaneously the error code testing sequence is delivered to error code detection module and does inspection.Error code detection module is analyzed and is counted cycle tests, calculate the error rate of current link, the threshold value that if line conditions is good, the error rate is lower than appointment, then the value of link performance status register is constant, continues to return original state processing valid data and also in real time link circuit condition is monitored.When the value of the error rate that draws when link performance deterioration, error code detection module is higher than the threshold value of appointment, the value of link performance status register changes, indicate this link transmission performance deterioration, receive control module and stop this chain road direction inverse multiplexer transmission valid data, stop paying out valid data by feedback circuit notice transmitting terminal simultaneously.Under the present case, the link performance status register thinks that line quality is bad, from the data on the E1 link all is cycle tests, receiver module can be delivered to all these data flow the detection that error code detection module is carried out the error rate, the transmission performance that does not detect error code, circuit up to error code detection module in the time of a fixed length recovers normal, at this time, the link performance status register reverts to the link performance kilter, proceeds the reception of valid data.
According to the abovementioned embodiments of the present invention, those skilled in the art can carry out various modifications according to technical scheme of the present invention, form of Error detection signal etc. for example, and these all do not break away from technical scheme of the present invention.
Claims (8)
1, the method for a kind of protection of inverse multiplexer circuit layer and recovery is characterized in that: described method comprises the steps:
Error detection signal generator module at the E1 of inverse multiplexer transmitter side produces the Error detection signal;
When circuit in order, is not received the feedback signal of link performance deterioration of far-end, send control module and can beyond sending valid data, periodically send the Error detection signal to the opposite end;
Receiver side at the E1 circuit, receiver module receives the data from link, giving the inverse multiplexing module with valid data deals with, simultaneously the Error detection Signal Separation being come out to give error code detection module goes to check, error code detection module is checked the Error detection signal, and the error code that detects counted, calculate the error rate of current circuit;
When the error rate surpassed given thresholding, inverse multiplexer thought that this link should not use, and suspended the processing of valid data and the feedback information of generation link performance deterioration, outwards sent alarm simultaneously;
Link performance deterioration information feeds back to transmitting terminal by specific bit or frame structure, the link performance of transmitting terminal feedback receiver module receives after this deterioration information that notice sends that control module stops to send valid data then all sends the Error detection signals, and the error code detection module of receiver side can continue in real time the error performance of current circuit is monitored;
When the error code detection module of the receiver side of circuit monitored that the error rate that obtains satisfies the instructions for use of inverse multiplexer, inverse multiplexer notice transmitting terminal automatically continued to send valid data, reuses this E1 passage.
2, method according to claim 1, it is characterized in that: described Error detection signal is a fixing or cycle tests/bit at random that is produced by the cycle tests generation module, and periodically be inserted into and follow valid data to send to the opposite end in the valid data, after arriving receiving terminal, receiver module is except sending valid data to inverse multiplexer processes, also cycle tests is separated and given the Error detection sequence and check and count, thereby draw the error rate of current circuit.
3, method according to claim 1, it is characterized in that: described Error detection signal is CRC check bit/sequence signal, described CRC check bit/sequence is the CRC check bit/sequence that all contains in the frame structure of common data link layer, or in self-defining frame structure, increase verification and bit, at receiver side data flow is done identical calculating then, draw corresponding C RC check bit and with the CRC check that sends and compare and count, draw the error rate of current circuit.
4, the device of a kind of protection of inverse multiplexer circuit layer and recovery, described device comprise transmission part and receiving unit, and it is characterized in that: described sending part branch comprises:
First in first out module (301), the valid data that are used for receiving send sending module (302) successively to;
Sending module (302) under the control that sends control module (304), sends the signal from Error detection signal generator module (303) and first in first out module (301);
Send control module (304), judge the transmission performance of link, produce the Error detection signal thereby control Error detection signal generator module (303), and control sending module (302) sends according to the signal that comes from link performance feedback receiver module (305);
Link performance feedback receiver module (305) is used to receive the feedback signal about the circuit transmission performance from receiver side;
Error detection signal generator module (303) is used for producing the Error detection signal according to the control signal that sends control module (304), and sends to sending module (302);
Described receiving unit comprises:
Receiver module (306) is used for receiving the signal from sending module (302), and isolates valid data and Error detection signal;
Error code detection module (308), to separate from receiver module (306) the Error detection signal check and count, draw the error rate of current link, compare with error rate threshold value then, judge the transmission quality of circuit: when the link performance deterioration, suspend the processing of valid data and provide the feedback of performance degradation, when link performance recovers, recover the processing of valid data and cancel the feedback of performance degradation;
Link performance feedback module (309) receives the index signal from the expression link performance of error code detection module (308), and feeds back to the transmission part.
5, device according to claim 4, it is characterized in that: described Error detection signal generator module (303) is a cycle tests generation module (403), and this module produces a fixing or cycle tests/bit at random and periodically is inserted into follows valid data to send to the opposite end in the valid data.
6, device according to claim 5, it is characterized in that: described error code detection module (308) is a cycle tests detection module (407), be used for cycle tests is checked and by counter (406) error code counted, thereby draw the error rate of current circuit.
7, device according to claim 4, it is characterized in that: described Error detection signal generator module (303) is CRC check computing module (503), described CRC check bit/sequence is the CRC check bit/sequence that all contains in the frame structure of common data link layer, or increases check bit in self-defining frame structure.
8, device according to claim 7, it is characterized in that: described error code detection module (308) is a CRC check and computing module (507), be used for data flow is done identical calculating, draw corresponding C RC check bit and compare with the CRC check that sends with by comparator (508), count by counter (506) for the error code that occurs, draw the error rate of current circuit.
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| CN100403686C (en) * | 2005-06-17 | 2008-07-16 | 华为技术有限公司 | Data service protection reverse triggering process and apparatus |
| CN102629898B (en) | 2012-04-11 | 2014-12-10 | 华为技术有限公司 | Data transmission method and device as well as system |
| CN103546231B (en) * | 2012-07-10 | 2018-10-23 | 南京中兴新软件有限责任公司 | A kind of control method and device of Ethernet service air interface transmission delay variation |
| CN103874107A (en) * | 2012-12-12 | 2014-06-18 | 河南省电力公司焦作供电公司 | Electric power communication system client terminal device monitoring method and system thereof |
| CN105656703A (en) * | 2014-11-12 | 2016-06-08 | 中兴通讯股份有限公司 | Method and apparatus for processing signal degradation |
| CN105162551B (en) * | 2015-07-29 | 2018-11-06 | 中工科安科技有限公司 | A kind of computational methods of CRC safety check codes for code device signal processing |
| CN107888345B (en) * | 2016-09-29 | 2022-02-18 | 中兴通讯股份有限公司 | Information transmission method and equipment |
-
2003
- 2003-04-15 CN CN 03109745 patent/CN1206839C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1996898B (en) * | 2005-12-28 | 2010-04-14 | 中兴通讯股份有限公司 | A system and method for real time detection of the data channel states |
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