CN1206495A - Method for making circuit structure having flip-mounted matrix of device - Google Patents
Method for making circuit structure having flip-mounted matrix of device Download PDFInfo
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- CN1206495A CN1206495A CN 96199400 CN96199400A CN1206495A CN 1206495 A CN1206495 A CN 1206495A CN 96199400 CN96199400 CN 96199400 CN 96199400 A CN96199400 A CN 96199400A CN 1206495 A CN1206495 A CN 1206495A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
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Abstract
A means of connecting a plurality of essentially identical active devices is presented for the purpose of multifunction and multiple function operation. These devices, mounted on a chip, are flip-mounted to a circuit motherboard having large passive elements. A push-pull amplifier is presented as an example in which the multiple function operation is the combining of amplifiers whose active devices are on a single chip. The electromagnetic coupling, impedance matching and signal transmission are variously provided by the use of striplines, slotlines, coplanar waveguides, and a slotline converted into a coplanar waveguide.
Description
The present invention relates to a kind of circuit structure, this circuit has the integrated circuit of upside-down mounting on substrate, has metallic conductor to link to each other with integrated circuit on the substrate.Be particularly related to the metallic conductor that has on a plurality of devices and the substrate the sort of integrated circuit that interconnects between device is provided.
Because the GaAs integrated circuit is relatively expensive, therefore usually microwave and millimeter (mm) wave circuit are made into hybrid circuit.Require to use the active device of GaAs to be manufactured on the GaAs chip, this GaAs chip is installed in and has as silicon, Al then
2O
3, BeO and AlN etc. the motherboard of not too expensive substrate on.
Make custom circuit by independent integrated circuit or the chip of corresponding each active device manufacturing with a plurality of active devices.Electric circuit metal conductor and passive device are printed on the motherboard, and each chip is installed in the appointed place on the motherboard then.Integrated circuit on the chip can be very simple, for example FET only.Also can be very complicated, introduce multiple device all functions can be provided, for example the function of amplifier.
Complicated circuit need prepare and install a large amount of this chips.The composite request of the little chip of individual processing also is tending towards making manufacturing process cost increase to a certain extent.In addition, when chip had complicated circuit, its manufacturing was more expensive, was that it needs bigger GaAs substrate owing to compare with having the simpler chip that is equal to, and the benefit of hybrid circuit structure can not all realize.
Therefore need a kind of method of constructing hybrid circuit, when being applied to microwave and millimetre-wave circuit, hybrid circuit structure can make the minimized in size of GaAs substrate, and is easy to make, and makes effectively thereby can reduce cost.
The present invention provides these characteristics by a kind of improved hybrid circuit and manufacture method thereof.The structure of chip is for having a plurality of electric devices, each electric device has at least one active device that control end and two current-carrying ends are arranged, at least two chip exits are relevant with each active device, comprises first chip exit relevant with control end and the second chip exit relevant with a current-carrying end.Be formed on the circuit on the substrate, be called the branch road of whole hybrid circuit, have corresponding to the substrate exit of each die terminals and the interconnection between the substrate exit.Flip-chip is to branch road, and each chip exit is installed to relevant substrate exit, so that the electric device electrical interconnection.
Chip preferably downcuts from the wafer of the big array that contains device.Chip contains adjacent less array device afterwards, and these devices can be identical or different.Therefore the branch road exit also is arranged in the corresponding array, is used for the interconnect die exit.
In a preferred form, the invention provides a kind of device that connects a plurality of active devices that are equal to basically, be used for the purpose of multi-functional (multiple function) and complex function (a kind of function compound) operation.These devices are installed on the chip, and this flip-chip has on the motherboard of passive component afterwards.If these passive devices are produced on the chip, so the size of Ang Gui active medium will increase, thereby greatly increase whole cost.This is because active area is more much smaller than passive region usually.
Use the present invention can make many different types of circuit, for example amplifier, oscillator, detector, frequency mixer and other use other circuit of a plurality of identical or different active devices, preferably use the chip of single active device matrix.
As specific example, the power R.F. amplifier of recommending manufactured according to the present invention comprises first pair of active device with other control end of branch (grid) and current-carrying end (leaking and the source), for example field-effect transistor (FET).A current-carrying end of each active device is connected to reference potential, for example circuit ground or virtual earth.Have the former limit of input conductor as the input electromagnetic coupler of transformer or balanced-to-unblanced transformer, this conductor is connected electrically between first the input and control end of paired active device.Input secondary conductor electromagnetism is connected to the former limit of input conductor, and is connected electrically between second the input reference potential and control end of paired active device.
The output electromagnetic coupler has another current-carrying end that is connected electrically in first active device and the former limit conductor between the output.Export the second conductor electromagnetism and be connected to output former limit conductor, and be connected electrically in another current-carrying end of second active device and export between the reference potential of former limit conductor.
Therefore, the signal of output is the combination of the signal of paired active device conduction.Active device is formed on the single chip with the exit that is connected respectively to active device in pairs, and this flip-chip forms on the corresponding end of the substrate on it to transformer or balanced-to-unblanced transformer.Input and output transformer or balanced-to-unblanced transformer also can be used as slotted line or co-plane waveguide is formed on the substrate.Slotted line can be U-shaped, and first and second portion are adjacent to extend, first and the signal electromagnet coupling of transmitting along second portion.First and second parts are limited by the peninsula shape conductor that extends in the U-shaped slotted line.Chip is installed in the mode of control end upside-down mounting on the shape conductor of the peninsula of an active device with respect to substrate.An embodiment becomes co-plane waveguide by using the circular open of U-shaped slotted line end with slotline transition.The function of these openings is equivalent to open circuit, makes thus to extend to other signal conductors carry input signal of branch that forms as beginning lead wire of conductor (leg) in the U-shaped slotted line.
Therefore obviously the invention provides a kind of circuit that can constitute simple and economically.To the detailed introduction of preferred embodiment and the diagram of accompanying drawing, these and other feature and advantage of the present invention will be obviously by following.
Fig. 1 is for making the local wafer simplified plan view with FET array that circuit of the present invention uses.
The schematic diagram of the push-pull amplifier circuit that Fig. 2 makes for one group of FET in the array of Fig. 1 used according to the invention.
Fig. 3 is the schematic diagram of the plural serial stage connecting circuit of Fig. 2 of using the chip with FET array extending.
Fig. 4 is the simplified plan view of the chip that can use in the circuit of Fig. 3.
Fig. 5 is the plane graph of first embodiment of the circuit of Fig. 3 of use microstrip line conductor.
Fig. 6 is the schematic diagram of the push-pull amplifier circuit that can use in the second embodiment of the present invention.
Fig. 7 is the plane graph of second embodiment of Fig. 3 of use slotted line.
Fig. 8 is the layout plane graph of chip array FET that is used for the embodiment of Fig. 7.
Fig. 9 is the plane graph of the 3rd embodiment of the circuit of Fig. 3 of use co-plane waveguide.
Figure 10 is the chip FET layout amplification view of the circuit of Fig. 9.
Figure 11 is for carrying out the plane graph of slotted line to the 4th embodiment of Fig. 3 circuit of two co-plane waveguide conversions.
One aspect of the present invention relates to use and has a plurality of single chips that are connected respectively to the active device that is formed on the branch road on the motherboard.At first with reference to figure 1, the active device array 10 that is shown as FET12 uses conventional technology to be formed on the wafer 14.The term active device is meant discrete component, transistor for example, or any relevant integrated circuit, for example amplifier.
Illustrate potential saw or the scribe lanes that one or more groups FET and adjacent FET are demarcated as line 16 and horizontal dotted line vertical with 18 grades.Each FET comprises grid or control end 20, source 22 and leakage 24.Source and leakage also are called the current-carrying end.Each grid, source and leakage are connected at least one link, for example each exit 26,28 and 30.
Can prepare wafer 14 in a large number, can make each active device relatively inexpensive thus.The cutting pattern of use selecting then is divided into the array of active device with the wafer of selecting, so that the chip of gained has the active device of link corresponding to the link position on the motherboard.By changing the cutting pattern of wafer, the different arrays of active device can form different circuit.In an application of this scheme, the active device on the chip does not interconnect.Yet in other is used, have some interconnection, each active device all has other link of branch simultaneously.The example of back one feature is presented in Fig. 9 and 10, and introduces below, and wherein adjacent exit for example source or leakage links together.
Fig. 1 shows a simple form of the present invention, and wherein all devices on the wafer are all identical.When needs used different devices, different set of devices was made wafer with the configuration or the figure that repeat.
The present invention is to be used in the structure of the gate array of the megacryst pipe of high conducting electric current or high power output in an application of discrete many device arrays.For the application of microwave and millimeter wave, using Wilkinson combiner or coordinate to connect FET usually provides impedance conversion and makes up multiple exit connection.
Use the push-pull amplifier circuit, for example the circuit among Fig. 2 32 can obtain similar result.Use can constitute this circuit with reference to the active device array chip that figure 1 had introduced, and with respect to the power amplifier in parallel of many FET of routine, this circuit has intrinsic advantage, particularly impedance conversion.Circuit 32 comprises input 33, by the first input input electromagnetic coupled 34 that form of coupling element 35 be electromagnetically coupled to second of element 35 and import coupling element 36.
The chip 38 that is illustrated by the broken lines comprises first and second FET39 and 40.Element 35 is coupled to input the grid of the one FET.Element 36 is connected to common potential with the grid of the 2nd FET, for example.
By the first output coupling element 44 of component part output electromagnetic coupled 45, the leakage of FET39 is connected to output 42.The second output coupling element 46 with element 44 electromagnetic coupled is connected to ground with the leakage of FET40.
By the electromagnetic coupled in the input and output, signal is separated by two FET and is used for amplifying.This structure can be used in series connection shown in Figure 3/parallel pushpull configuration and is used for impedance conversion.The figure shows and have a plurality of series connection (recommending) parts for example part 52 and 54 power amplifier 50.Each part 52 and 54 comprises two circuit parts 56 and 58 with circuit 32 equivalences of Fig. 2, but the tie point of these two circuit parts does not have ground connection, but links together, shown in tie point 60 and 62.The virtual earth that causes tie point like this.
For example use the Wilkinson distributor to be divided into input signal to the signal of each circuit part and merge output signal, can obtain substantial power combination.Before or after Signal Separation or the merging, can reach impedance matching on the discrete FET.
FET aligns in the linear array 64 of FET, and this array can be formed by the single chip 66 that the content of introducing with reference to figure 1 is made.The exemplary FET of chip 66 or the actual graphical of bipolar transistor are presented among Fig. 4.In this case, the transistor of demonstration is the repetition of transistor to Q1, Q2, Q3 and Q4 etc.Each transistor is to corresponding to first and second FET in the circuit part shown in Figure 3.As introducing with reference to figure 1, each FET, for example FET Q1 comprises grid 68, grid exit 69, source 70, source exit 71, leaks 72 and leak exit 73.These transistorized structures may be different, and this depends on their functions separately.
First embodiment of power amplifier 50 is shown as the amplifier 74 among Fig. 5.Chip 75 has eight FET, comprises FET 76,77,78 and 79.Amplifier 74 comprises similar series connection push-pull circuit part 80 and 81.Quarter-wave input microstrip line conductor 82 and 83 is communicated with by air bridges (air bridge) 84.Similar with it, input microstrip line conductor 85 and 86 is communicated with by air bridges 87.Comprise quater-wave section for example these conductors of 82a part input signal is offered each part.Electromagnetic coupled is provided to complementary input signal the 2nd FET of the bottom of each part, for example FET 77 and 78.By each U-shaped conductor 88 and 89, each the 2nd FET is linked together.The conductor of microstrip line on the outlet side on general formal and input side is similar.
The design microstrip line is to obtain the impedance of any needs.Being connected in series inputs or outputs impedance, enough high up to impedance, and their power ranks as required become to connect many parts in parallel then.
Fig. 6-8 shows and uses slotted line to implement power amplifier 90 of the present invention.Fig. 6 is two FET 91 having that source electrode links together and 93 the schematic diagram of recommending part 92.Two balanced input signals are applied to each grid, and produce two balanced output signals in each drain electrode.
Fig. 7 show be used for part 92 and with the preferred form of the slotted line of part 92 similar extentions 95, they are positioned on the substrate of motherboard, on the electric hybrid board or on the substrate of another kind of type.Be equivalent to amplifier 76 in amplifier 90 operations.Input slotted line 94, the branch road that also is called the circuit of amplifier 90, conductor 96 and 98 by opposite planar forms, shape is similar to reverse " E " of belt length central tap part 94a, oppositely extend through sweep 94b and 94c, and closed end external lead portion 94d is parallel with central tap part 94a with 94e.This shape produces each beginning conductor and refers to 96a and 98a between the slotted line lead portion.
The effect of external lead portion is equivalent to the RF choke.Though because the impedance matching difference of input and output circuit causes the size difference, output slotted line 100 mirror images for the input slotted line, and type of action is identical.In the time of on being installed in slotted line 94 and 100, corresponding FET structure is presented in the chip 102 of Fig. 8.Chip 102 contains FET91,93,104 and 106, and grid, source and leakage exit that each all has separately are designated G, S and D.The corresponding exit that identifies among the arrangement of these exits and Fig. 7 is consistent.
Fig. 9 and 10 shows and realizes the 3rd power amplifier 110 of the present invention.Fig. 9 shows as metallic conductor and is formed on branch road 112 on the substrate of motherboard, and Figure 10 is the enlarged drawing of flip-chip 114 when being installed on the metallic conductor.As the applying date is that the sequence number 08/313,927 on August 26th, 1994 and the pending trial U.S. Patent application that transfers the assignee identical with the present invention are described, and co-plane waveguide also can be power amplifier impedance matching and signal transmission are provided.
Except impedance matching difference, with respect to the ground plane bar 132 that extends for 114 times at the FET array chip, output co-plane waveguide 130 is essentially the mirror image of input co-plane waveguide.This metallic conductor make the FET array be connected in parallel rather than connect/parallel connection recommends operation, although the metallic conductor that is used to recommend also is easy to constitute.
Figure 10 has two group 134 and two FET of 135 diagram to 136 chip 114.Each FET in the chip is to the 136 relevant exits with a upside-down mounting corresponding exit to the branch road.Therefore, grid exit 138 is connected to grid 139 and 140. Source exit 141 and 142 and leak exit 143 and be connected respectively to source 144 and 145 and leak 146.FET exit 138,141,142 and 143 is connected to other branch road exit 150,151,152 and 153 of branch.
Leak 146 function and be equivalent to the two drain electrodes of each FET two FET in 136.Similarly, each source for example can be used as the source electrode of the relevant FET of adjacent FET centering in source 142.Therefore these dual-purpose exits are actually the connection exit.
Though chip 114 is custom-designed in this embodiment, can downcuts from the complete FET centering of wafer and make amendment.In this case, to can be used for each FET right to the two FET of 136 or one cover for the source exit of separation.Perhaps, amplifier 110 can be made together with the bimetallic conductor 112 and 113 of the parallel connection of the single chip that is installed to the FET configuration with the chip 114 that duplicates.
At last, Figure 11 shows the part of power amplifier 160, and this power amplifier has the motherboard branch road 162 of fet chip 164 upside-down mountings shown in the dotted line on it.The same with the situation in the amplifier 110, the FET in the chip 164 in the array 168 of FET, for example (grid) in series are electrically connected FET166 in the input.
The importation of branch road 162 is different in this embodiment.It can carry out the conversion to two co-plane waveguides 176 and 178 of the input line of rabbet joint 170 that formed by copline conductor 172 and 174.These output lines can or be recommended the similar mode of line and make up with input circuit.Replacement stops in the E of amplifier shown in Figure 7 90 shape groove, and groove 180 is punished into the U-lag 180a and the 180b of elongation at node 182.
U-lag terminates in circular open 180c and 180d.These openings are equivalent to open circuit, can make each conductor delivery input signal as beginning lead wire of conductor 172a that extends into U-lag and 174a formation thus.The middle conductor 184 that chip is connected to conductor 172 and 174 for 164 times extends to the source exit of FET by node 182, and for example exit 186.That introduces when FET is installed and is connected to conductor and introduces amplifier 90 is the same.
Therefore be appreciated that to the invention provides a kind of hybrid circuit structure, wherein a plurality of active devices preferably are formed on the chip that will install with array format, and are separately connected to the branch road on the substrate that is formed on motherboard.Though the applicable any circuit that need be connected with a plurality of discrete active devices of the present invention or the combination of circuit, the present invention is particularly useful to multifunction chip and power amplifier.The present invention to FET to recommend configuration also particularly useful, to various copline metallization pattern advantageous particularlies.Connect between the active device that also may reside on the chip, and the branch road that each active device connects needn't be correlated with.
Other example that can implement this circuit according to the present invention easily comprises the receiver of the power amplifier of being with internal detector, band RF low noise amplifier, as the blender of Gilbert cell blender etc., with or without the oscillator and the intermediate frequency amplifier of adjustable variable capacitance diode.The present invention also is applicable to phase-shift circuit, particularly distributing line (artificial transmission line) type.
In all these situations, preferably matrix tube core or chip only have the active device of upside-down mounting to the substrate, for example FET.Can realize several advantages thus.Can use simple FET technology and MMIC technology to make chip.Because wafer is cut into multiple different configuration, therefore be easy to provide appropriate samples.Product can make and correspond with a sample so.Even before determining application, also can prepare suitable wafer.Can realize high production rate and a large amount of manufacturings.
Therefore to one skilled in the art, the change that the form and the details of preferred embodiment are made does not obviously exceed the spirit and scope of the present invention that claims limit, and any modification that the language or the meaning of claims are made is to carry out under the principle that is equal to.Therefore preferred embodiment is provided is to be explanation and illustrative purposes, rather than the purpose in order to limit.
Claims (27)
1. method that constitutes first hybrid circuit (50) comprises step:
Formation has a plurality of electric device (Q
1, Q
2) first chip (66), each electric device (Q
1, Q
2) comprise that at least one has the active device (Q of control end (68) and two current-carrying ends (70,72)
1, Q
2) and at least two and each active device (Q
1, Q
2) relevant chip exit (69,71,73), these two chip exits comprise first chip exit (69) relevant with control end (68) and the second chip exit (71,73) relevant with a current-carrying end (70,72);
On first substrate, form first branch road (34,35), substrate have corresponding to the substrate exit of each chip exit (69,71,73) (G, S, D) and substrate exit (G, S, D) interconnection between;
With chip (66) upside-down mounting on branch road (34,35), each chip exit (69,71,73) be installed to relevant substrate exit (G, S, D) on, so electric device (Q
1, Q
2) electrical interconnection.
2. according to the method for claim 1, the step of wherein said formation chip (66) also is included in first wafer (14) and goes up the array (10) that forms electric device (12), and from wafer (14) cutting-out a plurality of first chips (66), each chip (66) contains a plurality of electric device (Q
1, Q
2).
3. according to the method for claim 2, the step of the array (10) of wherein said formation electric device (12) is included on the wafer (14) between the electric device (12) has electrical interconnection ground to form the array (10) of electric device (12).
4. according to the method for claim 2, the step of wherein said formation array (10) comprises with electric device (12) the formation array (10) that is equal to.
5. according to the method for claim 4, further also form second hybrid circuit (90) different, comprise step with first hybrid circuit (80):
Go up the array (10) that forms electric device (12) at second wafer (14);
Downcut many second chips (102) different from second wafer (14) with first chip (66), each second chip (102) also has a plurality of electric devices (91,93), each electric device (91,93) comprise that at least one has control end (G) and two current-carrying end (S, D) active device (91,93), at least two chip exit (G, Ss relevant with each active device (91,93), D), these two chip exits comprise the first chip exit (G) relevant with control end (G) and with a current-carrying end (S, D) the relevant second chip exit (S, D);
On second substrate, form second branch road (94) different with first branch road (82), second substrate also have corresponding to each chip exit (G, S, substrate exit D) (G, S is D) with substrate exit (G, S, D) interconnection between;
With second chip (102) upside-down mounting on second branch road, each chip exit (G, S, D) be installed to relevant substrate exit (G, S, D) on, so electric device (91,93,104,106) electrical interconnection.
6. according to the method for claim 5, the step of wherein said formation array (10) comprises the electric device (12) that formation is made up of transistor (12).
7. according to the method for claim 4, further also form second hybrid circuit (90) different and comprise step with first hybrid circuit (74):
Go up the electric device (12) that forms identical array (10) at second wafer (14);
Downcut a plurality of first chips (66) from second wafer (14);
On second substrate, form second branch road (94) different with first branch road (82), second substrate also have corresponding to each chip exit (G, S, substrate exit D) (G, S is D) with substrate exit (G, S, D) interconnection between;
With first chip (66) upside-down mounting on second branch road (94), each chip exit (G, S, D) be installed to relevant substrate exit (G, S, D) on, so electric device (Q
1, Q
2) electrical interconnection.
8. according to the method for claim 7, the step of wherein said formation array (14) comprises the electric device (12) that formation is made up of transistor (12).
9. according to the process of claim 1 wherein that the step of described coupling comprises each electric device (Q
1, Q
2) be directly connected to branch road (34,35).
10. according to the method for claim 9, the step of wherein said installation comprises chip (66) upside-down mounting to substrate.
11. according to the process of claim 1 wherein that the step of described formation chip (66) comprises with identical electric device (Q
1, Q
2) formation chip (66).
12. according to the process of claim 1 wherein that the step of described formation chip (66) comprises with a plurality of active electric device (Q
1, Q
2) formation chip (66).
13. according to the method for claim 12, the step of wherein said coupling comprises each active device (Q
1, Q
2) be directly connected to branch road (34,35).
14. according to the method for claim 12, the step of wherein said formation chip (66) comprises with at least one active electric device (Q on the common sides that is connected to chip (66)
1, Q
2) a plurality of exits (G, S D) form chip (66), the step of described formation branch road (34,35) comprises with a plurality of exits (G, S on the common sides, D) form branch road (34,35), the step of described coupling comprises the exit of chip (66) (G, S, D) upside-down mounting is to branch road (34, exit 35) (G, S, D).
15. according to the method for claim 14, the step of wherein said formation chip (66) also comprises with being connected to each active electric device (Q
1, Q
2) at least one exit (G, S D) form chip (66).
16. according to the process of claim 1 wherein that the step of described formation chip (75) comprises that also the electrical connection (84,87,88,89) between the electricity consumption device (76,77,78,79) forms chip (75).
17. according to the method for claim 16, the step of wherein said formation chip (75) also comprises with active electric device (76,77,78,79) the formation chip (75) that is transistor (76,77,78,79) form.
18. according to the process of claim 1 wherein that the step of described formation chip (66) also comprises with being transistor (Q
1, Q
2) the active electric device (Q of form
1, Q
2) formation chip (66).
19. according to the method for claim 18, wherein hybrid circuit (50) is amplifier (50), the step of described formation chip (66) comprises forming to have a plurality of field-effect transistor (Q that are arranged to linear array (64)
1, Q
2) chip (66), the corresponding array (64) of chip input (69) is connected to transistorized grid (68).
20. method according to claim 19, the step that wherein forms substrate branch road (80) comprises a plurality of input conductors (82 that extend to a plurality of intervals in the bonding pad (75) of formation, 85,88), each input conductor (82,85,88) be connected to the substrate input (G) relevant, and the step of described installation chip (75) comprises with each the chip input (G) that is connected to relevant substrate input (G) chip (75) is installed in the bonding pad (75) with each chip input (G).
21. according to the method for claim 20, the step that wherein forms substrate branch road (80) comprises that also near small part input conductor (82,83) publishes in instalments the step of (84) with the end of bonding pad (75).
22. method according to claim 20, the step that forms chip (75) comprises that also transistor leaks or the chip output exit (D in source with being connected to, S) linear array forms chip (75), the step that forms substrate branch road (80) comprises a plurality of output conductors that extend to a plurality of intervals in the bonding pad (75) of formation, each output conductor is connected to the substrate output (D relevant with each chip input (G), S), and the step of described installation chip (75) comprises with being connected to relevant substrate output (D, S) (D S) is installed in chip (75) in the bonding pad (75) each chip output.
23. according to the method for claim 22, the step that wherein forms substrate branch road (80) comprises that also near small part output conductor (82,83) publishes in instalments the step of (84) with the end of bonding pad (75).
24. according to the method for claim 19, the step that wherein forms chip (75) comprises that the transistor (76,77,78,79) with 1x N array forms chip (75), wherein N is the integer greater than 1, and chip input (G) is along the distribution of lengths of array.
25. according to the process of claim 1 wherein that the step of described formation chip (66) comprises a plurality of electric device (Q
1, Q
2) between have electrical interconnection ground to form chip (66).
26. according to the method for claim 25, the step of wherein said formation chip (66) also comprises with being transistor (Q
1, Q
2) active electric device (Q
1, Q
2) formation chip (66).
27. according to the method for claim 25, the step of wherein said formation chip (66) also comprises with only comprising transistor (Q
1, Q
2) active electric device (Q
1, Q
2) formation chip (66).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 96199400 CN1206495A (en) | 1996-10-25 | 1996-10-25 | Method for making circuit structure having flip-mounted matrix of device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 96199400 CN1206495A (en) | 1996-10-25 | 1996-10-25 | Method for making circuit structure having flip-mounted matrix of device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1206495A true CN1206495A (en) | 1999-01-27 |
Family
ID=5129467
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 96199400 Pending CN1206495A (en) | 1996-10-25 | 1996-10-25 | Method for making circuit structure having flip-mounted matrix of device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1206495A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102609597A (en) * | 2012-03-29 | 2012-07-25 | 中国电子科技集团公司第十三研究所 | Method for layout of compound semiconductor microwave power chip |
-
1996
- 1996-10-25 CN CN 96199400 patent/CN1206495A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102609597A (en) * | 2012-03-29 | 2012-07-25 | 中国电子科技集团公司第十三研究所 | Method for layout of compound semiconductor microwave power chip |
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