CN1205673C - Current guiding circuit for reducing plasma damage and semiconductor making method - Google Patents
Current guiding circuit for reducing plasma damage and semiconductor making method Download PDFInfo
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- CN1205673C CN1205673C CN 01117696 CN01117696A CN1205673C CN 1205673 C CN1205673 C CN 1205673C CN 01117696 CN01117696 CN 01117696 CN 01117696 A CN01117696 A CN 01117696A CN 1205673 C CN1205673 C CN 1205673C
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- guiding circuit
- oxide semiconductor
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Abstract
The present invention relates to a method for decreasing plasma damaging a grid electrode oxidizing layer of a metal oxide semiconductor (MOS) transistor. Firstly, a dielectric layer is formed on the MOS transistor on a substrate. Then, a first contact hole and a second contact hole are etched in the dielectric layer, wherein the first contact hole is communicated with a grid electrode of the MOS transistor; the second contact hole is communicated with an N-type well of the substrate. A current guide circuit is formed on the dielectric layer and in the first contact hole and the second contact hole, and is electrically connected with a power-off region. The MOS transistor is electrically connected with the N-type well. The ions which originally enter a grid electrode oxidizing layer by the technology are guided into the N-type well by the current guide circuit, so that the condition of the plasma damaging the grid electrode oxidizing layer is decreased. After the MOS transistor technology is completed, the electric connection in the power-off region is cut off.
Description
Technical field
The present invention relates to a kind of metal-oxide semiconductor (MOS) (metal-oxide semiconductor, MOS) transistorized guiding circuit, the plasma damage (plasma damage) that is suffered with the grid oxic horizon (gate oxide) that reduces MOS transistor.The invention still further relates to the semiconductor making method that reduces plasma damage.
Background technology
(metal-oxide semiconductor, MOS) transistor is the most normal a kind of electronic component that is applied in the integrated circuit (integrated circuits) to metal-oxide semiconductor (MOS).MOS transistor is by grid (gate), source electrode (source) and drain electrode three kinds of four contact elements that different electrode constituted such as (drain), it mainly is to utilize the grid of MOS transistor to come as digital (digitalized) solid-state switch between a kind of source electrode and drain electrode, to arrange in pairs or groups other element application on the integrated circuit (IC) products of various logic and memory at formed channelling effect under the different grid voltages (channel effect).
Please refer to Fig. 1 to Fig. 4, Fig. 1 to Fig. 4 is the method schematic diagram of existing making MOS transistor.As shown in Figure 1, existing MOS transistor is made on the semiconductor wafer 10, include a silicon base (silicon substrate) 12 on the semiconductor wafer 10, and one grid (gate) 16 be located on the silicon base 12, wherein 12 of grid 16 and silicon base include a grid oxic horizon 14 in addition, are located on the surface of silicon base 12.
Then as shown in Figure 2, carry out one first ion and inject (ion implantation) technology 18, form two doped regions with silicon base 12 top layers in grid 16 both sides, be used for regarding lightly doped drain (the lightly doped drain of MOS transistor, LDD) 22, source drain extension just (Source-DrainExtension, SDE).
As shown in Figure 3, utilize an insulating material around the vertical sidewall of grid 16, to form sidewall (spacer) 24 afterwards again.Then as shown in Figure 4, carry out one second ion implantation technology 26, on the silicon base 12 of sidewall 24 outer rims, form two doped regions,, finish the technology of MOS transistor, as shown in Figure 4 as the source electrode (source) 27 and drain electrode (drain) 28 of MOS transistor.
Please refer to Fig. 5, Fig. 5 aims at silicide (self-alignment silicide, salicide) the method schematic diagram of technology voluntarily for existing MOS transistor.After finishing the technology of MOS transistor, present semiconductor technology can increase the technology of aiming at silicide together voluntarily mostly again, or in the technology formerly just respectively at sputter one deck polycrystalline metal silicide (polycide) on grid 16, source electrode 27 and 28 the siliceous surface of draining, be used for reducing the contact resistance on each siliceous surface.Therefore, finish after this aims at silicide process voluntarily, the grid 16 of MOS transistor, source electrode 27 and 28 surfaces that drain can form metal silicide layers 32, to reduce the contact resistance on each siliceous surface.
Yet in the process of making MOS transistor, the ultra violet radiation steps such as (UV radiation) of being carried out during owing to plasma etching (plasma etching), ion bombardment (ion bombardment) and development (photo process) all might cause a large amount of electronics to be accumulated among the grid, and then produce the phenomenon of electric current, that is " antenna effect " that be commonly called as (antenna effect) from grid infiltration silicon base.This antenna effect will cause the degeneration (degradation) of grid oxic horizon, and just so-called " plasma damage " (plasma process induced damage PPID), and then has a strong impact on the function of MOS transistor.Therefore, how avoiding electronics to accumulate in MOS transistor manufacturing process in the grid and cause grid oxic horizon to be subjected to plasma damage, is an instant important topic in fact.
Summary of the invention
Therefore main purpose of the present invention is to provide a kind of minimizing metal-oxide semiconductor (MOS) (MOS) plasma damage that transistorized grid oxic horizon suffers (plasma process induced damage, PPID) method is to solve the problem of above-mentioned existing manufacture method.
The guiding circuit that one aspect of the present invention provides a kind of grid oxic horizon that is used for reducing a metal oxide semiconductor transistor to suffer plasma damage, this guiding circuit is located on the semiconductor wafer, comprise a substrate on this semiconductor wafer, this metal oxide semiconductor transistor is located in this substrate, one dielectric layer is covered on this metal oxide semiconductor transistor, and this guiding circuit is located on this dielectric layer, this guiding circuit comprises: one comprises the lead of one first contact jaw and one second contact jaw at least, and this first contact jaw is electrically connected on a grid conducting layer at this metal oxide semiconductor transistor top, and this second contact jaw then is electrically connected on this suprabasil doped region; And an outage area, be located in this lead, be used for cutting off being electrically connected of this lead and this metal oxide semiconductor transistor, and this guiding circuit is different with the material of this outage area; Wherein the ion in this grid oxic horizon is conducted in this doped region by this lead, suffers plasma damage to reduce this grid oxic horizon.
The present invention provides a kind of grid oxic horizon of minimizing one metal oxide semiconductor transistor to suffer the method for plasma damage on the other hand, this metal oxide semiconductor transistor is to be located in the substrate of semiconductor wafer, and this method comprises the following steps: to be covered on this metal oxide semiconductor transistor in forming a dielectric layer in this substrate; In this dielectric layer, etch the top of sensible this metal oxide semiconductor transistor in one first contact hole, and sensible this suprabasil doped region in one second contact hole; On this dielectric layer, in this first contact hole and this second contact hole, form a guiding circuit, and in this guiding circuit, be electrically connected an outage area, and this guiding circuit is different with the material of this outage area, is electrically connected so that this metal oxide semiconductor transistor forms with this doped region; And the electrical connection of after finishing the technology of this metal oxide semiconductor transistor, cutting off this outage area; Wherein the ion in this grid oxic horizon is conducted in this doped region by this guiding circuit, suffers plasma damage to reduce this grid oxic horizon.
The guiding circuit that further aspect of the present invention provides a kind of grid oxic horizon that is used for reducing a metal oxide semiconductor transistor to suffer plasma damage, this guiding circuit is located on the semiconductor wafer, and comprise a substrate on this semiconductor wafer, at least one metal oxide semiconductor transistor is located in this substrate, this guiding circuit comprises: one comprises the lead of one first contact jaw and one second contact jaw at least, and this first contact jaw is electrically connected on a grid conducting layer of this metal oxide semiconductor transistor, and this second contact jaw then is electrically connected on this suprabasil doped region; And an outage area, be located in this lead, be used for cutting off being electrically connected of this lead and this metal oxide semiconductor transistor; Wherein the ion in this grid oxic horizon is conducted in this doped region by this lead, suffer plasma damage to reduce this grid oxic horizon, and this guiding circuit is different with the material of this outage area.
In a preferred embodiment of the invention, this MOS transistor is located in the substrate of semiconductor wafer.At first, be covered on this MOS transistor, in this dielectric layer, etch the top of sensible this MOS transistor in one first contact hole again in forming a dielectric layer in this substrate, and sensible this suprabasil N type well (n-well) in one second contact hole.Then on this dielectric layer, form a guiding circuit (bypass) that is constituted by a metal level in this first contact hole and this second contact hole, and in this guiding circuit, be electrically connected one by the superfine plain conductor of a width, or, make this MOS transistor be electrically connected on this N type well by the outage area that polysilicon constitutes.At last, after finishing the technology of this MOS transistor, make this outage area part lead fusion in a high temperature mode, or with this outage area of a laser radiation, to cut off the electrical connection of this outage area.
Because manufacture method of the present invention is to make this MOS transistor be electrically connected on this N type well by a guiding circuit, so because the ion that plasma etching (plasma etching), ion bombardment (ionbombardment) and the ultra violet radiation steps such as (UV radiation) of being carried out when developing (photo process) are accumulated is able to be conducted in this N type well by this guiding circuit, form electrical neutralization in this grid with ion in this N type well.Therefore manufacture method of the present invention can prevent the generation of antenna effect (antennaeffect), and then reduce plasma damage (the plasma processinduced damage that this grid oxic horizon suffers, PPID), effectively guarantee the normal operation of MOS transistor.
Description of drawings
Below in conjunction with accompanying drawing the preferred embodiments of the present invention are described.In the accompanying drawing:
Fig. 1 to Fig. 4 is the existing method schematic diagram of making MOS transistor;
Fig. 5 aims at the method schematic diagram of silicide process voluntarily for existing MOS transistor;
Fig. 6 to Figure 11 reduces the method schematic diagram that the transistorized grid oxic horizon of a metal-oxide semiconductor (MOS) suffers plasma damage for the present invention.
Accompanying drawing shows symbol description:
10 semiconductor wafers, 12 silicon base
14 grid oxic horizons, 16 grids
18 first ion implantation technologies, 22 lightly doped drains
24 sidewalls, 26 second ion implantation technologies
28 drain electrodes of 27 source electrodes
32 metal silicide layers, 40 semiconductor wafers
42 silicon base, 44 grid oxic horizons
46 grids, 48 first ion implantation technologies
54 sidewalls, 56 second ion implantation technologies
58 drain electrodes of 57 source electrodes
60 dielectric layers, 62 first contact holes
64 second contact holes, 66 guiding circuits
68 outage area, 70 shallow isolating trough
Embodiment
Please refer to Fig. 6 to Figure 11, Fig. 6 to Figure 11 reduces a metal-oxide semiconductor (MOS) plasma damage that transistorized grid oxic horizon suffered (plasma process induced damage, method schematic diagram PPID) for the present invention.As shown in Figure 6, include a silicon base (silicon substrate) 42 on the semiconductor wafer 40, and one grid (gate) 46 be located on the silicon base 42, wherein 42 of grid 46 and silicon base are provided with a grid oxic horizon 44 in addition and are located on the surface of silicon base 42.In addition, in the zone outside distance grid 46 1 segment distances, other is provided with N type well (n-well) 50 in silicon base 42, and N type well 50 is separated by with a shallow isolating trough (STI) 70 with this MOS transistor at least.
Then as shown in Figure 7, carry out one first ion and inject (ion implantation) technology 48, form two doped regions with silicon base 42 top layers in grid 46 both sides, be used for regarding lightly doped drain (the lightly doped drain of MOS transistor, LDD) 52, source drain extension just (Source-DrainExtension, SDE).
As shown in Figure 8, utilize an insulating material around the vertical sidewall of grid 46, to form sidewall (spacer) 54 afterwards again.Then as shown in Figure 9, carry out one second ion implantation technology 56, on the silicon base 42 of sidewall 54 outer rims, form two doped regions, as the source electrode (source) 57 and drain electrode (drain) 58 of MOS transistor.
Then as shown in figure 10, be covered on this MOS transistor in forming a dielectric layer 60 on the silicon base 42, and in dielectric layer 60, etch the top that these MOS transistor are led in one first contact hole 62, and the N type well 50 on the 64 sensible silicon base 42 of one second contact hole.Subsequently as shown in figure 11, on dielectric layer 60, form one by tungsten metal level or conductive plunger that other conductive material constitute (plug) in the first contact hole 62 and the second contact hole 64, and be the guiding circuit (bypass) 66 of the part of metal interconnecting, utilize deposition and photoetching technology (photo-etching-process then, PEP), on dielectric layer 60, form required metal interconnecting, and define the pattern of guiding circuit 66 simultaneously, utilize deposition and the photograph and the etching process (PEP) of polysilicon subsequently again, on dielectric layer 60, to form the outage area 68 in the guiding circuit 66, this MOS transistor is formed with N type well 50 to be electrically connected, so that the plasma etching in the subsequent technique (plasma etching), ion bombardment (ion bombardment), the ion that development (photo process) and ultra violet radiation processing steps such as (UV radiation) are accumulated is able to be conducted in the N type well 50 by guiding circuit 66, or allow the ion in the grid 46 be able to be conducted in the N type well 50 by guiding circuit 66, form electrical neutralization with the ion in the N type well 50, suffer plasma damage to reduce grid oxic horizon 44.
Wherein, technology of the present invention also can be prior to forming the outage area 68 in the guiding circuit 66 on the dielectric layer 60, and then form the metal interconnecting layer that is electrically connected this MOS transistor, outage area 68 and N type well 50.In addition, this utilizes the formed outage area 68 of polysilicon also can be formed in grid 46 technologies of this MOS transistor, that is utilizes in the photograph and etching process (PEP) of definition grid 46, forms the pattern of each grid 46 and guiding circuit 66 simultaneously.Finish after plasma etching, ion bombardment, development and ultra violet radiation etc. may cause the technology of plasma damage at last, make the fusion of outage area 68 part leads in a high temperature mode again, or be electrically connected with blocking-up with a laser radiation outage area 68, finish the technology of this MOS transistor.
Than prior art, manufacture method of the present invention is to make this MOS transistor be electrically connected on this N type well by a guiding circuit, so in this grid because plasma etching (plasma etching), the ion that the ultra violet radiation steps such as (UVradiation) of being carried out when ion bombardment (ion bombardment) and development (photo process) is accumulated is able to be conducted in this N type well by this guiding circuit, form electrical neutralization with the ion in this N type well, so can prevent effectively that ion accumulation is in grid, and then produce electric current and infiltrate silicon base, that is be commonly called as the phenomenon of " antenna effect " (antenna effect) from grid.Therefore manufacture method of the present invention can reduce the plasma damage that this grid oxic horizon suffers (plasmaprocess induced damage PPID), slows down the degeneration (degradation) of grid oxic horizon, and then guarantees the normal operation of MOS transistor.
The above only is preferred embodiment of the present invention, and all equivalences of doing according to the scope of claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (20)
1. guiding circuit that the grid oxic horizon that is used for reducing a metal oxide semiconductor transistor suffers plasma damage, this guiding circuit is located on the semiconductor wafer, comprise a substrate on this semiconductor wafer, this metal oxide semiconductor transistor is located in this substrate, one dielectric layer is covered on this metal oxide semiconductor transistor, and this guiding circuit is located on this dielectric layer, and this guiding circuit comprises:
One comprises the lead of one first contact jaw and one second contact jaw at least, and this first contact jaw is electrically connected on a grid conducting layer at this metal oxide semiconductor transistor top, and this second contact jaw then is electrically connected on this suprabasil doped region; And
One outage area is located in this lead, be used for cutting off being electrically connected of this lead and this metal oxide semiconductor transistor, and this guiding circuit is different with the material of this outage area;
Wherein the ion in this grid oxic horizon is conducted in this doped region by this lead, suffers plasma damage to reduce this grid oxic horizon.
2. guiding circuit as claimed in claim 1, wherein this lead is made of a plurality of contact plungers and a metal level.
3. guiding circuit as claimed in claim 1, wherein this lead is the part of a metal interconnecting.
4. guiding circuit as claimed in claim 1, wherein this outage area is made of polysilicon.
5. guiding circuit as claimed in claim 1, wherein this doped region is a N type well.
6. guiding circuit as claimed in claim 1, wherein the ion in this grid oxic horizon forms charge neutrality by the ion in this lead and this doped region, suffers plasma damage to reduce this grid oxic horizon.
7. the grid oxic horizon of minimizing one metal oxide semiconductor transistor suffers the method for plasma damage, and this metal oxide semiconductor transistor is to be located in the substrate of semiconductor wafer, and this method comprises the following steps:
Be covered on this metal oxide semiconductor transistor in forming a dielectric layer in this substrate;
In this dielectric layer, etch the top of sensible this metal oxide semiconductor transistor in one first contact hole, and sensible this suprabasil doped region in one second contact hole;
On this dielectric layer, in this first contact hole and this second contact hole, form a guiding circuit, and in this guiding circuit, be electrically connected an outage area, and this guiding circuit is different with the material of this outage area, is electrically connected so that this metal oxide semiconductor transistor forms with this doped region; And
After finishing the technology of this metal oxide semiconductor transistor, cut off the electrical connection of this outage area;
Wherein the ion in this grid oxic horizon is conducted in this doped region by this guiding circuit, suffers plasma damage to reduce this grid oxic horizon.
8. method as claimed in claim 7, wherein this guiding circuit is made of a metal level.
9. method as claimed in claim 7, wherein this guiding circuit is the part of a metal interconnecting.
10. method as claimed in claim 7, wherein this outage area is made of polysilicon.
11. method as claimed in claim 7, wherein this doped region is a N type well.
12. method as claimed in claim 7, the method for wherein cutting off this outage area are to make this outage area part lead fusion and the blocking-up electrical connection in a high temperature mode.
13. method as claimed in claim 7, the method for wherein cutting off this outage area are with this outage area of a laser radiation.
14. method as claimed in claim 7, wherein this doped region is provided with like this, makes that the ion in this grid oxic horizon forms charge neutrality by the ion in this guiding circuit and this doped region, suffers plasma damage to reduce grid oxic horizon.
15. guiding circuit that the grid oxic horizon that is used for reducing a metal oxide semiconductor transistor suffers plasma damage, this guiding circuit is located on the semiconductor wafer, and comprise a substrate on this semiconductor wafer, at least one metal oxide semiconductor transistor is located in this substrate, and this guiding circuit comprises:
One comprises the lead of one first contact jaw and one second contact jaw at least, and this first contact jaw is electrically connected on a grid conducting layer of this metal oxide semiconductor transistor, and this second contact jaw then is electrically connected on this suprabasil doped region; And
One outage area is located in this lead, is used for cutting off being electrically connected of this lead and this metal oxide semiconductor transistor;
Wherein the ion in this grid oxic horizon is conducted in this doped region by this lead, suffer plasma damage to reduce this grid oxic horizon, and this guiding circuit is different with the material of this outage area.
16. guiding circuit as claimed in claim 15, wherein this lead is made of a plurality of contact plungers and a metal level.
17. guiding circuit as claimed in claim 15, wherein this lead is the part for a metal interconnecting.
18. guiding circuit as claimed in claim 15, wherein this outage area is made of polysilicon.
19. guiding circuit as claimed in claim 15, wherein this doped region is a N type well.
20. guiding circuit as claimed in claim 15, wherein this doped region is provided with like this, makes that the ion in this grid oxic horizon forms charge neutrality by the ion in this lead and this doped region, suffers plasma damage to reduce grid oxic horizon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01117696 CN1205673C (en) | 2001-05-16 | 2001-05-16 | Current guiding circuit for reducing plasma damage and semiconductor making method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01117696 CN1205673C (en) | 2001-05-16 | 2001-05-16 | Current guiding circuit for reducing plasma damage and semiconductor making method |
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| Publication Number | Publication Date |
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| CN1385907A CN1385907A (en) | 2002-12-18 |
| CN1205673C true CN1205673C (en) | 2005-06-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 01117696 Expired - Fee Related CN1205673C (en) | 2001-05-16 | 2001-05-16 | Current guiding circuit for reducing plasma damage and semiconductor making method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100507702B1 (en) * | 2003-04-03 | 2005-08-09 | 주식회사 하이닉스반도체 | Method of forming a metal line in a semiconductor device |
| CN101789444A (en) * | 2010-01-28 | 2010-07-28 | 上海宏力半导体制造有限公司 | First layer of metal capable of increasing breakdown voltage of MOS transistor |
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Granted publication date: 20050608 Termination date: 20100516 |