CN1203540C - Manufacture of double-embedded structure - Google Patents
Manufacture of double-embedded structure Download PDFInfo
- Publication number
- CN1203540C CN1203540C CN 01139647 CN01139647A CN1203540C CN 1203540 C CN1203540 C CN 1203540C CN 01139647 CN01139647 CN 01139647 CN 01139647 A CN01139647 A CN 01139647A CN 1203540 C CN1203540 C CN 1203540C
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric layer
- double
- embedded structure
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a manufacturing method of a double-embedded structure, which comprises the following steps: a substrate with a formed conducting layer is provided first; a first dielectric layer, a second dielectric layer and a top cap layer as a bottom anti-reflecting layer are successively formed on the substrate; the top cap layer, the second dielectric layer and the first dielectric layer are defined to form a dielectric layer window opening to expose the conducting layer; a negative light resisting layer is formed on the top cap layer, and the negative light resisting layer is patterned to form an opening; the exposed top cap layer and the second dielectric layer are removed to form a channel which exposes the first dielectric layer with taking the negative light resisting layer as a mask, and then the negative light resisting layer is removed; a conformal barrier layer and a conductor layer are formed in the channel and the dielectric layer window opening, and the conductor layer fills up the channel and the dielectric layer window opening.
Description
Technical field
The invention relates to a kind of manufacture method of multiple internal connecting lines (Multi-LevelInterconnects) of semiconductor element, and particularly relevant for the manufacture method of a kind of double-embedded structure (DualDamascene).
Background technology
In semiconductor technology, the binding of each element mainly is by lead, and the linking portion of lead and integrated circuit component is commonly referred to as contact hole (Contact), and the binding between lead and lead then is called interlayer hole (Via).The resistance of lead itself and the size of the parasitic capacitance between lead are for influencing one of decisive key of element speeds.Therefore, after semiconductor technology enters the deep-sub-micrometer field, often utilize copper to replace aluminum and make intraconnections, and be used metal intermetallic dielectric layer (the Inter-Metal Dielectrics of low-k (Low K) material, IMD), resist the ability of electromigration (Electromigration) with effective reduction resistance capacitance late effect (RC Delay) and lifting.This is because the electromigration resistance value of copper is 30 to 100 times of aluminium, and the interlayer hole resistance value reduces by 10 to 20 times, and resistance value reduces by 30%.Moreover, because etch copper is very very difficult,, the general using mosaic technology makes the copper metal interconnecting so replacing traditional direct definition mode of lead.
General dual damascene process comprises that interlayer hole aims at dual-inlaid (Self-AlignedDual Damascene voluntarily, SADD), the lead irrigation canals and ditches define dual-inlaid (Trench First DualDamascene earlier, TFDD), first definition dual-inlaid (Via First Dual Damascene, the mode such as VFDD) of interlayer hole.
Please refer to Figure 1A to Fig. 1 E, define the manufacturing process profile of double-embedded structure for known a kind of interlayer hole earlier.At first, please refer to Figure 1A, in the substrate 100 that is formed with lead 102, form protective layer 104, dielectric layer 106, etch stop 108, dielectric layer 110, cap layer 112 and bottom layer anti-reflection layer 114 in regular turn.Then, on bottom layer anti-reflection layer 114, form positive photoresist layer 116 again, and with the positive photoresist layer 116 of little shadow imaging technique patterning, to form opening 117, it defines the position of interlayer hole opening.Then, serve as that the cover curtain removes part bottom layer anti-reflection layer 114, cap layer 112, dielectric layer 110, etch stop 108 and dielectric layer 106 with positive photoresist layer 116, to form an interlayer hole opening 118 that exposes protective layer 104.
Then, please refer to Figure 1B, after removing positive photoresist layer 116 and bottom layer anti-reflection layer 114, in substrate 100, form one deck ditch filling chock bed of material 120 to fill up interlayer hole opening 118.Carry out an etch back process then, remove the interlayer hole opening 118 ditch filling chock bed of material 120 in addition.Then, in substrate 100, form bottom layer anti-reflection layer 122 and positive photoresist layer 124 in regular turn, again with little shadow imaging technique with positive photoresist layer 124 patternings forming opening 125, in order to definition after a while with the position of the irrigation canals and ditches that form.
Then, please refer to Fig. 1 C, serves as the cover curtain with positive photoresist layer 124, removes part bottom layer anti-reflection layer 122, cap layer 112 and dielectric layer 110 to form irrigation canals and ditches 126, also can remove the part ditch filling chock bed of material 120 simultaneously.Then, remove positive photoresist layer 124 and bottom layer anti-reflection layer 122 again.
Then, please refer to Fig. 1 D, after removing the ditch filling chock bed of material 120, remove the partial protection layer 104 that partially-etched suspension layer 108 that opening 126 exposed and interlayer hole opening 118 are exposed, and expose the surface of the lead 102 in the substrate 100.
Then, please refer to Fig. 1 E, in substrate 100, form the conformal barrier layer 128 of one deck earlier, in substrate 100, form one deck conductor layer 130 again, to fill up interlayer hole opening 118 and irrigation canals and ditches 126.Then, carry out planarization with chemical mechanical milling method again, to remove interlayer hole opening 118 and irrigation canals and ditches 126 unnecessary conductor layer 130 and barrier layer 128 in addition.
Define in the dual-metal inserting technology earlier at above-mentioned interlayer hole, need in interlayer hole opening 118, form a ditch filling chock bed of material 120 and residue in the interlayer hole opening 118, and then prevent that the resistance of interlayer hole connector and the resistance capacitance late effect of element from raising because of residual positive photoresistance to prevent positive photoresist layer 124.But, tighten to 0.13 micron or more hour, fill out the ditch material and promptly be difficult to insert the opening of depth-width ratio (Aspect Ratio) greater than 5 in live width.And, after removing the ditch underfill material, having corner (Comer) that part ditch underfill material remains in 126 in interlayer hole opening 118 and irrigation canals and ditches goes up and forms a palisade (Fence) structure 132 of surrounding interlayer hole opening 118, so when deposition barrier layer 128, barrier layer 128 can be blocked by palisade (Fence) structure and reduce its obstacle function, and cause between metal connecting line bridge joint improperly, even make component failure.
In addition, be serve as the cover curtain during definition interlayer hole opening 118 in the known technology with positive photoresist layer 116, directly remove bottom layer anti-reflection layer 114, cap layer 112, dielectric layer 110, etch stop 108 and dielectric layer 106 till exposure protective layer 104.Yet, the etch depth required owing to continuous etching two layers of dielectric layer is very big, therefore positive photoresist layer 116 needs suitable thickness just can be used for defining interlayer hole opening 118, and cause the cost of photoresistance to increase, and thicker positive photoresist layer 116 problem that also can produce the lithography process degradation and peel off or drop.
In addition, the advanced low-k materials that known technology uses must have and is lower than 3 dielectric constant, for example be vapour deposition macromolecule (Vapor-Phase Deposition Polymers, VPDP), spin-coating dielectric medium (Spin-on Dielectric, SOD) or spin-on glasses (Spin-on Glass, SOG) etc., its compactness, (Mechanical Strength) is all less for hardness and mechanical strength, so when being subjected to stress, cause the distortion (Deformation) of interlayer hole structure easily because of the existence of interlayer hole opening, and then form weak spot (Weak Point) and cause defective, and influence the element qualification rate.
Summary of the invention
Therefore, a purpose of the present invention can be kept acceptable resistance capacitance and postpone (RC Delay) characteristic for proposing a kind of manufacture method of double-embedded structure, improves element efficiency.
Another object of the present invention can increase critical size (Critical Dimension, consistency CD), and the cost of minimizing photoresistance and increase process margin for proposing a kind of manufacture method of double-embedded structure.
A further object of the present invention can prevent the distortion of interlayer hole opening for proposing a kind of manufacture method of double-embedded structure.
According to above-mentioned purpose; the present invention proposes a kind of manufacture method of double-embedded structure, and the method is to form a protective layer, one first dielectric layer, an etch stop, one second dielectric layer and a cap layer as bottom layer anti-reflection layer in the substrate that forms a conductive layer in regular turn.Then define the cap layer and second dielectric layer, to form first opening that exposes etch stop, in order to define the position of an interlayer hole opening.Then, on cap layer, form a patterning negative photoresist layer, in order to define the position of irrigation canals and ditches with one second opening.Then remove the cap layer that second opening is exposed, and remove the etch stop that first opening is exposed, remove second dielectric layer that second opening exposed again to form irrigation canals and ditches, remove first dielectric layer that first opening exposed simultaneously to form an interlayer hole opening.Then, remove the protective layer that the interlayer hole opening is exposed.Remove negative photoresist layer then, in irrigation canals and ditches and interlayer hole opening, form a conformal barrier layer and a conductor layer more in regular turn, and conductor layer fills up irrigation canals and ditches and interlayer hole opening.
In addition, the present invention also can adopt the mode of definition interlayer hole opening earlier, forms one first dielectric layer, one second dielectric layer and a bottom layer anti-reflection layer in the substrate that forms conductive layer in regular turn.Then define bottom layer anti-reflection layer, second dielectric layer and first dielectric layer to form an interlayer hole opening that exposes conductive layer.Form a negative photoresist layer on bottom layer anti-reflection layer, this negative photoresist layer of patterning is to form an opening.Then, with the negative photoresist layer cover curtain, remove anti-reflecting layer that opening exposes and second dielectric layer to form irrigation canals and ditches of exposure first dielectric layer.Remove negative photoresist layer then, in irrigation canals and ditches and interlayer hole opening, form again a conformal barrier layer and on a conductor layer, and conductor layer fills up irrigation canals and ditches and interlayer hole opening.
Because the present invention utilizes negative photoresistance definition irrigation canals and ditches pattern, and can remove by developer solution at the unexposed negative photoresist layer of trench regions, so can not cause photoresistance residual.Therefore, need in the interlayer hole opening, not form the ditch filling chock bed of material when adopting this method, can keep acceptable resistance capacitance and postpone (RC Delay) characteristic, simultaneously because do not form the ditch filling chock bed of material yet, so can on the corner of interlayer hole opening and irrigation canals and ditches, not form grating structure, and can prevent between metal connecting line bridge joint and component failure improperly.
In addition, one of institute of the present invention extracting method is to utilize local etching technique to define the double-embedded structure of compound advanced low-k materials, and use anti-etching can the employed positive photoresistance of force rate known technology strong negative photoresistance, therefore the thickness of negative photoresist layer does not need too thick, and can increase the consistency of critical size, and can reduce cost and increase process margin.And use the dielectric layer of the comparatively fine and close advanced low-k materials of structure as double-metal inlaid structure, to prevent the distortion of interlayer hole hatch frame.
In addition, directly utilize the bottom layer anti-reflection layer of cap layer, therefore do not need on cap layer, to form in addition bottom layer anti-reflection layer, can reduce cost as definition interlayer hole opening and irrigation canals and ditches.
Description of drawings
Figure 1A to Fig. 1 E is the manufacturing process profile of known a kind of double-embedded structure.
Fig. 2 A and Fig. 2 F are the manufacturing process profiles according to the double-embedded structure of one embodiment of the invention.
Description of reference numerals:
100,200: substrate
102,202: lead
104,204: protective layer
108,208: etch stop
106,110,206,210: dielectric layer
112,212: cap layer
114,122: bottom layer anti-reflection layer
116,124: positive photoresist layer
117,125,216,218,222,223: opening
118,219: the interlayer hole opening
126,223: irrigation canals and ditches
120: the ditch filling chock bed of material
128,224: barrier layer
130,226: conductor layer
132: grating structure
214: photoresist layer
220: negative photoresist layer
Embodiment
The manufacturing process of a kind of double-embedded structure of the embodiment of the invention is to illustrate with Fig. 2 A to Fig. 2 F.
Please refer to Fig. 2 A, a substrate 200 (for simplicity, the element in the substrate 200 is not drawn) at first is provided.This substrate 200 has a lead 202.Then, in substrate 200, form protective layer 204, dielectric layer 206, etch stop 208, dielectric layer 210 and cap layer 212 in regular turn.
Wherein, protective layer 204 for example is a silicon nitride with the material of etch stop 208, its formation method for example be chemical vapour deposition technique (Chemical Vapor Deposition, CVD).
In addition, the material of cap layer 212 is the bottom antireflection material that can be used as photoresist layer, and it for example is silicon oxynitride (SiON), and the method that forms cap layer 212 for example is a chemical vapour deposition technique.
Then, on cap layer 212, form one deck photoresist layer 214 again.The material of this photoresist layer 214 can be positive photoresistance or negative photoresistance.Then, patterning photoresist layer 214 is to form an opening 216, in order to the position of definition interlayer hole opening.Serve as the cover curtain then, remove cap layer 212 and the opening 218 of dielectric layer 210 that opening 216 is exposed with formation expose portion etch stop 208 with photoresist layer 214.
Please refer to Fig. 2 B, remove photoresist layer 214 then fully, on cap layer 212, form one deck negative photoresist layer 220 again.Then, patterning negative photoresist layer 220 is to form an opening 222, in order to the position of definition irrigation canals and ditches.So the reason of using negative photoresistance herein is as follows: because positive photoresistance is that irradiation partly produces decomposition reaction, negative photoresistance is that irradiation partly produces the link reaction, so when using positive photoresistance to define irrigation canals and ditches, positive photoresistance in the irrigation canals and ditches bottom may decompose by irradiation, and remain in the interlayer hole open bottom, it is residual to prevent photoresist layer therefore need to fill up the interlayer hole opening at the preceding formation one ditch filling chock bed of material of definition irrigation canals and ditches.On the contrary, when using negative photoresistance to define irrigation canals and ditches, the unexposed negative photoresistance that is positioned at the irrigation canals and ditches part does not link, so can remove with developer solution easily, do not residue in the interlayer hole opening and do not have the negative photoresistance of part, therefore need not forming a ditch filling chock bed of material before the definition irrigation canals and ditches, to fill up the interlayer hole opening residual to prevent photoresist layer.
Then, please refer to Fig. 2 C, serves as cover curtain with negative photoresist layer 220, removes 222 exposed portions cap layers 212 of opening exposing part dielectric layer 210, and removes 218 exposed portions etch stop 208 of opening to expose part dielectric layer 206.The method that removes part cap layer 212 and etch stop 208 for example is non-etc. to etching method.
Then; please refer to Fig. 2 D; with negative photoresist layer 220 is cover curtain, removes dielectric layer 210 that opening 222 exposed forming the irrigation canals and ditches 223 of expose portion etch stop 208, and removes dielectric layer 206 that opening 218 (Fig. 2 C) exposed to form the interlayer hole opening 219 of expose portion protective layer 204.
Then, please refer to Fig. 2 E, serves as cover curtain with negative photoresist layer 220, removes etch stop 208 that irrigation canals and ditches 223 expose exposing part dielectric layer 206, and removes protective layer 204 that interlayer hole opening 219 exposed to expose part lead 202.The method that removes partially-etched suspension layer 208 and protective layer 204 for example is non-etc. to etching method.
Then, please refer to Fig. 2 F, after removing negative photoresist layer 220, in substrate 200, form conformal one deck barrier layer 224 earlier.The material of barrier layer 224 for example is tantalum nitride (TaN), titanium nitride or titanium silicon nitride.Then, form a conductor layer 226 on barrier layer 224, and fill up opening 218 and opening 222.The method that forms conductor layer 226 for example be physical vaporous deposition (Physical Vapor Deposition, PVD), chemical vapour deposition technique or sputtering method.This conductor layer 226 for example is the copper metal.
Then, carry out chemical mechanical milling tech, remove irrigation canals and ditches 223 part metals layer 226 and barrier layer 224 in addition, till cap layer 212 comes out, and form double-embedded structure.
The foregoing description is the mode that local etching (Partial Etching) technology definition double-metal inlaid structure is adopted in explanation.
In addition, the present invention also can adopt the mode of direct definition interlayer hole opening, directly defines bottom layer anti-reflection layer 212, dielectric layer 210 and the interlayer hole opening 219 of dielectric layer 206 with formation exposed leads 202.Form a negative photoresist layer 220 then on bottom layer anti-reflection layer 212, patterning negative photoresist layer 220 is to form an opening 222.Then, serve as the cover curtain with negative photoresist layer 220, remove bottom layer anti-reflection layer 212 and the irrigation canals and ditches 223 of dielectric layer 210 that opening 222 is exposed with formation exposed dielectric layer 206.Remove negative photoresist layer 220 then, in irrigation canals and ditches 223 and interlayer hole opening 219, form again a conformal barrier layer 224 and on a conductor layer 226, and conductor layer 226 fills up irrigation canals and ditches 223 and interlayer hole opening 219.
The dual damascene process of the invention described above embodiment has following advantage:
(1) utilizes negative photoresistance definition irrigation canals and ditches pattern, and can remove with developer solution easily, do not residue in the interlayer hole opening so do not have photoresistance at the unexposed negative photoresist layer of trench regions.Therefore, need in the interlayer hole opening, not form the ditch filling chock bed of material, promptly can keep acceptable resistance capacitance and postpone (RC Delay) performance, simultaneously because do not form the ditch filling chock bed of material yet, so can on the corner of interlayer hole opening and irrigation canals and ditches, not form grating structure, and can prevent that barrier layer from being blocked by grating structure, and then prevent between metal connecting line bridge joint improperly and the component failure that is caused thereof.
(2) utilize local etching technique to define the double-metal inlaid structure of compound advanced low-k materials, and use anti-etching can the positive photoresistance of force rate strong negative photoresistance, therefore the thickness of photoresist layer does not need too thick, and can increase the consistency of critical size, can reduce the cost of photoresistance simultaneously and increase explained hereafter usefulness.
(3) use the dielectric layer of the comparatively fine and close advanced low-k materials of structure, with distortion and the damage that prevents the interlayer hole hatch frame as double-metal inlaid structure.
(4) utilize the anti-reflecting layer of cap layer, therefore do not need to form in addition bottom anti-reflection layer, can reduce cost as definition interlayer hole opening and irrigation canals and ditches.
Though the present invention with embodiment explanation as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when being as the criterion with claims.
Claims (20)
1. the manufacture method of a double-embedded structure, this method comprises:
One substrate is provided, and this substrate has a conductive layer;
In this substrate, form a protective layer, one first dielectric layer, one second dielectric layer and a cap layer in regular turn;
Define this cap layer and this second dielectric layer, to form one first opening, in order to define the position of an interlayer hole opening;
Form a patterning negative photoresist layer on this cap layer, this patterning negative photoresist layer has one second opening, in order to define the position of irrigation canals and ditches;
Remove this cap layer that this second opening is exposed;
Remove this second dielectric layer that this second opening exposed to form this irrigation canals and ditches, remove this first dielectric layer that this first opening exposed simultaneously to form this interlayer hole opening;
Remove this protective layer that this interlayer hole opening is exposed;
Remove this negative photoresist layer; And
In these irrigation canals and ditches and this interlayer hole opening, form a conformal barrier layer and on a conductor layer, this conductor layer fills up these irrigation canals and ditches and this interlayer hole opening, it is characterized by:
When in this substrate, forming this protective layer, this first dielectric layer, this second dielectric layer, more be included in formation one etch stop between this first dielectric layer and this second dielectric layer, and this cap layer while is as a bottom layer anti-reflection layer with this cap layer;
When defining this cap layer and this second dielectric layer, this first opening more exposes the surface of this etch stop; And
When removing this cap layer that this second opening exposed, remove this etch stop that this first opening is exposed simultaneously.
2. the manufacture method of double-embedded structure as claimed in claim 1, it is characterized by: the material of this first dielectric layer is selected from fluorine silicon glass or undoped silicon glass.
3. the manufacture method of double-embedded structure as claimed in claim 2 is characterized by: the method that forms this first dielectric layer comprises that plasma promotes chemical vapour deposition technique or high density plasma CVD method.
4. the manufacture method of double-embedded structure as claimed in claim 1 is characterized by: the material of this first dielectric layer is selected from poly-arylene ether, fluoridizes poly-arylene ether or silane sesquichloride.
5. the manufacture method of double-embedded structure as claimed in claim 4, it is characterized by: the method that forms this first dielectric layer comprises method of spin coating or chemical vapour deposition technique.
6. the manufacture method of double-embedded structure as claimed in claim 1, it is characterized by: the material of this second dielectric layer is selected from fluorine silicon glass or undoped silicon glass.
7. the manufacture method of double-embedded structure as claimed in claim 6 is characterized by: the method that forms this second dielectric layer comprises that plasma promotes chemical vapour deposition technique or high density plasma CVD method.
8. the manufacture method of double-embedded structure as claimed in claim 1 is characterized by: the material of this second dielectric layer is selected from poly-arylene ether, fluoridizes poly-arylene ether or silane sesquichloride.
9. the manufacture method of double-embedded structure as claimed in claim 8, it is characterized by: the method that forms this second dielectric layer comprises method of spin coating or chemical vapour deposition technique.
10. the manufacture method of double-embedded structure as claimed in claim 1, it is characterized by: the material of this cap layer comprises silicon oxynitride.
11. the manufacture method of double-embedded structure as claimed in claim 10 is characterized by: the method that forms this cap layer comprises chemical vapour deposition technique.
12. the manufacture method of a double-embedded structure, this method comprises:
One substrate is provided, has a conductive layer in this substrate;
In this substrate, form one first dielectric layer and one second dielectric layer in regular turn;
Define this second dielectric layer and this first dielectric layer to form an interlayer hole opening;
On this second dielectric layer, form a negative photoresist layer;
This negative photoresist layer of patterning is to form an opening;
With this negative photoresist layer is cover curtain, removes this bottom layer anti-reflection layer that this opening exposes and this second dielectric layer to form irrigation canals and ditches of this first dielectric layer of exposure;
Remove this negative photoresist layer;
In these irrigation canals and ditches and this interlayer hole opening, form a conformal barrier layer and on a conductor layer, this conductor layer fills up these irrigation canals and ditches and this interlayer hole opening, it is characterized by:
When in this substrate, forming this first dielectric layer and this second dielectric layer successively, more be included in and form a bottom layer anti-reflection layer on this second dielectric layer;
When defining this second dielectric layer and this first dielectric layer, more comprise this bottom layer anti-reflection layer of definition, to form this dielectric window opening that exposes this conductive layer; And
When forming these irrigation canals and ditches that expose this first dielectric layer, more comprise removing this bottom layer anti-reflection layer that this opening exposes.
13. the manufacture method of double-embedded structure as claimed in claim 12 is characterized by: the material of this first dielectric layer and this second dielectric layer all is selected from fluorine silicon glass, undoped silicon glass, poly-arylene ether, fluoridizes poly-arylene ether or silane sesquichloride.
14. the manufacture method of double-embedded structure as claimed in claim 12 is characterized by: the method that forms this first dielectric layer and this second dielectric layer comprises method of spin coating or chemical vapour deposition technique.
15. the manufacture method of double-embedded structure as claimed in claim 12 is characterized by: the material of this bottom layer anti-reflection layer comprises silicon oxynitride.
16. the manufacture method of double-embedded structure as claimed in claim 12 is characterized by: the method that forms this bottom layer anti-reflection layer comprises chemical vapour deposition technique.
17. the manufacture method of double-embedded structure as claimed in claim 12, it is characterized by: this first dielectric layer is that one first dielectric layer with low dielectric constant and this second dielectric layer are one second dielectric layer with low dielectric constant, and the mechanical strength of this first dielectric layer with low dielectric constant is greater than the mechanical strength of this second dielectric layer with low dielectric constant.
18. the manufacture method of double-embedded structure as claimed in claim 17 is characterized by: the material of this first dielectric layer with low dielectric constant is selected from fluorine silicon glass or undoped silicon glass.
19. the manufacture method of double-embedded structure as claimed in claim 17 is characterized by: the material of this second dielectric layer with low dielectric constant is selected from poly-arylene ether, fluoridizes poly-arylene ether or silane sesquichloride.
20. the manufacture method of double-embedded structure as claimed in claim 17 is characterized by: the material of this cap layer comprises silicon oxynitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01139647 CN1203540C (en) | 2001-11-30 | 2001-11-30 | Manufacture of double-embedded structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01139647 CN1203540C (en) | 2001-11-30 | 2001-11-30 | Manufacture of double-embedded structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1421915A CN1421915A (en) | 2003-06-04 |
| CN1203540C true CN1203540C (en) | 2005-05-25 |
Family
ID=4675333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01139647 Expired - Lifetime CN1203540C (en) | 2001-11-30 | 2001-11-30 | Manufacture of double-embedded structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1203540C (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100389488C (en) * | 2003-12-30 | 2008-05-21 | 中芯国际集成电路制造(上海)有限公司 | Method and apparatus for controlling etching-back cross section figure |
| US7390739B2 (en) * | 2005-05-18 | 2008-06-24 | Lazovsky David E | Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region |
| US20060205232A1 (en) * | 2005-03-10 | 2006-09-14 | Lih-Ping Li | Film treatment method preventing blocked etch of low-K dielectrics |
| CN100453323C (en) * | 2005-07-13 | 2009-01-21 | 国际联合科技股份有限公司 | Ink-jetting nozzle and its procedure |
| CN100407402C (en) * | 2005-08-18 | 2008-07-30 | 联华电子股份有限公司 | Method of manufacturing inner interconnection wires |
| DE102006044591A1 (en) * | 2006-09-19 | 2008-04-03 | Carl Zeiss Smt Ag | Optical arrangement, in particular projection exposure apparatus for EUV lithography, as well as reflective optical element with reduced contamination |
| CN102569156A (en) * | 2010-12-08 | 2012-07-11 | 上海华虹Nec电子有限公司 | Manufacturing method of buried layer of semiconductor device |
-
2001
- 2001-11-30 CN CN 01139647 patent/CN1203540C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1421915A (en) | 2003-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1191623C (en) | Method for making double inlaying latch by using metal hard shielding layer | |
| US7157366B2 (en) | Method of forming metal interconnection layer of semiconductor device | |
| CN1831643A (en) | Method for forming dual damascene with improved etch profiles | |
| CN1828845A (en) | Inlaid structure and its forming method | |
| CN1815711A (en) | Interconnect structure and method of forming the same | |
| CN1835206A (en) | Method of forming double-setting line arrange for semiconductor device using protective access cover layer | |
| CN1599028A (en) | Metal-insulator-metal capacitor and interconnecting structure | |
| CN1812074A (en) | Methods for forming interconnecting structure and semiconductor devices | |
| CN101063065A (en) | Cleaning porous low-k material in the formation of an interconnect structure | |
| CN1799138A (en) | Interconnect structures in integrated circuit devices | |
| CN1967845A (en) | Semiconductor device and its manufacturing method | |
| CN101079408A (en) | Double-inlay structure and its making method | |
| CN1728358A (en) | The manufacture method of dual damascene interconnection | |
| CN1343372A (en) | Air gap dielectric in self-aligned via structures | |
| CN1677643A (en) | Method of manufacturing a semiconductor device having damascene structures with air gaps | |
| CN1469467A (en) | Semiconductor device and producing method thereof | |
| CN1822329A (en) | Semiconductor and method for fabricating the same | |
| CN1466190A (en) | Method for forming copper metal line | |
| CN1238892C (en) | Method for mfg. double inlaid structure | |
| CN1115725C (en) | Process for forming multilevel interconnection structure | |
| CN1203540C (en) | Manufacture of double-embedded structure | |
| CN101055421A (en) | Method for forming double inserted structure | |
| CN1278409C (en) | Manufacturing method of semiconductor device and semiconductor device | |
| CN1199266C (en) | Semiconductor device and its manufacture | |
| KR20040102981A (en) | A method for forming a metal line of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20050525 |
|
| CX01 | Expiry of patent term |