CN1202737A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN1202737A
CN1202737A CN98102275A CN98102275A CN1202737A CN 1202737 A CN1202737 A CN 1202737A CN 98102275 A CN98102275 A CN 98102275A CN 98102275 A CN98102275 A CN 98102275A CN 1202737 A CN1202737 A CN 1202737A
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China
Prior art keywords
layer
type
conductive type
depletion
voltage
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Pending
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CN98102275A
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Chinese (zh)
Inventor
小林研也
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NEC Corp
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NEC Corp
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Publication of CN1202737A publication Critical patent/CN1202737A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention provides a semiconductor device to obtain a high withstand voltage with a shallow diffused layer Source and gate terminals are short-circuited and reverse bias is applied between it and a drain terminal 27 so as to form first, and second depletion layers 29-1, 29-2 according to applied voltages at p-n junctions between a p-type drain layer 20 and n-type well layer 19 and between a p-type semiconductor Si substrate 1A and well layer 19. The applied voltages lower to couple the first layer 29-1 with the second layer 29-2 to form a single depletion layer 29.

Description

Semiconductor device
The present invention relates to semiconductor device, especially have the semiconductor device of high-breakdown-voltage.
Because the cmos semiconductor device electric breakdown strength is higher, therefore be necessary between P passage MOSFET (hereinafter referred to as PMOS) and the N passage MOS FET (hereinafter referred to as NMOS) or between PMOS, NMOS and other element, the element branch is arranged or isolates setting, be independent of each other to reach.For example, be 300 volts or more lower slightly semiconductor for puncture voltage, brought into use self-separation system or self-isolation system, to reduce production costs based on diffusion layer.This diffusion layer that makes element to separate is called as " trap ", and it is formed at the depths of semiconductor chip to keep enough separation puncture voltages.Further, in order to keep the puncture voltage between semiconductor chip and the trap, the concentration of semiconductor chip impurity is lowered, and therefore the impurity concentration of opposite conductivity type trap has expanded a depletion layer to semiconductor one side than semiconductor chip height.Present technique has been published in Japanese patent application publication No. Hei-6-132525.
Fig. 1 is a profile, shows the structure of a kind of high-breakdown-voltage IGBT (igbt), is disclosed in Japanese patent application publication No.: Hei-6-132525.
IGBT shown in Fig. 1 is a kind of horizontal type IGBT of the NPNP of having structure, include a N+ type emitter layer 5, a P type substrate layer 3, a N type trap layer 2 and a P type collector layer 7, wherein N type trap layer 2 is between N+ type emitter layer 5 and P type collector layer 7, and keep certain width, to form the high-breakdown-voltage structure.
P type base layer 3 and N type base layer 6 are positioned at the surface of N type trap layer 2, form the P type semiconductor silicon chip 1 of low impurity concentration, and P+ type base stage contact layer 4 and N+ type emitter layer 5 are positioned at the surface of P type base layer 3.Further, P type collector layer 7, P+ type contact layer 8 and N+ type base stage contact layer 9 are positioned at the surface of N type base layer 6.P+ type substrate contact layer 12 be positioned at N type trap layer 2 on the P type semiconductor silicon chip 1 near.Grid 17 forms by the gate oxidation films that is positioned at N+ type emitter layer 5, P type base layer 3 and N type trap layer 2 surface.Dielectric film 11 (be connected to field oxide film and generate simultaneously with it) is formed by gate oxidation films 10 integral extension, and on the N type trap layer 2 between P type base layer 3 and the N type base layer 6, its thickness is bigger than gate oxidation films 10.Emitter 16 is connected on each N+ type emitter layer 5, P+ type base stage contact layer 4 and the P+ type substrate contact layer 12.Further, emitter terminal 13, grid lead 14 and collector terminal 15 are connected respectively to emitter 16, grid 17 and collector electrode 18.
Here, the impurity concentration of N type trap layer 2 is arranged to the height than P type semiconductor silicon chip 1, so depletion layer mainly expands to the P type silicon chip side at the PN junction place between P type silicon chip 1 and the N type trap layer 2.Therefore can guarantee in the zone of depletion layer expansion, also promptly can improve the puncture voltage of element.
The IGBT of horizontal type as mentioned above, puncture voltage between emitter-collector electrode is determined by the PN junction puncture voltage between N type trap layer 2 and the P type base layer 3, therefore need to improve the distance between P type basic unit 3 and the N type base layer 6, perhaps deepen the degree of depth of P type base layer 3, perhaps adopt other similar approach.When deepening the degree of depth of P type base layer 3, N type trap layer 2 will become darker, and this will produce a problem: need long time could form diffusion layer, and strengthened the area of element.
Even the purpose of this invention is to provide the very narrow semiconductor device that also can realize high-breakdown-voltage of a kind of diffusion layer.
The invention provides a kind of have second conductive type of trap layer that on the first conductivity regions surface portion that forms on the surface portion of semiconductor silicon substrate, forms and the semiconductor device that is formed at impurity diffusion layer on the second conductive type of trap layer, it is characterized by: when applying reverse bias voltage, first depletion layer is expanded from impurity diffusion layer, junction expansion between second depletion layer area, two depletion layers connect each other, exhaust first and second and to be combined into a depletion layer before breakdown, realized high-breakdown-voltage thus.
In this case, a kind of gated transistor is provided, include the first conductive type source layer and the first conductivity type drain electrode layer, it is positioned on the surface portion of the second conductive type well layer, separate each other, grid covers semiconductor chip between the first conductivity type source electrode layer and first conduction depletion layer via gate insulating film, source electrode connects first conductive type source layer to the second conductive type well layer, drain electrode connects the first conductivity type drain electrode layer, and first and second utmost point depletion layers are combined into single depletion layer voltage, can be set between the second conductive type well layer and the first conductivity type drain electrode layer and the puncture voltage of the PN junction between the second conductive type well layer and first conductive area.
In addition, can add the dielectric film that last layer is connected to gate insulating film on the surface of the first conductivity type drain electrode layer selectively, its thickness is greater than thick gate insulating film, so that grid can expand on the thick insulating film.Furtherly, this thick insulating film can generate simultaneously with a field oxide film.
The second conductive type well layer is positioned on first conductive region of surface of semiconductor chip, and impurity diffusion layer is positioned on the second conductive type well layer, forming electronic component, as MOS transistor etc.When applying reverse bias voltage, first depletion layer is expanded from impurity diffusion layer, second depletion layer is expanded since the junction between second the conductive type well layer and first conductivity type regions, being connected to each other before two depletion layers are breakdown respectively becomes independent depletion layer together, has realized high-breakdown-voltage thus.Therefore, just can design impurity diffusion layer and trap layer narrowlyer, and can reduce the area of element.
Fig. 1 is the profile of conventional semiconductor device;
Fig. 2 is the profile of the embodiment of semiconductor device according to the present invention; And
Fig. 3 A and 3B are the working section figure of embodiments of the invention.
Below in conjunction with accompanying drawing the preferred embodiments of the present invention are described.
Fig. 2 is the profile of the preferred embodiment of the present invention.
As shown in Figure 2, one embodiment of the present of invention are horizontal type PMOS, include a P type drain electrode layer 20, a N type trap layer 19 and a P+ type source layer 22, and the P type drain electrode layer 20 between P+ type source layer 22 and the P+ type drain electrode layer 21 is very wide, has realized the high-breakdown-voltage structure thus.
As shown in Figure 2, P+ type source layer 22 and N+ type trap contact layer 23 are formed at the surface of N type trap layer 19, and N type trap layer 19 is positioned at the surface of P type low impurity concentration semiconductor silicon substrate 1A.P+ type drain contact layer 21 is positioned at the surface of P type drain electrode layer 20.Further, P+ type substrate contact layer 12A is positioned at the surface of P type semiconductor silicon chip 1A, with adjacent with N type trap layer 19.Grid 17A is formed at the surface of P+ type source layer 22, N type trap layer 19 and P type drain electrode layer 20 via gate oxidation films 10A.Further, silicon oxide layer 11A (be connected on the field oxide film and [do not illustrate], and form simultaneously with it when field oxide film forms) integrally expands from gate oxidation films 10A, is positioned at the surface of P type drain electrode layer 20.Drain electrode 24 is connected to P+ type drain electrode contact layer 21, and source electrode 25 is connected to P+ type source layer 22 and N+ type trap contact layer 23, and base stage 26 is connected to P+ type substrate contact layer 12A.Drain lead 27 is connected to drain electrode 24, and grid lead 14A is connected to grid 17A, and source lead 28 is connected to source electrode 25.When drain voltage is applied on the drain lead 27, also be applied to P+ type substrate contact layer 12A.This is because this description is based on the strictest semiconductor device breakdown condition and is described.
Below, with reference to Fig. 3 A and 3B the work of high-breakdown-voltage PMOS pipe among Fig. 2 is described.
When source lead 28 with grid lead 14A is shorted to together and to these lead-in wires and drain electrode end line 27 when applying reverse bias voltage, the PN junction place between the PN junction between P type drop ply 20 and the N type trap layer 19 and P type semiconductor silicon chip 1A and N type trap layer 19 form respectively with corresponding first depletion layer 29-1 of the voltage that applies and the second depletion layer 29-2 (Fig. 3 A).When the voltage that applies strengthened, the first depletion layer 29-1 and the second depletion layer 29-2 were connected to each other to an independent depletion layer 29 (Fig. 3 B).When the electric field strength of each depletion layer reached critical value, the PN junction between the PN junction between N type trap layer 19 and the P type drop ply 20 and N type trap layer 19 and the P type semiconductor silicon chip 1A might be breakdown.If the voltage of first depletion layer and second depletion layer becomes independent depletion layer 29 together, the puncture voltage of this layer is made as the puncture voltage that is lower than these two PN junctions, because the electric field strength reduction, so puncture voltage improves.This is that the warp architecture than low edge of first depletion layer make that the most concentrated original electric field has been disperseed, and the thickness of depletion layer has strengthened also owing to compare with the PN junction between P type drop ply 20 and the N type trap layer 19.
A specific embodiment of the present invention is described below.
Puncture voltage is that the COMS integrated circuit of 200V between 300V is formed at P type silicon chip 1A when going up, and the impurity concentration of substrate is set to about 3 * 10 14To 7 * 10 14Centimetre -3Usually, NMOS is formed on the p type island region territory of P type silicon semiconductor substrate 1A, and PMOS is positioned at N type trap layer 19, and the latter is positioned on the surface portion of P type silicon chip 1A.N type trap layer 19 also is used as the element separating layer.Inject or heat treatment process by ion, make the maximum concentration of impurity be approximately 1 * 10 16Centimetre -3, junction depth is approximately 7 μ rice, forms N type trap layer 19.P type drop ply 20 is positioned on the surface of N type trap layer 19, and the maximum concentration of all impurity is approximately 1 * 10 16Centimetre -3, junction depth is approximately 1.5 nanometers.The thickness of gate oxidation films 10A is determined by the maximum voltage that is applied to grid.Need increase the thickness of Silicon-On-Insulator oxide-film 11A as much as possible, to reduce the electric field strength that is applied to P type drop ply 20A from grid 17A, dielectric film 11A and field oxide generate simultaneously.P+ type drain contact layer 21 and P+ type substrate contact layer 12A and P+ type source layer 22 and N+ type trap contact layer 23 are connected respectively to drain electrode 24/ base stage 26 and source electrode 25, therefore need increase the impurity concentration of these laminar surfaces as much as possible.
In the PMOS that forms like this, when source lead 28 and grid lead 14A short circuit and when the reverse bias voltage that drain lead 27 and source lead 28 apply increases, the PN junction place of depletion layer between P type drop ply 20 and N type trap layer 19 and the PN junction place expansion of P type semiconductor silicon chip 1A and N type trap layer 19.In the present embodiment, these depletion layers are connected one to the other to before breakdown respectively becomes an independent depletion layer together.
More than describe at PMOS.For CMOS, NMOS is positioned at the surface of P type silicon chip 1A, and its drain electrode is connected to the drain electrode of PMOS.In Fig. 2, drain lead 27 is connected to base stage 26, is in order to be set to the strictest voltage conditions.But for this situation of CMOS, the drain lead 27 of PMOS is connected to the drain electrode of NMOS, and the source electrode of NMOS is connected to P+ type substrate contact layer 12A.The structure of NMOS is by replacing with P type trap layer, N type drop ply, N+ type drain contact layer, N+ type source layer and P+ type substrate contact layer to the N type trap layer 19 among Fig. 2, Fig. 3 A and Fig. 3 B, P type drop ply 20, P+ type drain contact layer 21, P+ type source layer 22 and N+ type trap contact layer 23 respectively, and its structure is the same.
Further, the PMOS with the NMOS of low breakdown voltage and low breakdown voltage is formed on P type silicon semiconductor substrate 1A and the narrow N type trap layer, and the latter separates from N type trap layer 19.

Claims (4)

1. semiconductor device, has the second conductive type well layer, this layer is formed at the surface of first conductive area, the latter is positioned at the surface of semiconductor chip, and impurity diffusion layer, it is formed at the surface of the second conductive type well layer, it is characterized by: when applying reverse voltage, first depletion layer begins expansion from said impurity diffusion layer, second depletion layer begins expansion from said second conductive type well layer and the said first conductive region junction, before said first depletion layer and second depletion layer were breakdown, they were interconnected into an independent depletion layer, have realized high-breakdown-voltage thus.
2. as said semiconductor device in the claim 1, wherein provide a gated transistor, comprised the first conductive type source layer and the first conductivity type drop ply, they are formed at the surface of the second conductive type well layer, to reach the purpose that is separated from each other; A grid covers the surface of the semiconductor chip between the first conductive type source layer and the first conductivity type drop ply via gate insulating film; A source electrode is connected to the second conductive type well layer to the first conductive type source layer; And drain electrode, be connected to the first conductivity type drop ply, and the voltage that said first depletion layer and second depletion layer are combined into a depletion layer is set to the PN junction between said second conductive type well layer and the said first conductivity type drop ply and the puncture voltage of the PN junction between the said second conductive type well layer and first conductive area.
3. as said semiconductor device in the claim 2, wherein on the surface of the said first conductivity type drop ply, provide as required to be connected on the gate insulating film, and its thickness is greater than the additional dielectric film of gate insulating film, said thus grid expands on the said supplementary insulation film.
4. as said semiconductor device in the claim 3, wherein said additional dielectric film forms simultaneously with field oxide film.
CN98102275A 1997-06-13 1998-06-15 Semiconductor device Pending CN1202737A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP156518/97 1997-06-13
JP9156518A JPH118381A (en) 1997-06-13 1997-06-13 Semiconductor device

Publications (1)

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CN1202737A true CN1202737A (en) 1998-12-23

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CN98102275A Pending CN1202737A (en) 1997-06-13 1998-06-15 Semiconductor device

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KR (1) KR19990006882A (en)
CN (1) CN1202737A (en)

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GB8711212D0 (en) * 1987-05-12 1987-06-17 English Electric Valve Co Ltd Laser apparatus
KR100660917B1 (en) * 1999-02-03 2006-12-26 페어차일드코리아반도체 주식회사 Ldmos

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KR19990006882A (en) 1999-01-25

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