CN1194459A - Packaging body of semiconductor device - Google Patents
Packaging body of semiconductor device Download PDFInfo
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- CN1194459A CN1194459A CN97122211A CN97122211A CN1194459A CN 1194459 A CN1194459 A CN 1194459A CN 97122211 A CN97122211 A CN 97122211A CN 97122211 A CN97122211 A CN 97122211A CN 1194459 A CN1194459 A CN 1194459A
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Abstract
The invention aims at providing a substrate which is welded with a surface mount semiconductor device with good heat and fatigue resistant performance. The package of the semiconductor device is that a group of relative borders of the semiconductor device are equipped with the leading foots; and the semiconductor device is mounted on the substrate in a surface mount way. The invention is characterized in that only the specific leading foots are welded on the mount substrate.
Description
The present invention relates to little gabarit encapsulation (SOP) or quad flat flat raft encapsulation (QFP) etc. is that the surface mount type semiconductor device of representative is installed to packaging body on the installation base plate in the mounted on surface mode.
Be that the surface mount type semiconductor device of representative is well-known with little gabarit encapsulation (SOP) or the encapsulation of quad flat flat raft etc. so far.
Figure 11 represents the perspective view of the state on the substrate 110 that the semiconductor device 100 of general little gabarit encapsulation (SOP) type is installed to.As shown in the figure, the semiconductor device 100 of little gabarit encapsulation (SOP) type is equipped with leading foot 101a～101g and 103a～103g at a pair of opposed side.Make leading foot 101a～101g and 103a～103g bending, so that under the state that semiconductor device is floated from substrate 110, flatly fix.Leading foot 101a～the 101g and the 103a～103g of semiconductor device 100 are welded to respectively on welding portion 102a～102g and the 104a～104g.
Figure 12 represents the perspective view of the state on the substrate 160 that the semiconductor device 150 of general quad flat flat raft encapsulation (QFP) type is installed to.As shown in the figure, be equipped with leading foot 151a～151g, 153a～153g, 155a～155g and 157a～157g on four limits of quad flat flat raft encapsulation (QFP) N-type semiconductor N device 150.The shape leading foot 101a～101g and the 103a～103g as shown in figure 11 of each leading foot is crooked in an identical manner.The whole leading foot 151a～151g that are equipped with on the semiconductor device 150,153a～153g, 155a～155g and 157a～157g are welded to welding portion 152a～152g respectively, and 154a～154g is on 156a～156g and the 158a～158g.
In above-mentioned surface mount type semiconductor device, have some leading foots not need from function, just in order to improve versatility setting, and in the past all leading foot all to weld.
; in order to test the thermal endurance of (evaluation) this packaging body; thereby the substrate that various samples have been installed is alternately being placed when applying big thermal stress in the big environment of the temperature difference; distinguished that the sample that sample that whole leading foots all weld does not weld than whole leading foots has more sealing-off, and the few more difficult more sealing-off of leading foot number of welding.
Open on the flat 2-5593 communique the spy, propose between a unwanted leading foot and substrate, an insulating trip to be set, and the scheme of under this insulating trip, passing conductive pattern.Yet owing to other leading foot that comprises remaining unwanted leading foot in this semiconductor device all is welded on the substrate, so can not improve durability to above-mentioned thermal stress.
In addition, as Figure 11 and shown in Figure 12, each leading foot begins to stretch to propagation direction from the periphery of semiconductor device, because the expansion of this leading foot has reduced the erection space of the electronic unit of semiconductor device etc.In order to address this problem, guarantee the mounted on surface area of semiconductor device, proposed to observe the scheme (spy opens flat 2-68983 communique) that each leading foot is set in point-symmetric mode from package center point.Even but in this semiconductor device, because all leading foot all welds, so can not improve durability to above-mentioned thermal stress.
The purpose of this invention is to provide and surface mount type semiconductor device welded the packaging body that constitutes, has good thermal fatigue resistance.In addition, further purpose of the present invention provides the semiconductor device that can install with high density more.
To be a kind of semiconductor device that will dispose leading foot on one group of relative limit be installed in packaging body on the installation base plate in the mode of mounted on surface to the packaging body of semiconductor device of the present invention, and it is characterized in that: specific leading foot is welded on the installation base plate in only above-mentioned leading foot being arranged.
In addition, the packaging body of semiconductor device of the present invention is the packaging body of the 1st semiconductor device, it is characterized in that: above-mentioned specific leading foot is meant the leading foot of using as input/output interface in the leading foot that is provided with at least one group of opposite side of above-mentioned semiconductor device.
In addition, the packaging body of semiconductor device of the present invention is the packaging body of above-mentioned the 1st semiconductor device, it is characterized in that: above-mentioned specific leading foot is meant the leading foot of using as input/output interface in the leading foot that is provided with on one group of opposite side, and between leading foot that does not use as input/output interface and substrate insulating trip is set.
In addition, the packaging body of semiconductor device of the present invention is the packaging body of above-mentioned the 1st semiconductor device, it is characterized in that: above-mentioned specific leading foot is the leading foot that uses as input/output interface, remove not the leading foot that uses as input/output interface, be in slidably at semiconductor device between above-mentioned semiconductor device and the installation base plate and under the state holding components be set.
In addition, the packaging body of semiconductor device of the present invention is the packaging body of above-mentioned the 1st semiconductor device, it is characterized in that: above-mentioned specific leading foot is leading foot that is provided with on one side and the leading foot that is provided with at the another side two ends relative with above-mentioned limit.
In addition, the packaging body of semiconductor device of the present invention is the packaging body of above-mentioned the 1st～the 4th semiconductor device, it is characterized in that: above-mentioned specific leading foot only is set on one side.
In addition, the packaging body of semiconductor device of the present invention is that the semiconductor device that has leading foot configuration on one group of relative limit is installed to packaging body on the installation base plate in the mounted on surface mode, it is characterized in that: above-mentioned semiconductor device is removed the leading foot at both ends on one side that the leading foot that is used as input/output interface only is set, both ends at the another side relative with this limit are provided with leading foot, and these leading foots are welded on the installation base plate.
Fig. 1 is that expression will be installed to state diagram on the substrate in the mounted on surface mode according to little gabarit (SOP) the N-type semiconductor N device of embodiment 1.(a) being the vertical view of installation base plate, (b) is the figure of the installation base plate seen by the direction of arrow A.
Fig. 2 is that expression will be installed to the state diagram of substrate 17 according to quad flat (QFP) the N-type semiconductor N device 10 of embodiment 2 in the mounted on surface mode.
Fig. 3 is that expression will be installed to state diagram on the substrate in the mounted on surface mode according to little gabarit encapsulation (SOP) N-type semiconductor N device of embodiment 3.(a) being the vertical view of installment state, (b) is the figure of the substrate seen along the arrow E direction.
Fig. 4 is that expression will be installed to the state diagram of substrate according to quad-flat-pack (QFP) the N-type semiconductor N device of embodiment 4 in the mounted on surface mode.
Fig. 5 is that expression will be installed to the state diagram of substrate according to the semiconductor device 40 of the SOP type of embodiment 5 in the mounted on surface mode.(a) being the vertical view of installment state, (b) is the figure of the installation base plate seen along arrow I direction.
Fig. 6 is that expression will be installed to the state diagram of substrate according to the semiconductor device of the QFP type of embodiment 6 in the mounted on surface mode.(a) being the vertical view of installment state, (b) is a plurality of installment state figure of expression.
Fig. 7 is that expression will be installed to the state diagram of substrate according to the semiconductor device of the SOP type of embodiment 7 in the mounted on surface mode.(a) being the vertical view of installment state, (b) is the figure of the substrate seen from arrow J direction.
Fig. 8 is that expression will be installed to the state diagram of substrate according to the semiconductor device of the QFP type of embodiment 8 in the mounted on surface mode.
Fig. 9 is that expression will be installed to the state diagram of substrate according to the semiconductor device of the SOP type of embodiment 9 in the mounted on surface mode.(a) expression installation base plate vertical view, (b) expression a plurality of semiconductor devices have been installed state diagram.
Figure 10 is that expression will be installed to the state diagram of substrate according to a plurality of semiconductor device of the QFP type of embodiment 10 in the mounted on surface mode.
Figure 11 is the perspective view that expression is installed to general SOP N-type semiconductor N device the state of substrate.
Figure 12 is the perspective view that expression is installed to general QFP N-type semiconductor N device the state of substrate.
At semiconductor device of the present invention and installed in the mounted on surface mode on the packaging body of this semiconductor device, put on input/output interface with the thermal stress on the leading foot in order to alleviate, save useless welding about the leading foot (hereinafter referred to as the NC leading foot) that in the leading foot of semiconductor device, is not connected with chip electrode, so just alleviate the thermal stress that the welding portion of the leading foot that input/output interface is used applies, thereby improved the heat-resistant anti-fatigue characteristic.In addition, by removing the NC leading foot, increased the erection space on the substrate.Below have the semiconductor device of above-mentioned feature and the embodiment 1～10 of installation base plate with accompanying drawing explanation.
(1) embodiment 1
Fig. 1 is that expression will be installed to state diagram on the substrate 5 in the mounted on surface mode according to the SOP semiconductor device 1 of the embodiment of the invention 1.In Fig. 1 (a), left side seven leading foot 2a～2g arranged side by side are the leading foots that input/output interface is used, and are connected (bonding) with each electrode of chip in being sealed in main body.Leading foot 2a～2g is welded to respectively on the welding portion 3a～3g that is provided with on the substrate 5.Right side seven leading foots arranged side by side be not be sealed in packaging body in the leading foot (hereinafter referred to as the NC leading foot) that is connected of chip electrode, all be not welded on the substrate 5.
The semiconductor device 1 that the direction of arrow that Fig. 1 (b) presentation graphs 1 (a) illustrates is seen and the figure of substrate 5.The same being bent of device of the leading foot 2a～2g that extends from semiconductor device main body 1 and surface encapsulation type in the past is so that make main body 1 remain on the level height of being scheduled to from substrate.
Shown in Fig. 1 (a) and Fig. 1 (b), in semiconductor device 1, adopt following formation: only weld leading foot 2a～2g that input/output interface is used, and remaining NC leading foot does not weld.Therefore, even because variations in temperature causes substrate 5 change in size, substrate 5 is also only along direction horizontal slip shown in figure (b) arrow B, thereby reduced the thermal stress that puts on welding portion 3a～3g, can improve the heat-resistant anti-fatigue characteristic that is installed in the semiconductor device 1 on the substrate 5 in the mounted on surface mode.
(2) embodiment 2
Fig. 2 is that expression will be installed to state diagram on the substrate 17 in the mounted on surface mode according to the semiconductor device 10 of quad-flat-pack (QFP) type of embodiment 2.As shown in Figure 2, the semiconductor device 10 of quad-flat-pack (QFP) type all is provided with leading foot on four limits.Leading foot 11a～11g and 13a～13g on the both sides of clamping a bight are the input/output interface leading foots, are welded to welding portion 12a～12g and 14a～14g on the substrate 17 respectively.With the both sides at the diagonal angle of above-mentioned angle on leading foot 15a～15g and 16a～16g be the NC leading foot, these leading foots all do not have welding.
Semiconductor device 10 adopts following formation: leading foot 11a～11g and the 13a～13g welding of having only input/output interface to use, remaining all NC leading foot 15a～15g and 16a～16g do not weld.Therefore similar with the foregoing description 1, even because variations in temperature makes the change in size of substrate 17, but because this substrate 17 slides along arrow C and D direction, so alleviated the thermal stress that is added on welding portion 12a～12g and the 14a～14g, can improve the heat-resistant anti-fatigue characteristic that is installed in the semiconductor device 10 on the substrate 17 in the mounted on surface mode.
Have, can adopt following formation yet: on one group of relative limit the I/O leading foot is set, they are welded on the welding portion that is provided with on the substrate, on one side the NC leading foot is set at all the other, these leading foots do not weld.
(3) embodiment 3
Fig. 3 represents and will be installed to state diagram on the substrate 25 in the mounted on surface mode according to the semiconductor device of little gabarit encapsulation (SOP) type of embodiment 3.In Fig. 3 (a), left side seven leading foots arranged side by side all are the leading foots that input/output interface is used, be sealed in device main body in each electrode of chip be connected.These leading foots 21a～21g is welded to respectively on the welding portion 22a～22g that is provided with on the substrate 25.Right side seven leading foot 23a～23g arranged side by side are the NC leading foots.Between these NC leading foot 23a～23g and substrate 25, insulating trip 24 is set.
Fig. 3 (b) is the figure that sees semiconductor device 20 and substrate 25 from the direction of arrow E shown in Fig. 3 (a).As shown in the figure, from each leading foot 21a～21g that semiconductor device main body 20 is extended, 23a～23g and in the past the same ground of surface installing type device bending.Have, the thickness of insulating trip 24 preferably and being of uniform thickness of welding portion 22a～22g again.
Semiconductor device 20 is taked following structure, that is: only be arranged on input/output interface on one side and be welded on the substrate 25 with leading foot 21a～21g, and all the other all NC leading foot 23a～23g portions do not weld.Therefore, even variations in temperature causes substrate 25 change in size, but because this substrate 25 slides in insulating trip 24 lower edge arrow F directions, so alleviated the thermal stress that is applied on welding portion 22a～22g, can improve the heat-resistant anti-fatigue characteristic that is installed in the semiconductor device on the substrate 25 in the mounted on surface mode.In addition, between NC leading foot 23a～23g and substrate 25, insulating trip 24 is set, can prevents because the NC leading foot contacts the misoperation that produces with substrate 25.
Have again, can utilize the space between insulating trip 24 and the substrate 25 to form wiring figure in the zone below semiconductor device, therefore can improve the degree of freedom of wiring and the integrated level of circuit.
(4) embodiment 4
Fig. 4 represents and will be installed to state diagram on the substrate 39 in the mounted on surface mode according to quad-flat-pack (QFP) the N-type semiconductor N device 10 of embodiment 4.As shown in Figure 4, QFP N-type semiconductor N device 30 all is provided with leading foot on whole four limits.Leading foot 31a～the 31g and the 33a～33g that clamp the both sides in bight are the leading foots that input/output interface is used, and are welded on the welding portion 32a～32g and 34a～34g that is provided with on the substrate 39.And the leading foot 35a～35g and the 37a～37g that clamp the both sides in the bight relative with above-mentioned bight be the NC leading foot, welds, and between these leading foots and substrate 39 insulating trip 36 and 38 is set.
In semiconductor device 30, adopt following formation: only the input/output interface that is provided with will be gone up on one side and be welded on the substrate 39, and remaining all NC leading foot 35a～35g and 37a～37g do not weld with leading foot 31a～31g and 33a～33g.Therefore, identical with the situation of the foregoing description 3, even variations in temperature causes the change in size of substrate 39, but because this substrate slides along arrow G and H direction, so alleviated the thermal stress that applies on welding portion 32a～32g and the 34a～34g, can improve the heat-resistant anti-fatigue characteristic of device.In addition, between NC leading foot 35a～35g and 37a～37g and substrate 39, insulating trip 36 and 38 are set, so can prevent because NC leading foot 35a～35g, 37a～37g contact the misoperation that produces with substrate 39.
Have again, on one group of relative limit, the input/output interface leading foot is set, these leading foots are welded on the substrate 39, on remaining one group of limit the NC leading foot is set, between these NC leading foots and the substrate 39 insulating trip 36 and 38 are set.
Utilization semiconductor device 20 with the insulating trip 36 of lower area and 38 and substrate 39 between the space form wiring figure.Therefore can improve the degree of freedom of wiring and the integrated level of circuit.
(5) embodiment 5
Fig. 5 is that expression will be installed to state diagram on the substrate 45 in the mounted on surface mode according to the semiconductor device 40 of the SOP type of embodiment 5.Fig. 5 (a) is the vertical view of installment state.Left side seven leading foot 41a～41g arranged side by side are the leading foots that input/output interface is used, be sealed in main body in each electrode of chip be connected.Leading foot 41a～41g is welded to respectively on the welding portion 42a～42g that is arranged on the substrate 45.The NC leading foot that the right side of semiconductor device 40 is provided with all removes.For this package main body maintains between the package main body of semiconductor device 40 and the substrate backing materials such as resin are set, so that this package main body is maintained flatly slidably state.
On semiconductor device 40, unwanted NC leading foot is removed fully, moreover utilize backing material 43 that this package main body is maintained flatly slidably state.Therefore, even because of variations in temperature causes the change in size of substrate 45, but package main body slides on backing material 43, thereby alleviates the thermal stress that is applied on welding portion 42a～42g, improve the heat-resistant anti-fatigue characteristic, can prevent that the NC leading foot from contacting the misoperation that produces with substrate 45 simultaneously.
Fig. 5 (b) is the figure that sees semiconductor device 40 and substrate 45 from arrow I direction shown in Fig. 5 (a).The space that produces because of the NC leading foot that removes semiconductor device 40 can be as the space that other semiconductor device 46 leading foots are installed, so can increase the erection space of electronic unit on the substrate as shown in the figure.
(6) embodiment 6
Fig. 6 represents to be installed to the state diagram of substrate 55 according to the QFP N-type semiconductor N device 50 of embodiment 6 in the mounted on surface mode.Shown in Fig. 6 (a), leading foot all is set on four limits of QFP N-type semiconductor N device 50.Leading foot 51a～the 51g and the 53a～53g that clamp the both sides in a bight are the leading foots that input/output interface is used, and are welded to welding portion 52a～52g and the 54a～54g that is arranged on the substrate 55.And the NC leading foot that is provided with face-to-face respectively with leading foot 51a～51g and 53a～53g of clamping the other both sides in the bight relative with above-mentioned bight all removes.In order to make semiconductor device 50 maintain between this device and the substrate 55 flatly slidably state, so resin supporting member 56 is set.
In semiconductor device 50, remove whole unwanted NC leading foots, utilize support component 56 this package main body to be maintained the state that can flatly slide then.Therefore, the same with the foregoing description 5, even cause the change in size of substrate 55 because of variations in temperature, this substrate 55 slides under support component 56, also can alleviate the thermal stress that puts on welding portion 52a～52g and the 54a～54g, improve the heat-resistant anti-fatigue characteristic that is installed in the semiconductor device 50 on the substrate 55, prevent misoperation simultaneously because of NC leading foot and substrate contacts generation.In addition, shown in Fig. 6 (b), the space that forms after the NC leading foot of semiconductor device 50 removes can be as the space of the leading foot that other semiconductor device 57,58 is installed, so can increase the erection space of electronic unit on the substrate.
Have again, also can adopt following structure, that is: on one group of relative limit, the leading foot that input/output interface is used is set, and these leading foots are welded on the substrate, and the NC leading foot that is arranged on all the other one group of limits is all removed, and between semiconductor device and substrate, support component is set.
(7) embodiment 7
Fig. 7 represents the SOP N-type semiconductor N device 60 relevant with embodiment 7 is installed to state diagram on the substrate in the mounted on surface mode.In Fig. 7 (a), left side seven leading foot 61a～61g arranged side by side are the input/output interface leading foots, be sealed in main body in each electrode of chip be connected.Leading foot 61a～61g is welded to respectively on the welding portion 62a～62g that is arranged on the substrate 65.Right side seven leading foot 63a～63g arranged side by side are NC leading foots, and the 63a and the 63g that only are in two ends are welded on welding portion 64a and the 64g.
Fig. 7 (b) is the figure that sees semiconductor device 60 and substrate 63 from the direction of arrow J shown in Fig. 7 (a).As shown in the figure, in NC leading foot 63a～63g, have only leading foot 63a and 63g to be welded on welding portion 64a and the 64b.At other NC leading foot 63b～63f of the state lower support of the thickness that floats welding portion 64a and 64b from substrate 65.
The input/output interface that is provided with on the one side on the semiconductor device 60 is welded on the substrate 65 with leading foot 61a～61g, and simultaneously, the NC leading foot 63a and the 63g that are arranged on the another side two ends are welded on the substrate 65.Therefore, semiconductor device 60 can stably be fixed on the substrate 65.In addition, the thermal stress that produces by will cause substrate 65 change in size because of variations in temperature the time concentrates on welding portion 64a and 64b, therefore can relax the power on the welding portion 62a～62g that puts on input/output interface usefulness leading foot 61a～61g.Can improve the heat-resistant anti-fatigue characteristic that is installed to the semiconductor device on the substrate 65 in the mounted on surface mode thus.
(8) embodiment 8
Fig. 8 represents and will be installed to state diagram on the substrate 79 in the mounted on surface mode according to the semiconductor device 70 of the QFP type of embodiment 8.As shown in Figure 8, four limits of the semiconductor device of QFP type all are provided with leading foot.Leading foot 71a～the 71g and the 73a～73g that clamp the both sides in a bight are the leading foots that input/output interface is used, and are soldered to the welding portion 72a～72g and the 74a～74g that are arranged on the substrate 79.And the leading foot 75a～75g and the 77a～77g that clamp the other both sides in the bight relative with above-mentioned bight be the NC leading foot, and wherein NC leading foot 75a, 75g, 77a, the 77g of the two end portions setting on each limit are welded on welding portion 76a, 76b, 78a, the 78b.State lower support NC leading foot 75b～75f and 77b～77f at the thickness that floats welding portion 76a, 76b, 78a, 78b from substrate 79.
The input/output interface that is provided with on the limit of a side of semiconductor device 70 is welded on the substrate 79 with leading foot 71a～71 g and 73a～73g, and the NC leading foot 75a, 75g, 77a and the 77g that are provided with of the two ends on the limit of opposite side is welded on the substrate 79 simultaneously.Therefore identical with the situation of the foregoing description 7, can stably be fixed on semiconductor device 70 on the substrate 79.In addition, because thermal stress concentrates on welding portion 76a, 76b, 78a and the 78b, so relaxed input/output interface leading foot 71a～71g and the welding portion 72a～72g of 73a～73g and the power on 74a～74g of putting on.Therefore improved the heat-resistant anti-fatigue characteristic that is installed to the semiconductor device 70 on the substrate 79 in the mounted on surface mode.
Have again, also can adopt following formation: on one group of relative limit, the input/output interface leading foot is set, these leading foots are welded on the substrate 79, and the NC leading foot is set on all the other limits of one group, only will be welded on the substrate 79 at the leading foot at the two ends on this group limit.
(9) embodiment 9
Fig. 9 represents to be installed to the state diagram of substrate 85 according to the SOP N-type semiconductor N device 80 of embodiment 9 in the mounted on surface mode.Semiconductor device 80 has adopted the characteristic of the semiconductor device 60 (with reference to Fig. 7) of the semiconductor device 40 (with reference to Fig. 5) of the foregoing description 5 and embodiment 7.
Specifically, input/output interface is welded on welding portion 82b～82f with leading foot 81b～81f, and has only the NC leading foot 83a at one side two ends relative with these leading foots and 83g to be welded on welding portion 84a and the 84b.In addition, remove NC leading foot between 83a and 83g.And then remove leading foot 81a and the 81g relative with NC leading foot 83a and 83g.So, it is such that the leading foot that semiconductor device 80 adopts is arranged, and leading foot is line with the center line by leading foot 81d to be arranged symmetrically, with input/output interface with not having leading foot on the relative one side of leading foot.Because leading foot 83a and 83g are welded on welding portion 84a and the 84b, so can stably be fixed on semiconductor device 80 on the substrate 85.In addition, because thermal stress concentrates on welding portion 84a and the 84b, so relaxed power on the welding portion 82b～82f that puts on leading foot 81b～81f that input/output interface uses.Therefore improved the heat-resistant anti-fatigue characteristic that is installed to the semiconductor device 80 on the substrate 85 in the mounted on surface mode.And then can be as the leading foot space of the semiconductor device that other is installed, so can increase the erection space of electronic unit because remove the space that the NC leading foot stays.Have again, shown in arrow k1 and k2, can consider also to think that leading foot 83a and 83g are suitable with the leading foot 81a and the 81g that use as input/output interface.At this moment the number of the leading foot of using as input/output interface increases by two.
Fig. 9 (b) expression will be installed to the state diagram of substrate 89 with the semiconductor device 86,87,88 of semiconductor device 80 same structures shown in Fig. 9 (a).Shown in Fig. 9 (b), remove the space of the leading foot that space that the NC leading foot of semiconductor device 86 forms can use as the input/output interface of welding semiconductor device 87.Equally, remove the space of the leading foot that space that the NC leading foot of semiconductor device 87 stays can use as the input/output interface of welding semiconductor device 88.
(10) embodiment 10
Figure 10 represents and will be installed to state diagram on the substrate 99 in the mounted on surface mode according to the semiconductor device 90 of the QFP type of embodiment 10.As shown in the drawing, four limit portions of QFP N-type semiconductor N device 90 are provided with leading foot.Semiconductor device 90,97a, 97b and 97c have same structure.Here only be described with regard to semiconductor device 90.Semiconductor device 90 has adopted the characteristic of the semiconductor device 70 (with reference to Fig. 8) of the semiconductor device 50 (with reference to Fig. 6) of the foregoing description 6 and embodiment 8.In other words, the semiconductor device 90 structural features of the foregoing description 9 are applicable to QFP N-type semiconductor N device.
Specifically, clamp leading foot 91b～91f that the input/output interface on the both sides in a bight is used, 92b～92f is welded on the substrate 99, NC leading foot 93a, 93g, 95a and the 95g at the two ends on the limit that welding simultaneously is relative with these leading foots.In addition, remove the NC leading foot (not shown) that is clipped between 93a and the 93g and be clipped in 95a and 95g between NC leading foot (not shown).Like this, leading foot adopts and to be line with the M line in the semiconductor device and to arrange symmetrically, and with input/output interface with not having leading foot on the relative limit of leading foot.Because leading foot 93a, 93g, 95a and 95g are welded on the substrate, so semiconductor device can stably be fixed on the substrate 99.In addition, because thermal stress concentrates on welding portion 94a, 94b, 96a and the 96b, so relaxed input/output interface leading foot 91b～91f, the power on the welding portion of 92b～92f of putting on.Therefore, improved the heat-resistant anti-fatigue characteristic that is encapsulated in substrate 99 semiconductor-on-insulator devices 90,97a, 97b, 97c.And then, shown in figure, can be because remove the space that the NC leading foot stays as the space of the leading foot that semiconductor device 97a and 97b are installed, so can increase the erection space of electronic unit.
In the packaging body of semiconductor device of the present invention, by only welding the specific leading foot in the leading foot of arranging on the semiconductor device, even variations in temperature causes the installation base plate change in size, substrate also can flatly slide under the leading foot of not welding, therefore disperse thermal stress, can alleviate the thermal stress that puts on the leading foot that has welded.Therefore can improve the heat-resistant anti-fatigue characteristic that is installed to the semiconductor device on the installation base plate in the mounted on surface mode.
In addition, in the packaging body of semiconductor device of the present invention, at least in the leading foot that on one group of opposite side, is provided with, by only welding the leading foot of using as input/output interface, even so cause the installation base plate change in size because of variations in temperature, substrate also can flatly slide under the unwanted leading foot of not welding, has therefore disperseed thermal stress, can alleviate to put on the thermal stress of welding on the leading foot.Therefore can improve the heat-resistant anti-fatigue characteristic that is installed to the semiconductor device on the installation base plate in the mounted on surface mode.
In addition, in the packaging body of semiconductor device of the present invention, even because of variations in temperature causes the installation base plate change in size, but owing to substrate can slide on predetermined direction under insulating trip.Therefore the thermal stress that puts on the leading foot that has welded is alleviated.Therefore can improve the heat-resistant anti-fatigue characteristic that is installed to the semiconductor device on the installation base plate in the mounted on surface mode.In addition, because be provided with insulating trip, contact the misoperation that causes with installation base plate so can prevent the unwanted leading foot that does not weld.
In addition, in the packaging body of semiconductor device of the present invention, even because of variations in temperature causes the installation base plate change in size, package main body also can be slided on support component, can prevent that thermal stress from concentrating on the welding portion, can improve the heat-resistant anti-fatigue characteristic, also can prevent misoperation simultaneously because of unwanted leading foot and substrate contacts generation.And then because removed unwanted leading foot, so can increase the shared erection space of unwanted leading foot part.
In addition, in the packaging body of semiconductor device of the present invention, the leading foot at the two ends on the limit of leading foot that is provided with on the limit of a side and the opposite side relative with above-mentioned limit is welded on the substrate, so semiconductor device can stably be fixed on the substrate.In addition, because thermal stress concentrates on the leading foot at two ends, thereby relaxed power on the welding portion that puts on relative limit.Therefore can improve the heat-resistant anti-fatigue characteristic that is installed to the semiconductor device on the substrate in the mounted on surface mode.
In addition, in the packaging body of semiconductor device of the present invention, in the packaging body of above-mentioned the 1st～the 4th semiconductor device, because the specific leading foot that is welded on the substrate only is set on the limit of a side, so when causing the installation base plate change in size because of variations in temperature, substrate under insulating trip or in the strutting piece lower slider, can make thermal stress disperse under the leading foot of not welding.Therefore can improve the heat-resistant anti-fatigue characteristic that is installed to the semiconductor device on the substrate in the mounted on surface mode.
In addition, in the packaging body of semiconductor device of the present invention, on the limit that only is provided as the leading foot that input/output interface uses, remove the leading foot at both ends, and at both ends leading foot is set on relative limit, these leading foots are welded on the installation base plate.Therefore, when variations in temperature causes the installation base plate change in size, thermal stress is concentrated on be arranged on the leading foot at both ends, alleviated the thermal stress that is applied on the leading foot of using as other input/output interface.Therefore can improve the heat-resistant anti-fatigue characteristic that is installed to the semiconductor device on the substrate in the mounted on surface mode.And then owing to removed unwanted leading foot in advance, so can increase the occupied area of this unwanted leading foot.
Claims (7)
1. the packaging body of a semiconductor device, in this packaging body the semiconductor device that has disposed leading foot on one group of relative limit is installed on the installation base plate in the mounted on surface mode, it is characterized in that: in the leading foot of above-mentioned configuration, have only specific leading foot to be welded on the installation base plate.
2. the semiconductor packages body described in the claim 1, it is characterized in that: in the leading foot that above-mentioned specific leading foot is provided with at least one group of opposite side of above-mentioned semiconductor device is the leading foot of using as input/output interface.
3. the semiconductor packages body described in the claim 1, it is characterized in that: in the leading foot that above-mentioned specific leading foot is provided with on one group of opposite side is the leading foot of using as input/output interface, and between leading foot of not using as input/output interface and substrate insulating trip is set.
4. the semiconductor packages body described in the claim 1, it is characterized in that: above-mentioned specific leading foot is the leading foot as the input/output interface use of above-mentioned semiconductor device, remove the leading foot of not using, slidably under the state support component is being set at semiconductor device between above-mentioned semiconductor device and the installation base plate as input/output interface.
5. the packaging body of the semiconductor device described in the claim 1 is characterized in that: while above-mentioned specific leading foot is the leading foot at leading foot that is provided with and relative with above-mentioned limit two ends.
6. the packaging body of the semiconductor device described in the claim 1,2,3 or 4 is characterized in that: above-mentioned specific leading foot only is provided with on one side.
7. the packaging body of a semiconductor device, the semiconductor device that in this packaging body one group of relative limit is provided with leading foot is installed on the installation base plate in the mounted on surface mode, it is characterized in that: on one side of the leading foot that only is provided as the input/output interface use, remove the leading foot of its two end portions, two end portions on one side relative with this limit is provided with leading foot, and these leading foots are welded on the installation base plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97122211A CN1194459A (en) | 1997-03-21 | 1997-11-05 | Packaging body of semiconductor device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP67814/97 | 1997-03-21 | ||
| CN97122211A CN1194459A (en) | 1997-03-21 | 1997-11-05 | Packaging body of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1194459A true CN1194459A (en) | 1998-09-30 |
Family
ID=5176736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97122211A Pending CN1194459A (en) | 1997-03-21 | 1997-11-05 | Packaging body of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1194459A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106257662A (en) * | 2015-06-19 | 2016-12-28 | 爱思开海力士有限公司 | There is the semiconductor packages of slip interconnection structure |
-
1997
- 1997-11-05 CN CN97122211A patent/CN1194459A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106257662A (en) * | 2015-06-19 | 2016-12-28 | 爱思开海力士有限公司 | There is the semiconductor packages of slip interconnection structure |
| CN106257662B (en) * | 2015-06-19 | 2019-10-25 | 爱思开海力士有限公司 | Semiconductor packages with sliding interconnection structure |
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