CN1193596C - Circuit and method for re-arranging element in read-out signals in digital image element sensor - Google Patents
Circuit and method for re-arranging element in read-out signals in digital image element sensor Download PDFInfo
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Abstract
An image sensor includes a sensor array, a data memory for storing pixel data and a pixel normalization circuit. The sensor array has a two-dimensional array of pixel elements and outputs digital signals as pixel data representing an image of a scene. The pixel data outputted by the sensor array are arranged in a sensor-bit arrangement and the pixel normalization circuit rearranges the pixel data into a pixel-bit order. In another embodiment, an image sensor includes a sensor array, a data memory, and a pixel normalization circuit, all fabricated on a single integrated circuit. The pixel normalization circuit includes one or more of a pixel rearrangement circuit, a Gray code to binary conversion circuit, a reset subtract circuit, and a multiple sampling normalization circuit. Finally, a Gray code to binary conversion circuit is provided for high speed conversion.
Description
Technical field
The present invention relates to the digital pixel transducer, particularly relate to a kind of digital pixel transducer with digital pixel data treatment circuit.
Background technology
The present invention is two common pending trial U.S. Patent application No.09/567,638 (agent docket PIXI0002) and No.09/567, the subsequent application of 786 (agent docket PIXI0001), these two applications are entitled as " the integrated digital element sensor with sensing area and digital storage area " and " utilizing the time index method to realize the multiple sampling of wide dynamic range " respectively, they are all submitted to by people such as David Yang on May 9th, 2000, two co-inventors that the people also is described invention wherein.
The application and the U.S. Patent application No.xx/xxx that submits to simultaneously, xxx (agent docket M-9054 US) and No.xx/xxx, xxx (agent docket M-9055 US) is relevant, these two applications are entitled as " the normalized embodiment of the pixel in the digital pixel transducer " and " Gray code is to the circuit and the method for Binary Conversion " respectively, and the invention people is Seye Ewedemi etc.
The present invention relates to image sensor system; Relate in particular to a kind of imageing sensor that utilizes digital pixel sensor body architecture.
The Digital photographic art is one of exciting technology that occurs in recent years.Utilize suitable hardware and software (and some knowledge), anyone can try out the principle of Digital photographic art.For instance, digital camera just is in the forward position of Digital photographic.The appearance of recent product recommendations, technological progress and downward price adjustment and Email and World Wide Web (WWW) has promoted digital camera becomes the most popular novel consumer.
But digital camera is not to work in the mode of traditional film camera.In fact, they more approach computer scanning instrument, photocopier or facsimile machine.Most of digital cameras use imageing sensor or light-sensitive device, come sensing scenery as charge-coupled device (CCD) or CMOS (Complementary Metal Oxide Semiconductor) device (CMOS).The light of light-sensitive device induction scenery reflection also is converted to the electron charge signal to this induction, these electron charge signals and then be digitized.For example, by making light through the red, green and blue filter, can at each independently chromatogram measure this induction.When read output signal is that camera can be determined the concrete color of each part of picture when making up with valuation by software.Because image is actually the set of numeric data, therefore can easily downloads to it in computer and handle to obtain abundanter artistic effect.
But digital camera does not have by the obtainable definition of traditional photography art.Though only be subject to the influence of the granularity of the substrate of making according to chemical method based on the conventional art of film, but it generally has the definition of tens million of pixels, and employed imageing sensor has the definition that is slightly more than one or 2,000,000 pixel in the acceptable most of commercial digital cameras of ordinary consumer.Although there is definition to reach the digital camera of 6,000,000 pixels, the selling at exorbitant prices of these high definition cameras.And the dynamic range of digital image sensor does not usually resemble the wide dynamic range of use based on the traditional photography art of film.This situation especially appears in the cmos image sensor, and usually, cmos image sensor has the dynamic range lower than CCD.
Authorize in people's such as B.Fowler the U.S. Patent No. 5,461,425 and described a kind of analog-to-digital conversion cmos image sensor that has on the Pixel-level.This class imageing sensor that is known as digital pixel transducer (DPS) provides the digital output signal of expression by the light intensity of this pixel element detection with each pixel element.Being combined with of photistor and mould-number (A/D) transducer helps improve the detection accuracy and reduce power consumption, and improves the performance of whole system.And U.S. Patent application No.09/567 has described the integrated DPS transducer of monolithic memory a kind of and at least one frame image data of storage in 638.Sheet carries the bottleneck problem that being used in combination of memory alleviated the transfer of data relevant with the memory chip that uses the storage pixel data.The integrated use that especially promotes multiple sampling of memory and DPS transducer, thus the quality of catching image improved.Multiple sampling is considered to realize wide dynamic range, the technology of not relevant with other dynamic range increase technology many shortcomings again, does not for example have signal to noise ratio to reduce and the shortcoming of the complexity increase of embodiment.U.S. Patent application No.09/567 discloses a kind of service time indexing method in 786 and has been beneficial to the method for image multiple sampling.Above-mentioned patent and patent application integral body are incorporated herein by reference.
In the DPS transducer of ｀ 425 patents, analog-to-digital conversion (ADC) is modulated to the basis with single order ∑-Δ.Although this ADC method only needs very simple and stable circuit, its shortcoming is to produce too many data and the infringement of the low light level performance that can be differed from.U.S. Patent No. 5,801,657 and sequence number be that 09/274,202 U.S. Patent application provides in addition optionally ADC device, it can significantly improve the performance of whole system, reduces the size of A/D converter simultaneously.Above-mentioned patent and patent application integral body are incorporated herein by reference.
Thereby a kind of digital image sensor of needs with the integrated support circuit that improves image sensor performance.
Summary of the invention
According to a scheme of the present invention, a kind of imageing sensor comprises sensor array, data storage and pixel normalization circuit.Sensor array has the pixel element array of two dimension and the digital signal that the pixel data of scene image is represented in the output conduct.The pixel data of sensor array output is arranged with the form of transducer bit arrangement.Data storage is communicated by letter with sensor array and the storage pixel data.Pixel normalization circuit and data storage coupling are the pixel bit-order so that pixel data is reset, and the rearrangement pixel data as output signal is provided.
According to another aspect of the present invention, a kind of imageing sensor comprises sensor array, data storage and pixel normalization circuit, and they all are structured on the integrated circuit.Sensor array has the pixel element array of two dimension and the digital signal that the pixel data of scene image is represented in the output conduct.Data storage is communicated by letter with the storage pixel data with sensor array.The coupling of pixel normalization circuit and data storage is so that pixel data normalization and provide normalized pixel data as output signal.In one embodiment, sensor array is with the form output pixel data of transducer bit arrangement, and the pixel normalization circuit comprises that pixel resets circuit, is used for pixel data reset being the pixel bit arrangement.In another embodiment, pixel data and pixel normalization circuit that sensor array output is represented with Gray code comprise change-over circuit, are used for pixel data is converted to binary representation.In another embodiment, the reset values of each pixel element in the data storage storage sensor array, and the pixel normalization circuit comprises the subtraction circuit that resets, and is used for deducting reset values from the pixel data of each pixel element.In yet another embodiment, sensor array uses multiple sampling setting up the wide dynamic range of sensor array, and data storage comprises the time index memory, is used to store the time index value of each pixel element.In another embodiment, the pixel normalization circuit comprises the multiple sampling normalization circuit, is used for calculating according to pixel data and time index value the normalization pixel data of each pixel element.
A kind of method of n-bit Gray code to binary conversion circuit that be used to make up described according to another aspect of the present invention.A kind of being used for the number conversion of n-bit Gray code is that the method for n-bit binary number comprises that (1) use the XOR tree to calculate the binary value of the minimum effective bit (LSB) of n-bit Gray yardage; XOR tree comprises first group of XOR gate, is used to obtain the value of n-bit Gray yardage and with the binary value of the shortest gate delay Time Calculation LSB; (2) determine in XOR tree, not to be the first bit group of LSB, equally also produce the binary value that is used for this first group of bit for this reason; And (3) provide second group of XOR gate, be used to calculate the binary value of second group of bit of the n-bit Gray yardage that is not first group of bit and LSB, second group of XOR gate is to be less than or to equal the gate delay Time Calculation binary value of hatch time of delay of XOR tree.
In accordance with yet a further aspect of the invention, a kind of being used for the number conversion of n-bit Gray code is that the method for n-bit binary number comprises: (1) is provided for changing a plurality of modular circuits (building block) of 2-bit, 3-bit and 4-bit Gray yardage, and each described modular circuit includes one or more XOR gate and has the hatch time of delay that is used to change 2-bit, 3-bit or 4-bit Gray yardage; (2) select to be used to change the combination of the described modular circuit of described n-bit Gray yardage; (3) output in the described modular circuit of the low step bit of changing described n-bit Gray yardage as required provides first group of XOR gate.Gray code according to the present invention to binary conversion circuit can provide high-speed transitions and save circuit area.
Description of drawings
After having considered the following detailed description and accompanying drawing, will be better understood the present invention.
Fig. 1 is the block diagram of imageing sensor according to an embodiment of the invention.
Fig. 2 shows the stored configuration of the memory in the imageing sensor shown in Figure 1 according to an embodiment of the invention.
The stored configuration of the memory in the imageing sensor shown in Figure 1 when Fig. 3 shows pixel data with the storage of the form of transducer bit arrangement.
Fig. 4 shows the pixel bit arrangement of hope of the imageing sensor of Fig. 1.
Fig. 5 represents to use the n-bit Gray code of simple and direct embodiment of recurrence XOR equation to the circuit diagram of binary conversion circuit.
Fig. 6 represents the pixel intensity value and the time relation of four represent pixels in the pattern matrix of imageing sensor shown in Figure 1.
Fig. 7 is illustrated in an embodiment of the multiple sampling refresh circuit 104 that uses in the imageing sensor shown in Figure 1.
Fig. 8 represents pixel normalization circuit according to an embodiment of the invention.
Fig. 9 represents that 4-bit Gray code is to the circuit diagram of binary conversion circuit according to an embodiment of the invention.
Figure 10 represents to be used for to calculate according to one embodiment of present invention the nested XOR tree of binary value of the minimum effective bit of 15-bit Gray yardage.
It is all bits switch of 15-bit Gray code input value the XOR tree of 15-bit-binary output valve according to one embodiment of present invention that Figure 11 represents to be used for.
Figure 12 represents that a kind of in accordance with another embodiment of the present invention 15-bit Gray code is to binary conversion circuit.
Figure 13 represents that a kind of 15-bit Gray code of another embodiment according to the present invention is to binary conversion circuit.
Figure 14 represents to be used to make up according to an embodiment of the invention n-bit Gray code to some modular circuits of binary conversion circuit.
Figure 15 represents to use modular circuit shown in Figure 14 to make up according to an embodiment of the invention 15-bit Gray code to binary conversion circuit.
In this manual, the analogical object that occurs in a more than accompanying drawing is represented with similar reference number.
Embodiment
According to the present invention, integrated to be used to improve the performance and the efficient of imageing sensor based on the imageing sensor and the pixel normalization circuit of the architecture of digital pixel transducer (DPS).Pixel normalization circuit in imageing sensor of the present invention is carried out one or more pixel normalization functions, comprises the normalization operation to the double sampling operation and the multiple sampling of Binary Conversion, digital correlation of pixel bit rearrangement, Gray code.Fig. 1 shows the block diagram of imageing sensor according to an embodiment of the invention.Imageing sensor 100 can be used for being used to catch static or video camera in the image capture device such as digital camera.The DID that imageing sensor 100 produces as the output signal on the bus 109.
Digital pixel transducer (DPS) array 102 uses the imageing sensor nuclear as imageing sensor 100.DPS array 102 is arrays of the photodetector that is also referred to as photodetector of a two dimension.In Fig. 1, DPS array 102 with N capable * photodetector of M row arranges and has the image definition of N * M pixel.Use for colour, the mosaic electrode of selective filter is aimed at stacked with each photodetector, so that the selection group of first, second and the 3rd photodetector is distinguished three different colour gamuts of sensing, as the red, green and blue colour gamut of visible spectrum.The digital signal that DPS array 102 produces as the transducer read output signal on the output bus 103.
In this explanation, DPS array or sensor array refer to be a kind ofly has an imageing sensor that photodetector array and each photodetector produce a digital output signal.In the present embodiment, the architecture that DPS array 102 is implemented as the digital pixel transducer of describing in the above-mentioned U.S. Patent No. 5,461,425 (｀ 425 patents), its uses the analog-to-digital conversion of Pixel-level.The photodetector of DPS array is known as sensor pixel or sensor element or digital pixel sometimes, these terms are used to represent that each photodetector of DPS array comprises mould-number (A/D) change-over circuit, and can distinguish mutually with the traditional photodetector that comprises light-sensitive element and produce analog signal.The digital output signal of DPS array is better than traditional analog signal part and is that digital signal can read with quite high speed.Certainly, other scheme that is used for implementing the A/D conversion of Pixel-level in area image sensor also can be used on imageing sensor of the present invention.
And in the present embodiment, DPS array 102 utilizes multichannel bit serial (MCBS) analog-to-digital conversion of describing in above-mentioned U.S. Patent No. 5,801,657.The digital signal that DPS array 102 uses k-bit MCBS ADC and output to represent with Gray code.MCBS ADC has many advantages of the image acquisition of can be applicable to, and especially is convenient to read at a high speed.Certainly also can use other ADC technology, as single order ∑-Δ modulation ADC.
In when operation, image is focused on the DPS array 102, makes the different piece that is focused image shine on each sensor pixel in this array.Each sensor pixel comprises an optotransistor, and its conductivity is relevant with the light intensity that shines the optotransistor base stage.The flow through analog current of optotransistor thereby corresponding to the light intensity that shines on the optotransistor.Analog signal from all optotransistors in the array 102 is converted to serial bit stream by the special-purpose A/D converter that is arranged in each sensor pixel simultaneously.The serial bit stream that produces in a frame period provides on bus 103 to shine the digital output signal of the average intensity on the optotransistor as expression.
In imageing sensor 100, offer memory 110 from the transducer read output signal of DPS array 102 through multiple sampling refresh circuit 104 and store.Multiple sampling upgrades logical circuit 104 and is used to carry out multiple sampling to increase the dynamic range of imageing sensor 100, and this will be described in detail following.Under the situation of not using multiple sampling, can be directly coupled to memory 110 from the transducer read output signal of DPS array 102.DPS array 102 provides the transducer read output signal with the form of bit-plane.Fig. 3 shows the stored configuration that directly stores the memory cell 220 in the memory 110 that produces in the memory 110 owing to handle from the transducer read output signal of DPS array 102 into.In DPS array 102, photodetector produces the digital pixel data of a bit simultaneously and the numerical data of a bit is provided as the output signal on the bus 103.Thereby first bit of the digital pixel data of all pixels in the sensor array (being bit 0) is written in the memory 110, forms the bit-plane 220a of pixel bit 0.Photodetector produces the next bit of the k-bit pixel data of each sensor pixel subsequently, and the next bit-plane that comprises the bit 1 of all pixels is written in the memory 110 with the pixel faces 220b as pixel bit 1.The photodetector of DPS array 102 produces the digital pixel data of the k bit of each sensor pixel continuously, and data be written in the memory 110 with as successive bits face 220a shown in Figure 3 to 220p.The memory cell 220 of memory 110 comprises the memory capacity of all bit-planes of storage k digital bit pixel data.
Because DPS array 102 is with the form output pixel data of transducer bit arrangement, so pixel data is stored in the memory 110 with the form of bit-plane.But when the k bit pixel data that are used for a pixel are dispersed in memory 110, the transducer bit arrangement of the pixel data in the memory 110 for the application that links of imageing sensor 100 be useless.In order to guarantee can to receive the image of being caught by imageing sensor 100 with the interface of other image processing equipment compatibility, pixel data need be the pixel bit arrangement, and promptly all bits of a pixel are adjacent one another are.The pixel bit arrangement of the hope of 4-bit pixel in memory 110 is shown in Figure 4.The 4-bit pixel data of preceding four bit storage pixels 0 of memory cell 220 are the 4-bit pixel data of pixel 1 and pixel 2 afterwards, so analogize.Although Fig. 4 remarked pixel 0 is arranged in order to pixel 4, pixel order is unimportant in the pixel bit arrangement.That is to say that neighbor arrangement adjacent one another are is unimportant.For the pixel bit arrangement, all bits of a pixel with continuous bit-order combine be only most important.The order of pixel can be arranged with the desirable any form of application-specific.Thereby, in one embodiment, in the pixel bit arrangement, be all bits of pixel 3 after all bits of pixel 0, be all bits of pixel 2 afterwards again.The pixel data that is stored in the memory 110 can use suitable memory addressing scheme to read.
According to the invention provides a kind of pixel normalization circuit 112, be used for that the pixel data that is stored in memory 110 is carried out pixel and reset operation.Pixel normalization circuit 112 is integrated on the same integrated circuit (IC) chip of imageing sensor 100.Pixel normalization circuit 112 is combined in the speed and the performance that can improve imageing sensor 100 on the imageing sensor 100.In one embodiment, pixel normalization circuit 112 only is used for resetting the configuration of the pixel data of memory 110.The pixel data of resetting is once more in the write memory 110, so that the pixel bit arrangement of the hope of an image of memory 110 storages.In another embodiment, the pixel data of rearrangement only outputs on bus 109 and is coupled in order to the miscellaneous equipment of reception from the view data of imageing sensor 100, and the data in the memory 110 are not upgraded with the form of pixel bit arrangement.In another embodiment of the present invention, except pixel was reset, pixel normalization circuit 112 also comprised the circuit that is used for the pixel data of reading from DPS array 102 is carried out other normalization function.The normalization function can include but not limited to Gray code conversion, CDS subtraction and multiple sampling normalization.In these cases, the normalization pixel data of pixel bit arrangement is stored or output on bus 109 in the write memory 110 once more.
In the present embodiment, the pixel of pixel normalization circuit 112 is reset operation Route Selection or the hardwired realization by carrying out between memory 110 and the pixel normalization circuit 112 fully.Fig. 8 represents pixel normalization circuit 112 according to an embodiment of the invention.In Fig. 8, pixel normalization circuit 112 is carried out pixel and is reset operation and other pixel normalization function.But this only is schematically, and those skilled in the art should be appreciated that the purpose that pixel normalization circuit 112 can be reset just to pixel and makes up.
With reference to figure 8, pixel normalization circuit 112 comprises buffer 830, is used to store the pixel data blocks of carrying out normalized from memory 110.In each processing cycle, the one part of pixel data in the buffer 830 are operated and are known as the conversion window.In Fig. 8, the conversion window is that the 4-pixel is wide, that is to say that it comprises four row of buffer 830.When circuit 112 is finished the processing of the pixel data of conversion in the window, circuit 112 and then be pixel data executable operations in following four row of buffer 830 to next one conversion window.As shown in Figure 8, buffer 830 is divided into three autonomous blocks.This is the operation for the conversion window of indication circuit 112.In the embodiment of reality, buffer 830 can be implemented in any form, and needn't have physical separation between the row of each conversion window.
In the present embodiment, read in pixel normalization circuit 112 each bit-plane from memory 110 first the row pixel data and storage in the buffer 830 of circuit 112.In the present embodiment, suppose that memory 110 and buffer 830 are the 12-bit width and each pixel data has 4 bits.By read the first row pixel data from each bit-plane, buffer 830 is preserved the 4-bit pixel data of each pixel in the vertical row of buffer 830.For example, in first row of buffer 830, the bit 0 of pixel 0 to bit 3 is stored; And in secondary series, the bit 0 of pixel 1 to bit 3 is stored, and so analogizes.In Fig. 8, buffer 830 also comprises the data value that is used for other normalization function, and this will be described in detail following.By the output of buffer 830 is connected with bus 109 or bus 108 so that buffer 830 with row order output pixel data, pixel data can be rearranged and be the pixel bit arrangement.Then output or with the pixel bit-order once more in the write memory 110 on bus 109 of the pixel data of resetting.After all pixel datas in buffer 830 are all processed, resetting operation proceeds, step is in the second row pixel data load buffer 830 that is stored in each bit-plane in the memory 110, and export on bus 109 with the pixel bit-order of hope, or on bus 108 output with in the write memory 110 once more.
The pixel data of resetting by the situation of write memory 110 once more under, data will be written into the address location that can read pixel data from it.For example, in Fig. 8, be read in the buffer 830 from first of each bit-plane capable pixel data.The data of resetting will write first row of each bit-plane once more, but be according to suitable pixel order.Even the pixel bit of pixel data is not arranged in the continuous row of memory 110, they also are to have separated known line number, and according to the addressing scheme of the means modification memory of knowing in memory addressing 110, pixel data can be with continuous calling over.
According to another embodiment of the invention, but from the transducer read output signal of DPS array 102 by using in the improved addressing scheme write memory 110, so that in the continuous row of neighbor bit write memory 110.In the case, when bit-plane was exported on bus 103, the first row bit was written into first in the memory cell 220 row, and was written into previous row from the bit of going subsequently of DPS array 102 and is separated by in the capable row of k.Next bit-plane is written in second row of memory cell 220 and row subsequently also is written in the capable row of the k of being separated by.Under 4-bit pixel situation, the pixel arrangement of the buffer 830 among consequent memory configurations and Fig. 8 is identical.When the pixel bit used in the addressing scheme write memory of revising 110, pixel normalization circuit 112 only read in the continuous row of pixel data in the buffer 830 and carries out pixel normalization operation as required.In this case, the pixel data of rearrangement can be according to the pixel bit-order once more in the write memory 110, and like this, memory 110 is assumed to pixel bit configuration shown in Figure 4.
In the superincumbent description, memory 110 and buffer 830 are the 12-bit width and pixel data has 4 bits.This only is schematically, and pixel normalization circuit of the present invention can be used for the pixel data of k-bit, and memory 110 and buffer 830 also can have other capacity.
In one embodiment, the Route Selection that is used for pixel rearrangement operation is carried out by on bus 107 pixel data of memory 110 being hard wired to pixel normalization circuit 112, so that data are read in the buffer 830 from the row of memory 110 and on bus 108 pixel data in the buffer 830 are being hardwired to memory 110 subsequently, so that from buffer 830, read pixel data with the row order.
For optimum performance and the valid function that realizes imageing sensor 100, the width of the width of DPS array 102 and memory 110 should be selected as the integral multiple of pixel bit number k.The logic that this situation has been simplified between memory 110 and the pixel normalization circuit 112 greatly connects.If the width of DPS array 102 is not the integral multiple of k, then the width of memory 110 has to be chosen as the next integral multiple of k, and it is greater than the width of DPS array 102.Carry out in the same manner as described above although pixel is reset operation, after end pixel is reset operation, also can remain the not row of the memory 110 of usefulness.
According to another aspect of the present invention, pixel normalization circuit 112 comprises the circuit that is used to carry out other pixel data normalization operation shown in Figure 8.Pixel normalization circuit 112 all is integrated in all normalization functions on the same integrated circuit (IC) chip of imageing sensor, has improved the speed and the efficient of imageing sensor thus.In the present embodiment, except pixel was reset, pixel normalization circuit 12 also comprised two resamplings (CDS) operation and the normalized circuit of multiple sampling that is used to carry out Gray code conversion, digital correlation.But the present invention only is schematically, and pixel normalization circuit 112 also can comprise the normalization operation of any one or any amount.
As mentioned above, pixel normalization circuit 112 comprises the buffer 830 that is used to store the pixel data that will handle.Circuit 112 also comprises the memory bank (bank) of Gray code conversion circuit 832, the memory bank of CDS subtraction circuit 834 and the memory bank of multiple sampling normalization circuit 836 (being expressed as the MS normalization circuit).As mentioned above, the normalization of circuit 112 operation is partly carried out the pixel data of the storage in the conversion window in the buffer 830.Pixel data in the conversion window is read from buffer 830.At every turn when the pixel data in the conversion window is processed, data or output on the bus 109 or on bus 108 quilt once more in the write memory 110.Next group pixel data in 112 in circuit and then the treatment conversion window is also carried out normalization in the same manner.Just stop this processing after all pixel datas in being stored in buffer 830 are all processed.In the embodiment shown in fig. 8, the conversion window is 4 bit widths.Although the conversion window can have arbitrary dimension, for operation effectively, the conversion window is the integer quotient of the width of buffer 830 preferably.
In the buffer 830 of Fig. 8, the data in the load buffer 830 not only comprise the pixel data of the one-row pixels in the memory 110, but also comprise CDS subtraction value relevant with pixel data and time index information.At this, the time index information of 2-bit is loaded in the 5th and the 6th row of buffer 830, and the CDS subtraction value of 2-bit is loaded in the 7th and the eighth row of buffer 830.
As mentioned above, the pixel data that is produced by DPS array 102 is represented with Gray code.Using Gray code is the influence that is not subject to noise error because of it.The pixel data that Gray code is represented need be converted to binary representation, so that be used in other image processing operations.The table of typical 4-bit Gray code to Binary Conversion is shown below.
| Gray code | Binary system |
| 0000 | 0000 |
| 0001 | 0001 |
| 0011 | 0010 |
| 0010 | 0011 |
| 0110 | 0100 |
| 0111 | 0101 |
| 0101 | 0110 |
| 0100 | 0111 |
| 1100 | 1000 |
| 1101 | 1001 |
| 1111 | 1010 |
| 1110 | 1011 |
| 1010 | 1100 |
| 1011 | 1101 |
| 1001 | 1110 |
| 1000 | 1111 |
The circuit that is used to carry out Gray code conversion is known, and those skilled in the art should know how to carry out the circuit of n-bit Gray code to Binary Conversion.For example, Gray code to Binary Conversion can be by with the highest significant bit (MSB) and next MSB being beginning and use recurrence xor operation (recursive XOR operation) to carry out to each bit.Proceed the recurrence xor operation by the bit result of before using xor operation and the next bit in Gray's yardage, till reaching minimum effective bit (LSB).The recurrence logical equation that is used to change n-bit Gray code value is as follows:
Binary system MSB=Gray MSB;
Binary system MSB-1=binary system MSB XOR Gray MSB-1;
Binary system MSB-2=binary system MSB-1 XOR Gray MSB-2;
Binary system MSB-(n-2)=binary system MSB-(n-3) XOR Gray MSB-(n-2);
With
Binary system LSB=binary system LSB+1 XOR Gray LSB
Wherein binary system MSB represents the binary bits value of MSB and Gray's code value that Gray MSB represents MSB, and the rest may be inferred.Fig. 5 represents to be used to change the simple and direct embodiment of the above-mentioned recurrence logical equation of 15-bit Gray yardage.In the simple and direct embodiment of this Fig. 5, change-over circuit 500 comprises a series of XOR gate, and wherein the transformation result cascade (cascade) of front is to minimum effective bit.Although change-over circuit 500 is simple and XOR gate number that use is minimum, because its change-over time is according to fluctuating to the XOR result of the last XOR of LSB, so the time of delay of LSB is obviously long than the time of delay of MSB.In change-over circuit 500,14 doors of needs carry out Gray code conversion but the gate delay number of LSB also must be 14 XOR gate.For the n-bits switch, simple and direct embodiment needs n-1 XOR gate and has n-1 XOR gate to postpone.Simple and direct embodiment is not desirable sometimes, this be because time of delay of LSB obviously greater than time of delay of MSB, especially when big bit number.
According to one embodiment of present invention, the pixel normalization circuit 112 of imageing sensor 100 uses circuit shown in Figure 5 to carry out Gray code to binary conversion.For 4-bit pixel data, only need 3 XOR gate and each change-over circuit 832 to implement as the XOR circuit of the bit MSB to MSB-3 in the circuit 500 of Fig. 5.The LSB of change-over circuit 832 has the gate delay of 3 XOR gate.According to another aspect of the present invention, provide a kind of be used to carry out n-bit Gray code to the circuit of Binary Conversion with the high conversion rate operation and reduce the difference of the highest significant bit (MSB) and the conversion delaing time between the minimum effective bit (LSB) of Gray's code value as far as possible.Fig. 9 shows 4-bit Gray code conversion circuit according to an embodiment of the invention.In another embodiment of imageing sensor 100, pixel normalization circuit 112 uses change-over circuit shown in Figure 9 900 to carry out the Gray code conversion of 4-bit pixel data to strengthen the operation of imageing sensor 100.Change-over circuit 900 uses 4 XOR gate but have only gate delay time of two XOR gate for LSB (B0), and gate delay is less than the simple and direct embodiment of Fig. 5.The Gray code of novelty of the present invention of embodiment that detailed description is comprised n-bits switch circuit below with reference to Figure 10-15 is to binary conversion circuit.
As shown in Figure 8, pixel normalization circuit 112 also comprises the memory bank of the CDS subtraction circuit 834 that is used to carry out correlated double sampling (CDS) method.CDS is a kind of the elimination in the sensor array because the method for the inconsistency that fixed pattern noise causes.In this case, CDS is used for the deviant of the variable comparator between the photodetector of correction array.Combine digital CDS method in the present embodiment.After sensor array was reset, the reset values of each photodetector was measured and be stored in the memory cell 226 of memory 110.Subsequently, for each frame pixel data that sensor array is caught, the reset values of being deposited is deducted from pixel value so that pixel data normalization.In pixel normalization circuit 112, CDS subtraction circuit 834 is built as carries out subtraction to pixel data.In Fig. 8, the pixel data (being the pixel data of pixel 0 to 3) in the conversion window at first represents to be converted to binary representation from Gray code.Binary pixel data is provided for CDS subtraction circuit 834 immediately.The reset values that is stored in the buffer 830 also offers CDS subtraction circuit 834.CDS subtraction circuit 834 deducts reset values from the pixel data of each pixel.The subtraction of CDS subtraction circuit 834 can be carried out according to the known method of those skilled in the art.
In the present embodiment, after 834 pairs of binary system pixel datas of CDS subtraction circuit were carried out computing, the normalized pixel data of CDS was provided for multiple sampling normalization circuit 836.As mentioned above, multiple sampling is a kind of algorithm, and it is repeatedly read and make readout normalization be used for increasing the dynamic range of sensor array according to multiple sampling information subsequently by carrying out from sensor array in whole process.Based on the scope of the simulation susceptibility that generation was had of the image of normalized pixel data actual sensitivity range much larger than sensor element.In the present embodiment, imageing sensor 100 is according to U.S. Patent application No.09/567, and the method for describing among 786 (the agent docket PIXI0001) is carried out multiple sampling, and this application is used a kind of time index method when multiple sampling.Certainly, imageing sensor of the present invention also can use other multiple sampling algorithm.
Now the operation of the multiple sampling in the imageing sensor 100 will be described briefly.Detailed multiple sampling operation is found in the above referenced patent application.Fig. 6 represents the pixel intensity value of four represent pixel A, B, C and D in the DPS array 102 and the relation of time for exposure.When using multiple sampling, pixel value is at first read and 104 pairs of pixel values of multiple sampling refresh circuit are carried out saturated compare operation at time for exposure 1T.Saturated compare operation can utilize the whole bag of tricks to carry out.In one embodiment, 50% saturation threshold is used.Therefore, at time 1T, multiple sampling refresh circuit 104 has relatively surpassed this 50% saturation threshold from pixel value and definite which pixel intensity value that DPS array 102 is read.For example, in Fig. 6, pixel A has the intensity level that surpasses 50% pixel saturation threshold, and pixel B has the intensity level that is lower than this saturation threshold to D.Multiple sampling refresh circuit 104 pixel A to the pixel value write memory 110 of D.The multiple sampling refresh circuit 104 also threshold value indication bit corresponding to pixel A in the memory cell 222 is set to a predetermined value, and as " 1 ", A reaches capacity with remarked pixel.By the threshold value indication bit of pixel A is set, multiple sampling refresh circuit 104 will prevent to upgrade once more the pixel value of the pixel A that enters memory 110.Multiple sampling refresh circuit 104 also stores the time index 1T of pixel A in the memory cell 224 into.Pixel normalization circuit 112 will use the time index value of pixel A and the analog intensity value that pixel value is derived pixel A.In Fig. 6, the transducer that the multiple sampling processing and utilizing obtains after time for exposure 2T, 4T, 8T and 16T read out continuation.At every turn when the pixel intensity value of a pixel during above 50% saturation threshold, then the threshold value indication bit is set up and the saturation time index of this pixel is stored in the memory 110 with the pixel value of measurement.Fig. 7 shows an embodiment of the multiple sampling refresh circuit 104 that uses in imageing sensor 100.Those skilled in the art should be known in that other embodiment also is fine.
In another embodiment, the saturation threshold level is chosen as the value near the saturation level of photodetector.For example can use 90% saturation threshold.When using 90% saturation threshold, multiple sampling refresh circuit 104 will write and upgrade pixel value in memory 110, till a pixel value surpasses 90% saturation threshold.In memory 110, memory cell 222 is stored in the saturated bit of each pixel in the sensor array 102.No matter when the pixel value of pixel surpasses 90% threshold value, and this saturated bit all is set to a predetermined value, as " 1 ".In the case, the saturated pixel value will be not in the write memory 110.On the contrary, multiple sampling refresh circuit 104 will detect when saturated index memory time.For example, suppose that the pixel saturation level among Fig. 6 is in 90% level, then at time 1T, the saturated and predetermined pixel value of pixel A is with in the write memory 110, and the time index 1T of pixel A will be stored and the saturated bit of pixel A also will be set to " 1 ".On the other hand, pixel B just becomes saturated up to time 4T.At time 4T, multiple sampling refresh circuit 104 will not rewritten the pixel value of the pixel B of having stored, but upgrade the time index and the saturated bit of pixel B.Pixel B will be used for determining the analog pixel value of pixel B by pixel normalization circuit 112 at pixel value and the saturated time index of generation before saturated.In another embodiment of multiple sampling refresh circuit, what saturated bit can be used as memory 110 writes mask (mask).Therefore, saturated bit uses as the enable signal of writing of each pixel, and whether definite pixel data is in the write memory 110.
After the number of times that sampling is wished, imageing sensor 100 has been caught the light intensity value of all pixels in the image.Memory 110 is stored in the pixel value that photodetector becomes saturated each pixel before.Memory 110 is also stored the time index value corresponding to each pixel of saturated time of pixel change.Pixel normalization circuit 112 is according to the normalization operation of pixel data being carried out multiple sampling at the time index value and the pixel value of each pixel storage.Multiple sampling normalization hypothesis pixel value in whole process is linear to the response of light.Linear response is approximate to be the good approximation of cmos sensor.Multiple sampling normalization realizes by pixel value and constant corresponding to total exposure time and the ratio of pixel saturation time are multiplied each other.
With reference to figure 6, the normalization pixel value of pixel A equals pixel value that time interval of after pixel A is saturated (being time 1T) reads and multiply by total exposure time (16T) and the saturation time ratio of (1T) at interval from pel array.Therefore, following formula has provided the normalized value of pixel A:
Pixel A (normalization)=pixel A (reading) * (total exposure time/saturated time for exposure)
=pixel A (reading) * (16/1)=pixel A (reading) * 16
Similarly, pixel B is as follows to the normalized value of D:
Pixel B (normalization)=pixel B (reading) * (16/4)=pixel B (reading) * 4
Pixel C (normalization)=pixel C (reading) * (16/8)=pixel C (reading) * 2; With
Pixel D (normalization)=pixel D (reading) * (16/16)=pixel D (reading).
The normalization computing of above-mentioned formulate when selecting 50% saturation threshold.Certainly, same normalization computing also can be used for 90% saturation threshold.In pixel normalization circuit 112, multiple sampling normalization circuit 836 is carried out above-mentioned multiple sampling normalization computing so that the output of the pixel data with wide dynamic range to be provided.Circuit 836 use in the buffer 830 that is stored in pixel normalization circuit 112, carry out normalization such as the time index value in the 5th and the 6th row of buffer 830 and calculate.836 pairs of pixel datas of multiple sampling normalization circuit and time index value are carried out computing to calculate normalized pixel data.
A kind of circuit of n-bit Gray code to Binary Conversion that be used to carry out is provided according to another aspect of the present invention.Gray code conversion circuit of the present invention has significantly reduced the gate delay time of the low step bit that is used to change n-bit Gray code value.In one embodiment, compare with 14 XOR gate delays in the simple and direct embodiment, 15-bit Gray code conversion circuit according to the present invention only has 4 XOR gate to postpone.Imageing sensor 100 of the present invention combines with Gray code conversion circuit of the present invention to improve the speed of service of imageing sensor 100.
Gray code can use above-mentioned recurrence XOR equation to carry out to Binary Conversion.Gray code of the present invention uses nested XOR tree architecture to reduce the time of delay of LSB as far as possible to binary conversion circuit, to replace the simple and direct embodiment of the recurrence XOR formula of understanding the long delay time that produces LSB.Be the critical path of change-over circuit the time of delay of the LSB of n-bit Gray yardage, and this is because it is the maximum delay of entire n-bit Gray code conversion circuit.A method according to the present present invention provides the Gray code that is used to produce n-bit Gray yardage to binary conversion circuit, and makes minimum time of delay of critical path.And method of the present invention also allows circuit size or the XOR gate number in the circuit the least possible, keeps the short delaing time in the critical path simultaneously.
Change-over circuit and being used to makes up the method for this circuit and will describe according to 15-bit Gray yardage.Certainly, circuit of the present invention and method also are applicable to any n-bit Gray yardage.At first make up nested XOR tree, so that with the LSB B0 of 15-bit Gray code number conversion binary value.The purpose that the XOR tree makes up is in order to reduce the time of delay of critical path as far as possible.Figure 10 illustrates the nested XOR tree 1010 of 15-bit Gray yardage.Using 2-input XOR gate conversion n-bit Gray code to the minimum gate delay number of the binary system LSB of binary conversion circuit is log2n.For 15-bit Gray yardage, the gate delay number is shown in Figure 10 4.For the bit G0 by conversion 15-bit Gray yardage obtains binary system LSB B0 to G14, the XOR tree 1010 of Figure 10 comprises four layers of XOR gate.In ground floor, seven 2-input XOR gate are carried out xor operation to G14 to G1 to the bit of 15-bit Gray code input value.At the second layer, four 2-import xor operation result and the LSB bit G0 execution xor operation of XOR gate to ground floor.If n is an even number, then ground floor to whole n-bit executable operations of input value and the second layer to the xor operation of ground floor executable operations as a result.Conversion process utilizes four xor operation results of the second layer to proceed at the 3rd layer.Finally, the binary value B0 of LSB passes through the 4th layer XOR gate generation.Utilize this method, XOR tree 1010 is fabricated the LSB that is used for changing 15-bit Gray code input value under the situation that critical path has only 4 XOR gate to postpone.
Although can produce the XOR tree at each binary system output bit, this embodiment is unrealistic, because if each bit has the XOR tree of himself, then the conversion of each bit will be shared logical term and logical circuit result's repetition.On the contrary, next step of the change-over circuit of structure 15-bit Gray code input value relates to the binary value that the XOR tree 1010 that discerns Figure 10 comprises the conversion of the output bit that is not LSB (bit B0).With reference to Figure 10, XOR tree 1010 also produces the binary value of bit B14, B13, B11 and B8.Thereby remaining work is exactly to finish change-over circuit by dosing the XOR gate that is used to change remaining bits.
Then, XOR gate is added in the XOR tree 1010 to be used for the also non-switched bit of conversion.In Figure 10, remaining not switch bit is that B12, B10, B9 and B7 are to B1.Major limitation at this is that the interpolation of changing the XOR gate of remaining bits does not produce the more gate delay than LSB.That is to say that all remaining bits all will be changed with 4 gate delays of 15-bit Gray code value or the maximum delay of log2n.Its objective is and be used in the logical term that has produced in the XOR tree 1010 as much as possible again.The XOR tree 1110 of the binary system output valve that it is the 15-bit that Figure 11 represents to be used for whole 15 bits switch of Gray code input value.XOR tree 1110 comprises the XOR tree 1010 of Figure 10 and is used to change the additional XOR gate of remaining bits.In XOR tree 1110, always have 28 XOR gate and be used and keep the 4-XOR gate delay.
In some applications, wish the zone reduce to carry out Gray code conversion circuit of the present invention as far as possible.In this case, change-over circuit of the present invention can be optimized at Minimum Area and critical path delay time.Optimization is to carry out by XOR circuit of resetting one or more bits rather than LSB, so then can use less XOR gate to produce the binary value of bit.This is by using shared to realize when producing binary bits to greatest extent.Even the rearrangement of XOR gate causes the gate delay of specific bit to increase, also can keep total delay time, i.e. the time of delay of critical path.Figure 12 shows the embodiment of 15-bit Gray code to binary conversion circuit, and wherein the change-over circuit of bit B8 has been rearranged so that reduce circuit size as far as possible.In Figure 11, circuit 1110 uses 28 doors and has the 4-XOR gate delay.Circuit 1110 postpones to calculate bit B8 with 3 XOR gate.Specifically, bit G10 and G9 carry out xor operation.This result carries out xor operation with bit G8.This result carries out xor operation once more with the result who bit G14, G13, G12 and G11 is carried out xor operation.But circuit 1110 can be optimized circuit size by removing at least one XOR gate.With reference to the circuit 1210 of Figure 12, binary system output bit B8 uses the output of XOR gate 1214 to produce.The XOR gate 1113 of Figure 11 is removed.Therefore, only use 27 doors to implement circuit 1210, lack a door, keep the 4-XOR gate delay in the critical path simultaneously than the circuit 1110 of Figure 11.Although B8 has the 4-XOR gate delay at present with respect to the 3-XOR gate delay of previous circuit, the time of delay of its critical path is identical, and therefore, the performance of whole change-over circuit is unaffected.Utilize this method can optimize circuit size and the critical path delay time of n-bit Gray code of the present invention to binary conversion circuit.
In some cases, even the gate delay of critical path needs to increase, also must reduce the circuit size of Gray code conversion circuit of the present invention as far as possible.Figure 13 represents that 15-bit Gray code is to binary conversion circuit in accordance with another embodiment of the present invention.Change-over circuit 1310 has the 5-XOR gate delay when producing LSB (bit MSB-14), but only uses 23 XOR gate altogether.Circuit 1310 reduces four to the XOR gate number when only increased an XOR gate time of delay of critical path.Change-over circuit 1310 is suitable for when wishing the minimum circuit size and can sacrifice some time of delays.
In a word, in said method of the present invention, set and implement n-bit Gray code to binary conversion circuit by making up nested XOR.The XOR tree at first makes up by optimization the time of delay as the critical path of the conversion of minimum effective bit (LSB).For the bit on critical path not, the XOR tree makes up by reducing circuit size as far as possible.Therefore, XOR tree is by making up with the nearest logical term of implementing at LSB or other bit again.By depending on executed as much as possible and fluctuation (ripple) logic and within the gate delay of critical path, the circuit size of minimum can be achieved.Certainly, n-bit Gray code of the present invention to the difference of binary conversion circuit change can be by optimizing critical path time of delay or circuit size one or both of implement.
The another kind of method of n-bit Gray code to binary conversion circuit that be used to make up is provided according to another aspect of the present invention.This n-bit Gray code is implemented by selection and combination plurality of modules circuit to binary conversion circuit.Although several combinations of modular circuit are fine for identical n-bits switch circuit, these combinations have different total XOR gate numbers and postpone number with different XOR gate.According to the present invention, the minimum gate that a kind of Gray code conversion circuit can be fabricated in order to the critical path of minimum circuit size that obtains to wish and hope postpones.Figure 14 represents to can be used for making up according to an embodiment of the invention n-bit Gray code to the plurality of modules circuit of binary conversion circuit.Figure 14 illustrates six disparate modules circuit that are used to change 2-bit, 3-bit, 4-bit and 8-bit Gray yardage.Circuit C2 is a 2-bits switch circuit.Circuit C3 is a 3-bits switch circuit, has the 2-XOR gate delay.Circuit C41 and C42 are 4-bits switch circuit, and wherein circuit C41 is optimized at gate delay, and circuit C42 is optimized at circuit size.When needs 4-bits switch circuit, according to being that short delaing time of needs or needs minimum circuit size can be used modular circuit C41 or modular circuit C42.
The modular circuit of Figure 14 also comprises two 8-bits switch circuit.Circuit C81 and C82 are illustrated in the modular circuit before how advantageously using when making up the more complicated change-over circuit with big bit number.For example, two example circuit C41 of circuit C81 use are used for 8-bit Gray code conversion.In circuit C81, the 4th the highest significant bit is used to fluctuation to minimum effective output bit.Circuit C81 uses 12 XOR gate and has the 3-XOR gate delay.And circuit C82 only uses the example of circuit C41.The logical circuit that is used to produce four minimum effective bits in circuit C82 is optimized at circuit size rather than time of delay.Therefore, circuit C82 uses 11 XOR gate but the 4-XOR gate delay is arranged.In circuit C82, critical path is actually the bit 1 of adjacent minimum effective bit.In fact the LSB of circuit C82 has only a 3-XOR gate delay.
By some modular circuits are provided, n-bit Gray code to binary conversion circuit can be by selecting and make up the modular circuit of right quantity and making up with the calculating of finishing low step bit in the logic of increase fluctuation subsequently.For example shown in Figure 15, the change-over circuit 1210 of Figure 12 can use modular circuit C82, C41 and C3 to make up.Change-over circuit 1510 and circuit 1210 are identical and have 27 XOR gate and a 4-XOR gate delay.The embodiment of 27 XOR gate is minimum embodiments of 15-bit Gray code conversion circuit.The change-over circuit of any n-bit number can make up in a comparable manner.
In the present embodiment, use 2-input XOR gate to make up modular circuit.Certainly, other modular circuit also can use 3 or 4-input XOR gate make up.Modular circuit shown in Figure 1 only is schematic.
In a word, in one embodiment of the invention, as follows in conjunction with the operation of the imageing sensor 100 of pixel normalization circuit 112.At first, imageing sensor 100 is carried out the CDS initialization with the DPS array 102 that resets.After sensor array resetted, reset values was read out and is stored in the memory cell 226 of memory 110 (Fig. 2).DPS array 102 is with post-exposure, to catch image.At first exposure time interval (time 1T) afterwards, whether multiple sampling refresh circuit 104 is carried out the saturation level comparisons and is become saturated and as required pixel value, time index and threshold value indication bit are stored in the memory 110 according to pixel value.Multiple sampling is handled and is continued on the whole time for exposure.Pixel value and storage threshold indicated value (memory cell 222), time index value (memory cell 224) and the reset values (memory cell 226) of all pixels that the mode that memory 110 storages are arranged with bit-plane is arranged.112 of pixel normalization circuits pass through at first carrying out the normalization operation from (Fig. 8) in the first row pixel data load buffer 830 of each bit-plane.Relevant with pixel subtraction value and the time index information of resetting also is loaded in the buffer 830.Pixel data in the conversion window partly offers Gray code conversion circuit 832 to be used for that data are represented to be converted to binary representation from Gray code.The binary system pixel data is coupled to CDS subtraction circuit 834 immediately, and in circuit 834, reset values is deducted from the binary system pixel data.The normalized data of CDS offer multiple sampling normalization circuit 836 subsequently, and in circuit 836, pixel data index information service time carries out normalization.Final normalization data or with the form of pixel bit arrangement output on the bus 109 or also with the form of pixel bit arrangement in bus 108 write memory again 110.112 of pixel normalization circuits continue next the group pixel data in the treatment conversion window.This normalized all pixel datas in buffer 830 are all just finished after the normalization.Subsequently, pixel normalization circuit 112 is in the next line pixel data load memory 110 from each bit-plane, and as mentioned above, normalized repeats, and all is normalized to up to all pixel datas and ends.
According to principle of the present invention, imageing sensor is integrated in sensor array, memory and pixel normalization circuit on the integrated circuit.The embodiment of single-chip has improved the efficient of imageing sensor and imageing sensor is easy to and the external system compatibility.Imageing sensor of the present invention can be coupled with any imaging system, just can receive the image of catching thereby needn't participate in the processing of circuit pixel data.These abilities according to imageing sensor of the present invention can't realize by traditional imageing sensor.
The detailed description that provides above is in order to show specific embodiment of the present invention and should be as restriction of the present invention.Various improvement within the scope of the invention and variation also are possible.The present invention is defined by appended claim.
Claims (15)
1. imageing sensor is characterized in that described imageing sensor comprises:
Sensor array comprises two-dimentional pixel element array, and its output is as the digital signal of the pixel data of expression scene image, and described pixel data is arranged in the mode of transducer bit arrangement;
Data storage is communicated by letter with described sensor array, is used to store described pixel data; With
The pixel normalization circuit with the coupling of described data storage, is used for described pixel data rearrangement for the pixel bit-order and described rearrangement pixel data as output signal is provided.
2. according to the imageing sensor of claim 1, wherein said sensor array, described data storage and described pixel normalization circuit are structured on the integrated circuit.
3. according to the imageing sensor of claim 1, wherein said pixel normalization circuit is reset described pixel data by the Route Selection of the holding wire between described data storage and the described pixel normalization circuit.
4. according to the imageing sensor of claim 3, wherein said Route Selection is a hardwired.
5. according to the imageing sensor of claim 1, the pixel data of wherein said rearrangement is written in the described data storage.
6. according to the imageing sensor of claim 1, the pixel data that wherein said pixel data has k-bit and described rearrangement has first pixel of the k bit of consecutive order, is second pixel of k bit afterwards.
7. according to the imageing sensor of claim 1, wherein said pixel normalization circuit comprises the buffer that is used to store from the described pixel data of a part of described data storage, and described pixel normalization circuit is reset described pixel data by the Route Selection of the holding wire between described data storage and the described buffer.
8. according to the imageing sensor of claim 1, wherein said sensor array is that array and each described pixel element of N * M pixel has the k-bit.
9. imageing sensor according to Claim 8, wherein said data storage have first bit that N * M * k bit and described data storage are stored each described pixel element continuously, are second bit of each described pixel element afterwards.
10. according to the imageing sensor of claim 9, the pixel data of wherein said rearrangement has the k bit of first pixel element of successive bits order, is the k bit of second pixel element afterwards.
11. according to the imageing sensor of claim 10, wherein said first pixel element and described second pixel element are not adjacent pixel elements in described sensor array.
12. a method that is used for imageing sensor comprises:
Use sensor array to catch the image of scenery;
Pixel data with transducer-described image of bit-order output expression;
Described pixel data is stored in the data storage; And
It is pixel-bit-order that described pixel data is reset.
13. the method according to claim 12 also comprises:
The pixel data of the described rearrangement of storage in described data storage.
14. the method according to claim 12 also comprises:
Provide described rearrangement pixel data from described imageing sensor as output signal.
15., wherein reset the described operation of described pixel data and carry out by the Route Selection of holding wire according to the method for claim 12.
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| US09/638,503 US6831684B1 (en) | 2000-05-09 | 2000-08-15 | Circuit and method for pixel rearrangement in a digital pixel sensor readout |
| US09/638,503 | 2000-08-15 |
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| JP (1) | JP2002165137A (en) |
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| US6452152B1 (en) * | 2000-02-22 | 2002-09-17 | Pixim, Inc. | Sense amplifier having a precision analog reference level for use with image sensors |
| TW522723B (en) * | 2000-08-15 | 2003-03-01 | Pixim Inc | Circuit and method for pixel rearrangement in a digital pixel sensor readout |
| JP4574045B2 (en) * | 2001-03-30 | 2010-11-04 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit and imaging system |
| JP4236152B2 (en) | 2002-07-29 | 2009-03-11 | 富士フイルム株式会社 | Solid-state image sensor |
| US20080212883A1 (en) * | 2005-08-17 | 2008-09-04 | Pixoneer Geomatics, Inc. | Processing Method of Data Structure for Real-Time Image Processing |
| JP4998056B2 (en) * | 2006-05-11 | 2012-08-15 | セイコーエプソン株式会社 | Imaging apparatus, imaging system, and imaging method |
| US8144215B2 (en) * | 2009-05-11 | 2012-03-27 | Himax Imaging, Inc. | Method and apparatus of using processor with analog-to-digital converter within image sensor to achieve high dynamic range of image sensor |
| US8320403B2 (en) * | 2010-06-29 | 2012-11-27 | Excelitas Canada, Inc. | Multiplexed sensor array |
| US9838628B2 (en) * | 2016-03-16 | 2017-12-05 | Sony Corporation | Detecting quantities beyond sensor saturation |
| CN109951657B (en) * | 2019-04-22 | 2021-04-23 | Oppo广东移动通信有限公司 | Pixel circuit and image sensor |
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| JP2845491B2 (en) * | 1989-05-25 | 1999-01-13 | 日本電気株式会社 | Graph data plane pack conversion circuit |
| JPH06303529A (en) * | 1993-04-16 | 1994-10-28 | Fuji Xerox Co Ltd | Picture processor |
| US5461425A (en) * | 1994-02-15 | 1995-10-24 | Stanford University | CMOS image sensor with pixel level A/D conversion |
| JPH08123949A (en) * | 1994-10-20 | 1996-05-17 | Fuji Photo Film Co Ltd | Method and device for filing picture, method and device for reproducing picture |
| EP0833502A3 (en) * | 1996-09-26 | 2000-01-05 | Eastman Kodak Company | Compact image capture device with local image storage |
| JPH10285467A (en) * | 1997-04-02 | 1998-10-23 | Nikon Corp | Image-pickup device |
| JP3457551B2 (en) * | 1998-11-09 | 2003-10-20 | 株式会社東芝 | Solid-state imaging device |
| US6975355B1 (en) * | 2000-02-22 | 2005-12-13 | Pixim, Inc. | Multiple sampling via a time-indexed method to achieve wide dynamic ranges |
| US6452152B1 (en) * | 2000-02-22 | 2002-09-17 | Pixim, Inc. | Sense amplifier having a precision analog reference level for use with image sensors |
| US6985181B2 (en) * | 2000-05-09 | 2006-01-10 | Pixim, Inc. | CMOS sensor array with a memory interface |
| TW522723B (en) * | 2000-08-15 | 2003-03-01 | Pixim Inc | Circuit and method for pixel rearrangement in a digital pixel sensor readout |
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| EP1182865A2 (en) | 2002-02-27 |
| CN1338864A (en) | 2002-03-06 |
| KR20020013818A (en) | 2002-02-21 |
| EP1182865A3 (en) | 2004-08-11 |
| JP2002165137A (en) | 2002-06-07 |
| TW522723B (en) | 2003-03-01 |
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