JP2002094886A - High speed picture processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high speed picture processor capable of quickly processing a basic picture arithmetic operation in a simple circuit constitution. SOLUTION: A parallel processing mechanism 14 constituted of plural arithmetic elements 400 arrayed in a plural lines and columns is provided with a data bus 17 for transferring data to an arithmetic element 400. The data bus 17 is provided with plural column directional data transferring data lines 170 corresponding to the respective columns and plural line directional data transferring data lines 180 corresponding to the respective lines. The respective directional rata transferring data lines 170 are connected to the corresponding one line directional data transferring data line 180, and the column directional data transferring data line and the line directional data transferring data line are used for the data transfer as the common data line. Also, a light receiving element array 11 as a picture reading part and an A/D converter array 13 are connected to the parallel processing mechanism 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed image processing apparatus, and more particularly to a high-speed image processing apparatus widely used for high-speed image processing for controlling a FA robot.

[0002]

2. Description of the Related Art In order to operate a robot at high speed in an FA system or the like, high-speed image processing is required. For example, in the case of a robot that forms a feedback loop between an image processing apparatus and an actuator, the actuator can be controlled in milliseconds, and therefore, an image processing speed corresponding to this is originally required. However, in the current vision system, since the image processing speed is limited to the video frame rate, only a low-speed operation corresponding to the image processing speed can be performed, and the performance of the robot cannot be fully utilized. On the other hand, some high-speed CCD cameras can capture an image in about 1 millisecond, but these are mechanisms that temporarily store the captured image in memory and read it out later for processing. Although it can be used for applications such as analysis, it has little real-time performance and could not be used for applications such as robot control.

In order to solve such a problem, research on a vision chip which integrally handles an image capturing unit and a processing unit is progressing. ("An Object Position and Orientation IC with Embe
dded Imager ”, David L. Standley (“ Solid StateCir
cuits ”, Vol. 26, No. 12, Dec. 1991, pp. 1853-185
9, IEEE), “Computing Motion Using Analog and Bina
ry Resistive Networks ”, James Hutchinson, et al.
(“Computer”, Vol. 21, March 1988, pp.52-64, IE
EE) and “Artificial retinas -fast, versatile i
mage processors ”, Kazuo Kyuma et al., (“ Natur
e ”, Vol. 372, 10 November 1994) However, these mainly use analog fixed circuits that are easy to integrate, and require post-processing of the output signal, or the content of image processing is limited to specific applications. There were problems such as being limited and lacking versatility.

As a vision chip capable of performing general-purpose image processing on these, Japanese Patent Laid-Open No. 10-14 / 1998
Techniques disclosed in 5680 and International Publication WO00 / 21284 are known. According to this technique, an arithmetic element is provided in one-to-one correspondence with a light receiving element, and an A / D converter is provided for each row of the light receiving element. There is an advantage that the number of transmission lines between elements can be reduced, and the degree of integration of both can be optimized.

[0005]

However, when calculating the center of gravity (first moment) of an image, which is information required in many image processes, the position information of the pixel (position in the x direction, y position) (The position in the direction) and the pixel data, the position information of each pixel needs to be stored in the memory of each arithmetic element in advance. JP-A-10-145680 and International Publication W
In the technique of O00 / 21284, first, position information must be sequentially transferred from the control circuit to each arithmetic element, and the position data and image data from the light receiving element must be calculated and output. It takes time to transfer data. It has been desired to speed up such basic image calculation processing.

Accordingly, an object of the present invention is to provide a high-speed image processing apparatus capable of processing basic image operations at a high speed with a simple circuit configuration in view of the above problems.

[0007]

In order to achieve the above-mentioned object, the present invention provides a multi-element system in which a plurality of processing elements are two-dimensionally arranged in a plurality of rows and columns, and each processing element performs a predetermined operation on a digital image signal. And a plurality of column direction data transfer data lines are provided in one-to-one correspondence with the respective columns of the parallel processing mechanism, and a plurality of row direction data transfer data lines are provided. Are provided in one-to-one correspondence with each row of the parallel processing mechanism, and each column-directional data transfer data line connects a plurality of arithmetic elements existing in a corresponding column, and is connected to each arithmetic element in the corresponding column. The data line for each row-direction data transfer connects a plurality of arithmetic elements present in the corresponding row, and performs data transfer with each arithmetic element in the corresponding row. line It provides high-speed image processing apparatus characterized by comprising corresponding a bus for data transfer, which is connected to one row-direction data transfer data line being.

According to the high-speed image processing apparatus of the present invention, a plurality of processing elements of the parallel processing element array can perform parallel processing of digital image signals at high speed. Moreover, by using the data transfer bus, arithmetic processing requiring data transfer from the outside can be performed at high speed, and each arithmetic element can be individually accessed from the outside.

For example, the position information of each column is externally transferred to the arithmetic element of the corresponding column via the corresponding data line for column direction data transfer, and the position information of each row is transferred to the corresponding row direction data transfer. When the data is transferred to the arithmetic elements in the corresponding row via the data line, each arithmetic element can perform the center of gravity calculation on the digital image signal based on the position information of the corresponding row and column to which the data has been transferred. . As described above, according to the present invention, since the dedicated data transfer bus is arranged in the row direction and the column direction, the position information required for the center of gravity calculation which is the basic operation of the image processing can be reduced by a small data transfer system. Can be transferred efficiently.

In addition, when address data for a predetermined operation control is externally transferred via a predetermined data line for column-direction data transfer, a predetermined operation on a digital image signal can be performed for all operation elements belonging to a predetermined column. Can be performed. Similarly, when address data for predetermined arithmetic control is externally transferred via a predetermined data line for row-direction data transfer, a predetermined arithmetic operation on a digital image signal is performed for all arithmetic elements belonging to a predetermined row. Can be made. Furthermore, if address data for a predetermined operation control is externally transferred via both a predetermined data line for column-direction data transfer and a predetermined data line for row-direction data transfer, the predetermined data belonging to the corresponding row and column can be obtained. Of the digital image signal. Therefore, it is also possible to cause each arithmetic element to execute different arithmetic processing.

Further, if address data for a predetermined operation control is externally transferred via a predetermined data line for column direction data transfer, the operation result can be output to all the operation elements belonging to the predetermined column. it can. Similarly, if address data for predetermined arithmetic control is externally transferred via a predetermined data line for row direction data transfer,
The operation result can be output to all operation elements belonging to a predetermined row. Furthermore, if address data for a predetermined operation control is externally transferred via both a predetermined data line for column-direction data transfer and a predetermined data line for row-direction data transfer, the predetermined data belonging to the corresponding row and column can be obtained. Can output operation result data to the operation element. Therefore, for example, the operation result can be output to a specific operation element.

Moreover, in the present invention, each column-direction data transfer data line is connected to a corresponding one row-direction data transfer data line. Therefore, only one of the input / output units of the data line for column data transfer and the data line for row data transfer needs to be used for input / output of the data transfer bus. Therefore, the number of input / output units is reduced and the size of the high-speed image processing device is reduced as compared with the case where both the data line for column-direction data transfer and the data line for row-direction data transfer are used for input / output with the outside. can do.

As described above, according to the present invention, since each column-directional data transfer data line is connected to one corresponding row-directional data transfer data line, the arithmetic elements and the rows arranged in the column direction are connected. Data transfer to the operation elements arranged in the direction is performed by using the data line for column direction data transfer and the data line for row direction data transfer in common. Each arithmetic element performs access to the data line for column-direction data transfer and the data line for row-direction data transfer individually, for example, at different timings from each other. Data exchange with the data transfer data line can be performed accurately, and data exchange with the outside can be performed accurately.

Here, the high-speed image processing apparatus comprises a light receiving element array in which a plurality of light receiving elements are two-dimensionally arranged in a plurality of rows and columns in a one-to-one correspondence with the plurality of arithmetic elements. , A plurality of A / D converters are provided for each of the plurality of rows of the light receiving element array and the plurality of rows of the arithmetic element array.
A / D converters are arranged in a one-dimensional manner corresponding to the above, and each A / D converter performs analog-to-digital conversion on output image signals sequentially read from the corresponding light receiving elements in one row. An A / D converter array for outputting the digital image signal to a corresponding row of the arithmetic element array, the light receiving element array, the A / D converter array, the parallel processing mechanism, and the data transfer bus. And a control circuit for controlling each of the arithmetic elements of the parallel arithmetic element array.
Preferably, a predetermined operation is performed on the digital image signal transferred from the converter array.

The output image signal of each light receiving element belonging to each row is sequentially read out, analog-to-digital converted by a corresponding A / D converter, and transferred to a corresponding arithmetic element belonging to the corresponding row. Thus, each arithmetic element receives a digital image signal which is image data of a corresponding pixel generated by a corresponding light receiving element. Each arithmetic element performs parallel arithmetic processing on the digital image signal at high speed.

Here, it is preferable to further include a data buffer corresponding to both the plurality of column-direction data transfer data lines and the plurality of row-direction data transfer data lines. For example, one of the input / output units of the column direction data transfer data line and the row direction data transfer data line is connected to the data buffer for input / output of the data transfer bus. Since each column-direction data transfer data line is connected to a corresponding one row-direction data transfer data line, this data buffer is divided into a plurality of column-direction data transfer data lines and a plurality of row-direction data transfer data lines. It can be used as a common data buffer for both of the lines.

For example, position data that can be commonly used as column position information and row position information can be stored in the data buffer in advance. When calculating the center of gravity,
By transferring the position data from the data buffer to the arithmetic element via the data line for column direction data transfer, the position information of the column can be transferred at high speed. Further, by transferring the position data from the data buffer to the arithmetic element via the data line for transferring data in the row direction, the position information of the row can be transferred at a high speed.

It is preferable that the apparatus further comprises an address data generation counter corresponding to both the data line for column data transfer and the data line for row data transfer. For example, one of the input / output units of the data line for column direction data transfer and the data line for row direction data transfer is connected to an address data generation counter for input / output of a data transfer bus. Since each column-direction data transfer data line is connected to a corresponding one row-direction data transfer data line, the address data generation counter is divided into a plurality of column-direction data transfer data lines and a plurality of row-direction data transfer data lines. Can be used as a common address data generation counter for both data lines.

The operation control address data generation counter is composed of, for example, a shift register, and can automatically and automatically generate operation control address data while counting sequentially generated clocks. The operation control address data is commonly used, for example, to select a column and a row. That is, by sequentially transferring the operation control address data generated sequentially through the column direction data transfer data line,
The columns can be sequentially selected, and the arithmetic elements belonging to the selected columns can execute the arithmetic processing or output the arithmetic results. Similarly, by repeatedly transferring the sequentially generated operation control address data via the row direction data transfer data line, the rows are sequentially selected, and the arithmetic elements belonging to the selected row execute the arithmetic processing. Or output the operation result.

The parallel processing mechanism further includes a plurality of transfer shift registers arranged in one-to-one correspondence with a plurality of A / D converters and a plurality of operation element rows, respectively. A transfer shift for sequentially transferring a digital image signal output from a corresponding A / D converter and corresponding to an output image signal of a light receiving element belonging to a corresponding light receiving element row to a predetermined arithmetic element belonging to the corresponding row. It is preferable to have a register array.

Since the transfer to the arithmetic elements is performed by the dedicated shift register, each arithmetic element can perform arithmetic processing even during the transfer. Therefore, since the arithmetic processing can be performed independently of the transfer processing, the arithmetic processing and the transfer processing can be efficiently performed. For example, the transfer processing and the arithmetic processing can be performed in parallel.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A high-speed image processing apparatus according to an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.

A high-speed image processing apparatus according to a first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram of a high-speed image processing apparatus 10 according to the present embodiment. FIG. 2 shows a configuration example of the high-speed image processing apparatus 10.

First, referring to FIG.
The overall configuration will be briefly described. The high-speed image processing apparatus 10 according to the present embodiment includes a parallel processing mechanism 14 for performing parallel arithmetic processing on image data of a digital signal. The high-speed image processing apparatus 10 of the present embodiment further includes a light receiving element array 11 and an A / D converter array 13 as an image capturing unit for generating image data of a digital signal and outputting the digital signal image data to the parallel processing mechanism 14. Further, the control circuit 15 and x / y
It includes a data bus 17, an instruction / command bus 16, and an output bus 155 (FIG. 6) described later.

The parallel processing mechanism 14 includes a processing element array 40 in which N × N processing elements (PE (processing elements)) 400 are arranged two-dimensionally (ie, N columns × N rows). Is provided. Here, N is a positive integer. The operation element array 40 includes N transfer shift register lines (image transfer shift register lines) 42 in one-to-one correspondence with the N operation element rows.
0 is added. Shift register line 4 for each transfer
Reference numeral 20 denotes a configuration in which N transfer shift registers (image transfer shift registers) 410 equal to the number (N) of the operation elements 400 belonging to the corresponding row are connected in series. Each transfer shift register 410 is connected to one corresponding arithmetic element 400 in a corresponding row, and inputs image data of a digital signal to the corresponding arithmetic element 400.

In the light receiving element array 11, N × N light receiving elements 120 are arranged two-dimensionally (ie, N columns × N rows) corresponding to the arithmetic elements 400. That is, the light receiving element array 11 includes a horizontal light receiving section 110 in which N light receiving elements 120 are arranged in the horizontal direction (x direction).
Are N vertical directions (y) orthogonal to the horizontal direction (x direction).
Direction).

The A / D converter array 13 has N A / D converters.
The D converters 210 are arranged one-dimensionally (in the vertical direction (y direction)). The N A / D converters 210 correspond one-to-one to the N horizontal light receiving units 110 in the light receiving element array 11 and are output from the light receiving elements 120 belonging to the corresponding horizontal light receiving units 110. The charge is sequentially converted to a voltage signal and further A / D converted.

The control circuit 15 controls the high-speed image processing apparatus 10
For sending and controlling command signals and data to the entire circuit. The x / y data bus 17 is connected to the arithmetic element 400 of each column, and has N 1-bit data lines 170 for transferring data to the arithmetic element 400 of each column.
And N 1-bit data lines 180 connected to the arithmetic elements 400 of each row and for transferring data to the arithmetic elements 400 of each row. The x / y data bus 17 is
It is connected to the control circuit 15. Instructions /
The command bus 16 is for sending a signal from the control circuit 15 to the light receiving element array 11, the A / D converter array 13, and the parallel processing mechanism 14. As shown in FIG. 6, which will be described later, the control circuit 15 further performs a wired OR operation with all the operation elements 400 through a single output bus 155.
It is connected.

Since the high-speed image processing apparatus 10 has the above configuration, the parallel processing mechanism 14 and the light receiving element array 11 can be connected by N data lines. Therefore, as shown in FIG. 2, the light-receiving element array 11 and the parallel processing mechanism 14 are formed on separate substrates, and the operation of each element can be confirmed.
The stable production of is possible. In addition, by forming the light receiving element array 11 and the parallel processing mechanism 14 on separate substrates in this way, both can be highly integrated, and a processing step adapted to the characteristics of each device can be achieved. The stable production is possible from the point that can be adopted. Also, each component of the high-speed image processing device 10 includes:
Since all components can be formed by a CMOS process, all the components can be made into one chip, which can greatly reduce the cost.

Next, the internal configuration of each circuit will be described.

FIG. 3 is a block diagram showing the configuration of the control circuit 15. The control circuit 15 includes a CPU 150, a memory 151,
The image capture control unit 300 (FIG. 4), the input / output interface 152 with the outside, and the like are connected by a bus 153. The memory 151 includes a CPU 150
An image processing program (FIG. 8) to be described later executed by the parallel processing mechanism 14 in the parallel image processing step (S110 in FIG. 8) in the image processing program.
A program for controlling the parallel processing of (for example,
9 to 13 and 16 to 21) are stored.
The memory 151 further has an address data storage area 154 (FIG. 14) described later. These image processing programs and parallel operation processing programs are written from an external device (for example, an external computer) 1000 to the memory 151 via the input / output interface 152. The bus 153 includes a command bus and a data bus (not shown), and is connected to the instruction / command bus 16 and the x / y data bus 17 in FIG. 1 and the output bus 155 in FIG.

The CPU 150 controls the light receiving element array 11 and the A / D converter array 13 via the image capturing control section 300 based on an image processing program (FIG. 8) in the memory 151, and also has a parallel processing mechanism. 14 is controlled. More specifically, the CPU 150 controls the image capture controller 300 (FIG. 4) (S101 in FIG. 8) to cause the light receiving element array 11 and the A / D converter array 13 to capture an image. The CPU 150 also controls the parallel processing mechanism 1
4 to control the data transfer by the transfer shift register 410 and the calculation by the arithmetic element 400 (S10 in FIG. 8).
2 to S104 and S110), SIMD (single i
(nstruction and multi data stream) type parallel operation processing. The CPU 150 further includes the parallel processing mechanism 1
During execution of the parallel operation processing of No. 4, necessary operations are performed, and necessary operations and determination operations are performed based on the processing results of the parallel processing mechanism 14. The CPU 150 further communicates with an external computer as the external device 1000 via the input / output interface 152,
For example, it controls an external actuator that is zero. For example,
The CPU 150 outputs the obtained calculation result to an external computer, and controls the external actuator based on the calculation result.

Next, the light receiving element array 11 serving as an image capturing section
The configuration of the A / D converter array 13 will be described in detail with reference to FIGS.

The light receiving element array 11 functions as a light receiving part for detecting light, and the A / D converter array 13 performs current / voltage conversion of an output signal from the light receiving part 11, and further performs A / D conversion.
Functions as a signal processing unit for performing the / D conversion processing. The image capturing control unit 300 of the control circuit 15
1 and the A / D converter array 13, and functions as a timing control unit that notifies the light receiving unit 11 and the signal processing unit 13 of an operation timing instruction signal.

First, the configuration of the light receiving element array (light receiving section) 11 will be described.

As shown in FIG. 4, in the light-receiving element array 11, each light-receiving element 120 includes a photoelectric conversion element 130 for generating an electric charge according to the input light intensity, and a photoelectric conversion element 130.
Of the horizontal scanning signal V _i (i = 0)
... N−1), and a switch element 140 that outputs the charge accumulated in the photoelectric conversion element 130 as one set. N light receiving elements 120 are arranged along the horizontal direction (x direction), and the switching elements 140 of each light receiving element 120 are electrically connected to each other to form the horizontal light receiving section 110. The light receiving unit 11 is configured by arranging N horizontal light receiving units 110 along a vertical direction (y direction) orthogonal to the horizontal direction. Therefore, the light receiving unit 11 includes the light receiving elements 120 _{i, j} (i = 0 to
N-1, j = 0 to N-1) are arranged two-dimensionally in N columns × N rows.

Next, the configuration of the A / D converter array 13 as a signal processing unit will be described with reference to FIG.

The A / D converter array 13 is configured by arranging N A / D converters 210 _j (j = 0 to N−1). Each A / D converter 210 _j (j = 0 to N−1)
This is for individually taking out and processing the charges transferred from the corresponding horizontal light receiving unit 110 _j (j = 0 to N−1), and outputting a digital signal corresponding to the charge intensity.

[0040] Each A / D converter 210 _j includes an integrating circuit 220 _j which includes a charge amplifier 221 _j, the comparison circuit 23
0 _j and a capacity control mechanism 240 _j .

The integration circuit 220 _j receives the output signal from the horizontal light receiving unit 110 _j as an input, and amplifies the charge of the input signal by a charge amplifier 221 _j and a charge amplifier 221 _j.
A variable capacitance section 222 _j having one end connected to the input terminal of the input terminal and the other end connected to the output terminal;
21 one end to the input terminal of the _j is connected, the other end consisting of a connected switch elements 223 _j to the output terminal.
The switch element 223 _j is turned ON and OFF in response to a reset signal R from the image capture control unit 300,
Integration of the integrating circuit 220 _j, is used to switch the non-integral operation.

FIG. 5 is a detailed block diagram of the integration circuit 220. This figure shows A having a resolution of 4 bits, that is, 16 gradations.
This is an example of an integrating circuit having a / D conversion function, and the following description will be given using this circuit configuration.

The variable capacitance section 222 includes a charge amplifier 22
One of the input terminals of the output signal from the horizontal light receiving section 110
C1 to C4 connected to the terminals of
The other terminals of 1 to C4 and the output terminal of the charge amplifier 221
And a capacitor indicating signal C₁₁~ C₁₄In response to the
Switch elements SW11 to SW14 that open and close, and capacitive elements
Between C1 to C4 and switch elements SW11 to SW14
One terminal is connected and the other terminal is connected to GND level.
Then, the capacity indication signal C_{twenty one}~ C_{twenty four}Open and close according to
It is composed of switch elements SW21 to SW24.
Note that the capacitance C of the capacitance elements C1 to C4₁~ C_FourIs C₁= 2C_Two= 4C_Three= 8C_Four  C₀= C₁+ C_Two+ C_Three+ C_Four  Satisfy the relationship. Where C₀Is required by the integration circuit 220
Is the maximum electric capacity, and the light receiving element 130 (see FIG. 4).
Q)₀And the reference voltage to V_REFThen C₀= Q₀/ V_REF  Satisfy the relationship.

Returning again to FIG. 4, the A / D converter 210 _j
The circuit other than the integrating circuit 220 _j will be described. Comparison circuit 2
30 _j is the integrated signal V _S output from the integrating circuit 220 _j
Is compared with a reference value V _REF to output a comparison result signal V _C. The capacity control mechanism 240 _j outputs a capacity indication signal C for notifying the variable capacity section 222 _j in the integration circuit 220 _j from the value of the comparison result signal V _C , and also outputs the capacity indication signal C (C
_{11 to} C ₁₄ ) are output.

Note that the A / D converter array 13 has four
Although the description has been given of the case where the resolution has 16 bits, that is, 16 gradations, the A / D converter array 13 may have a configuration having a resolution of another bit configuration such as 6 bits or 8 bits.

The image capturing units 11 and 13 having the above configuration
The timing of image capture is controlled by the image capture controller 300 in the control circuit 15. As shown in FIG. 4, the image capture control unit 300 generates a basic timing unit 310 that generates a basic timing for performing clock control of all the circuits 11 and 13, and outputs a horizontal scanning signal according to a horizontal scanning instruction notified from the basic timing unit 310. a horizontal shift register 320 for generating the V _i, and a control signal unit 340. which generates a reset instruction signal R.

Next, the configuration of the parallel processing mechanism 14 will be described.

As described above, the parallel processing mechanism 14 includes N horizontal light receiving sections 110 _j (j = 0 to N−1) of the light receiving element array 11 and A / D conversion as shown in FIG. A / D converters 210 _{j of the} detector array 13 (j = 0 to N−1)
Corresponding to N transfer shift register lines 420
_j (j = 0 to N−1). More specifically, N shift register lines for transfer 420 _j (j =
0 to N−1) are connected to N capacity control mechanisms 240 _j (j = 0 to N−1) of the A / D converter array 13.

Each transfer shift register line 420
_j (j = 0 to N−1) has a plurality of bits (4 in this case).
Shift register 410 _{i, j} (i = 0)
To N−1 and j = 0 to N−1) are connected in series. As shown in FIG. 6, a control circuit 15 is connected to each transfer shift register 410 _{i, j} via an instruction / command bus 16. Control circuit 15
Outputs the transfer start signal to each shift register 410 _{i, j} to transfer the data from the A / D converter array 13 to the required position of the arithmetic element 400.

The parallel processing mechanism 14 includes N × N light receiving elements 120 _{i, j} (i = 0 to N−1, j = 0 to N).
-1), the arithmetic elements 400 _{i, j} (i
= 0 to N−1 and j = 0 to N−1) are arranged two-dimensionally in N × N pieces. Each arithmetic element 400 _{i, j} (i = 0 to
N−1, j = 0 to N−1) correspond to the corresponding transfer shift registers 410 _{i , j} (i = 0 to N−1) of the corresponding shift register line 420 _j (j = 0 to N−1). j = 0
N-1). As shown in FIG. 6, a control circuit 15 is connected to each of the arithmetic elements 400 _{i and j} via an instruction / command bus 16, and controls arithmetic processing in the arithmetic element 400.

Next, the output bus 155 will be described.

As shown in FIG. 6, all the arithmetic elements 400 are connected to a single output bus 155. Here, the output bus 155 is composed of a single 1-bit signal line. Since the output bus 155 is connected to all the operation elements 400, a wired OR circuit (wiredO circuit) that communicates the OR logical operation result of the output of all the operation elements 400 to the control circuit 15
R circuit). For this reason, the control circuit 15
The output signals of all the operation elements 400 can be received after being collected, and the output signals can be received at high speed without using scanning.

Next, the x / y data bus 17 will be described.

As the x / y data bus 17, for example, a unidirectional data bus having only a function of transferring / writing data from the control circuit 15 to the arithmetic element 400 can be used. Alternatively, a bidirectional data bus having both a transfer / write function from the control circuit 15 to the arithmetic element 400 and an output / transfer function from the arithmetic element 400 to the control circuit 15 may be used. In this case, not only the data from the control circuit 15 is transferred to the arithmetic element 400 and written therein, but also the calculation result of the arithmetic element 400 is expressed as x /
It can be output to the control circuit 15 via the y data bus 17.

As shown in FIG. 7, the x / y data bus 17 includes a plurality of (in this case, N) 1-bit x data lines 170i (0 ≦ i ≦ N−1) and a plurality of (in this case, N) )
1-bit y data line 180j (0 ≦ j ≦ N−
1). In FIG. 7, the transfer shift register 410 is not shown for clarity. Each x data line 170i includes all N arithmetic elements 400 (i, j) located in the corresponding arithmetic element row i.
(0 ≦ j ≦ N−1). Further, each y data line 180j is composed of all N arithmetic elements 400 (i, j) (0 ≦ i ≦ N−1) located in the corresponding arithmetic element row j.
Is connected to Each x data line 170i (0 ≦ i
≤N-1) is the corresponding one y data line 180j
(0 ≦ j ≦ N−1), the connecting portion 175i (i = j: 0 ≦
i, j ≦ N−1). E.g., x data lines 170 _0, the y data lines 180 _0, via the connecting portion 175 ₀ is connected. Further, the x data line 170 ₁ is connected to the y data line 180 ₁ via the connection unit 175 ₁ .

The x / y data bus 17 having such a configuration is connected to the N / N
Input / output pins 170 at one end of the x data lines 170
e (0) to 170e (N−1), and the total N
It is connected to the control circuit 15 via the input / output pins 170e. Therefore, the x / y data bus 17 transfers data from the control circuit 15 to each input / output pin 170e.
(I: 0 ≦ i ≦ N−1), and by transferring the data to the corresponding x data line 170i, the data is transferred to all the processing elements 400 (i, j) located in the corresponding column i, and Further, by supplying the data to the corresponding y data line 180j via the connection portion 175i (i = j), the data is also transferred to all the arithmetic elements 400 (i, j) located in the corresponding row j. Can be. Further, each arithmetic element 400 (i, j) located in each column i transfers the data to the corresponding x data line 170i, thereby transferring the data to the corresponding input / output pin 170e (i: 0 ≦ i ≦ N-1)
To the control circuit 15. Further, each of the arithmetic elements 400 (i, j) located in each row j also transfers the data to the corresponding y data line 180 j, so that the data is transferred to the corresponding x via the connection unit 175 i (i = j). Data line 170j (i = j) and therefore the corresponding input / output pin 170e
(I = j: 0 ≦ i = j ≦ N−1) to output to the control circuit 15.

Next, regarding the structure of each arithmetic element 400,
This will be described in more detail with reference to the block diagram shown in FIG.

The arithmetic element 400 has a structure for performing SIMD parallel processing in which each element is controlled by a common control signal. The number of transistors per element is reduced, and the integration of the parallel processing mechanism 14 is reduced. As a result, the number of elements can be increased.

More specifically, the arithmetic element 400 is 4 × 8
It is composed of a 1-bit shift register matrix 401 capable of randomly accessing bits, an A latch 402, a B latch 403, and an arithmetic logic unit (ALU) 404. The register matrix 401 is for data retention and input / output. More specifically, the register matrix 401 includes the corresponding light receiving element 120
The digital signal D1 corresponding to the output signal is input from the shift register 410 and accommodated therein.

The register matrix 401 of each operation element 400 (i, j) is stored in the corresponding four adjacent operation elements 400 (i, j).
(I-1, j), 400 (i + 1, j), 400 (i, j)
j-1) and 400 (i, j + 1) are directly connected to the register matrix 401, and can also accommodate digital signals contained therein. The register matrix 401 of each arithmetic element 400 (i, j) is further connected to the corresponding x data line 170i and y data line 180j, so that data transfer can be performed using both data lines. ing.

The ALU 404 is for performing a sequential bit serial operation for sequentially calculating one bit at a time from the lower bits. The A-latch 402 and the B-latch 403 are for accommodating the signals held in the register matrix 401 and for performing the operation in the ALU 404.

With the above configuration, in the arithmetic element 400,
The A latch 402 and the B latch 403 each read data from an arbitrary register in the register matrix 401, and the ALU 404 performs an operation based on the data.
The operation result is written into an arbitrary register in the register matrix 401 again. The arithmetic element 400 can execute various arithmetic operations by repeating this operation as one cycle.

More specifically, the ALU 404 is a 1-bit arithmetic unit, and has arithmetic functions such as logical product (AND), logical sum (OR), exclusive logical sum (XOR), addition (ADD), and addition with carry. Have. Only one-bit operation can be performed at a time, and multi-bit operation is performed by performing serial operation one bit at a time. Complex operations can be described as a combination of the above functions,
By causing the ALU 404 to repeatedly perform the calculation while selecting one of the above-described calculation functions each time, a complicated calculation is realized.

The register matrix 401 has a structure in which 24 one-bit registers 4010 that can be accessed randomly are arranged, and eight function registers 4012 are arranged for input and output with the external and neighboring operation elements 400. Are treated as one address space.
In FIG. 6, the numbers described in the registers 4010 and 4012 indicate the addresses assigned to the registers. Specifically, addresses “0” to “23” are assigned to 24 registers 4010, and addresses “24” to “31” are assigned to eight function registers 4012. With such a configuration, input / output data can be accessed in the same manner as reading / writing data in the register.

The function register 4012 is mainly used for input / output. Specifically, the function register 4012 at the address “29” is connected to the corresponding transfer shift register 410 and is used for input from the transfer shift register 410. Further, the function register 4012 at the address “24” is used for outputting to the register matrix 401 of the four operation elements 400 in the up, down, left, and right directions. The function registers 4012 of addresses “24” to “27”
Each of the register matrices 401 of the corresponding one of the four neighboring computing elements 400
Used for input from.

Function register 4012 at address "28"
Are connected to the output bus 155 and are used as output addresses to the control circuit 15. Note that all the arithmetic elements 4
The address “28” of the register matrix 401 at 00 (i, j) is connected to the single output bus 155. Also, the function register 40 of the address “28”
Numeral 12 always reads 0 when reading.

Function register 4012 at address "30"
Are connected to the corresponding y data line 180j, and are used for inputting / outputting data from / to the y data line 180j. Further, the function register 4012 of the address “31” is connected to the corresponding x data line 170i, and is used for inputting / outputting data from / to the x data line 170i.

The control circuit 15 controls the register matrix 401
By controlling the access to the ALU 404 and the arithmetic processing of the ALU 404, all the arithmetic and input / output processing in the arithmetic element 400 are controlled.

For example, the input from the transfer shift register 410 is set to the address “0” of the register matrix 401.
0 (register address "2
8 ") and O of sensor input (register address" 29 ")
An instruction to write R to register address “0” is output to the arithmetic element 400. The arithmetic element 400 receiving this instruction outputs 0 (register address “28”) and a sensor input (register address “29”) to the A latch 402 and the B latch 403, and the ALU 404 The OR operation of the data of the latch 403 is performed, and the operation result is written to the register address “0”.

Similarly, the corresponding x data line 170i
If you want to write the data from
OR (register address “28”) and X data input (register address “31”) is ORed and an instruction to write to register address “0” is output to the arithmetic element 400. The arithmetic element 400 receiving the instruction sets the A latch 4
02 and the B latch 403 are set to 0 (register address "2
8 ") and the X data input (register address" 31 "), the ALU 404 performs an OR operation on the data of the A latch 402 and the B latch 403, and writes the operation result to the register address" 0 ".

Similarly, the corresponding y data line 180j
If you want to write the data from
OR (register address “28”) and Y data input (register address “30”) is ORed, and an instruction to write to register address “0” is output to the arithmetic element 400. The arithmetic element 400 receiving the instruction sets the A latch 4
02 and the B latch 403 are set to 0 (register address "2
8 ") and the Y data input (register address" 30 "), the ALU 404 performs an OR operation on the data of the A latch 402 and the B latch 403, and writes the operation result to the register address" 0 ".

As described above, in the arithmetic element 400, the reading of the A latch, the reading of the B latch, and the writing of the operation result are sequentially performed, and this processing is repeated a plurality of cycles, so that the necessary input / output to / from the register matrix 401 can be performed. The operation by the ALU 404 is performed.

Next, the operation of the high-speed image processing apparatus 10 according to the present embodiment will be described with reference to FIGS.

First, the operation of the image capturing units 11 and 13 will be described.

The image capture control unit 300 first sets the reset signal R to a significant value, and sets the reset signal R to the variable capacitance unit 22 shown in FIG.
2 SW11-SW14 are all "ON", SW21-S
Set all W24 to “OFF” state. As a result, the capacitance value between the input terminal and the output terminal of the charge amplifier 221 becomes C
Set to ₀ . At the same time, all the switch elements 140 shown in FIG.
_Is set so that none of the light receiving elements 120 _{i, j} is selected. From this state, the reset instruction signal R is set to be insignificant, and the integration operation in each integration circuit 220 is started.

[0076] When starting the integral operation, the 0-th light receiving element at the N pieces each horizontal receiving portion 110 _j shown in FIG. 4 12
A horizontal scanning signal V _{0 that} turns ON only the switch element 140 of _{0, j} is output. When the switch element is turned “ON”, the electric charge Q ₀ accumulated in the photoelectric conversion element 130 by the light reception up to that time is output from the light receiving unit 11 as a current signal. That is, a signal of the photoelectric conversion element can be read. The charge Q ₀ flows into the variable capacitance section 222 set to the capacitance value C ₀ .

Next, the operation inside the integrating circuit 220 will be described with reference to FIG.
Explain the work. The capacity control mechanism 240 (see FIG. 4)
After opening W12-SW14, close SW22-24
You. As a result, the integration signal V_SIs V_S= Q / C₁  Is output as the voltage value indicated by. Integration signal V_SCompare
The reference voltage value V_REFIs compared to
You. Where V_SAnd V_REFIs less than the resolution range,
That is, ± (C_Four/ 2) In the following cases, it is regarded as a match
However, no further capacity control is performed, and the integration operation ends. Minute
If they do not match within the range of resolution, perform additional volume control,
Continue the integration operation. For example, V_S> V_REFIf the capacity
After opening the SW 22, the control mechanism 240 further
Close W12. As a result, the integration signal V_SIs V_S= Q / (C₁+ C_Two). This integral signal V_SIs a subsequent comparison
Input to the circuit 230 (FIG. 4), the reference voltage value V_REFAnd ratio
Are compared. On the other hand, V_S<V_REFIf so, the capacity control mechanism 2
40, further, after opening SW11 and SW22,
SW12 and SW21 are closed. As a result, the integration signal V
_SIs V_S= Q / C_Two  It becomes the voltage value shown by. This integral signal V_SIs a subsequent comparison
The reference voltage V_REFIs compared to
You.

[0078] Thereafter, in the same manner, by the integration circuit 220 → comparator circuit 230 → the capacitance control mechanism 240 → the feedback loop of the integration circuit 220, until the integral signal V _S is coincident with the range of the reference voltage value V _{R EF} and resolution, Comparison and capacitance setting (O of SW11 to SW14 and SW21 to SW24
N / OFF control) is sequentially repeated. The value of the capacitance instruction signal C ₁₁ -C ₁₄ indicating the ON / OFF state of SW11~SW14 of time the integration operation is finished, a digital signal corresponding to the value of the charge Q _1, the value of the most significant bit (MSB) Is C
_11, the value of the least significant bit (LSB) is C _14. Thus, A / D conversion is performed, and these values are converted to digital signals D1.
Is output to the arithmetic element array 14. As described above, in this device, each bit value of the digital signal D1 is determined one bit at a time from the MSB side to the LSB side.

As described above, each of the capacitors C1 to C4 is
The comparison with the comparison voltage V _REF is performed while being N, and the comparison result is output as the output digital signal D1.
That is, first, the capacitor C1 is turned on, and the integration signal V _S
= Q / C1, and this _{V S} is compared with _{V REF.}
If V _S is large, it is “1” (= C ₁₁ ), and if V _S is small, it is “0” (= C ₁₁ ), which is output as MSB (most significant bit). Next, C2 is turned on and V
_S = Q / (C1 + C2) (when MSB = 1), or
V _S = Q / C2 (when MSB = 0) is obtained, and V _REF
Is compared to If V _S is large, “1” (=
C ₁₂ ), if smaller, “0” (= C ₁₂ ), which is output as the second bit. A / D conversion is performed by repeating the above processing up to the required number of bits.

[0080] When the transmission of the 0th light receiving element 120 0, _j digital signal corresponding to the photoelectric output is completed, the reset signal R is the significance, again, in the non-significance of the variable capacitance portion 222 _j After the capacitance value is initialized, each horizontal light receiving unit 11
0 _j 1st light receiving element 120 _{1, j} switch element 1
40 only outputs a horizontal scanning signal _{V 1} to the "ON"
By the same operation as described above, the first light receiving element 120
_The photoelectric output of _{1, j} is read, and a digital signal corresponding to this is transmitted. Hereinafter, the horizontal scanning signal is switched, the photoelectric output of all the light receiving elements 120 is read, and the corresponding digital signal is output to the parallel processing mechanism 14.

Next, the operation of the arithmetic element 400 will be described with reference to FIG.

The A / D-converted digital signal is transferred to each light-receiving element 1 via a transfer shift register 410.
20 _{i, j} is sent to the register matrix 401 of the operation element 400 _{i, j} . This transfer, in the corresponding transfer shift register line 420 _j, takes place by transferring the transfer shift register 410 sequentially neighboring pixel signals stored in the transfer shift register 410. By providing the transfer shift register 410, the transfer processing by the transfer shift register can be performed independently of the arithmetic processing by the arithmetic element 400. Therefore, while the processing element 400 is performing the processing operation, pipeline processing for transferring the data of the next frame to the transfer shift register 410 becomes possible, and the processing element 400 operates at a higher frame rate. Arithmetic processing becomes possible. The transfer shift register 410 starts transferring the A / D-converted data based on a transfer start signal from the control circuit 15, and performs bit shift by (the number of elements in the row direction × analog level). After the transfer, the signal of “data transfer completed” is sent back to the control circuit 15, so that efficient transfer can be performed. As described above, by performing the so-called pipeline processing in parallel with the arithmetic processing and the transfer processing, it is possible to reduce the waiting time between the processing for each frame in both processings,
Higher-speed image processing becomes possible.

The image processing operation inside the operation element 400 is as follows.
It is as follows. That is, if necessary, the signals contained in the respective register matrices 401 are transferred between the arithmetic elements 400, and the data and control signals are transferred from the control circuit 15 via the x / y data bus 17. After that, the signals necessary for the operation are
1 to the A latch 402 and the B latch 403.
The LU 404 performs a predetermined operation, and outputs the calculation result to the control circuit 15 via the register matrix 401 and the output bus 155.

In the parallel processing mechanism 14, the above image processing operation is performed in parallel by all the processing elements 400 at the same time.
Extremely high-speed operation is possible. The control circuit 15 outputs the calculation result of the parallel processing mechanism 14 to an external computer as the external device 1000 or another external device. For example, the calculation result is used as an on / off signal of the external device. The control circuit 15 may perform a necessary calculation based on the calculation result of the parallel processing mechanism 14 and then output the calculation result to the external circuit 1000.

Next, a series of image calculation processing from image input, transfer, and completion of calculation by the high-speed image processing apparatus 10 will be described with reference to FIG.

The CPU 150 of the control circuit 15 controls the image capture control unit 300 (FIG. 4) to sequentially switch between the validity / invalidity of the reset signal R and the horizontal synchronizing signal Vi. Of each row j (j = 0,...)
N-1), the image data (frame data: hereinafter, referred to as I (x, y)) output from the respective light receiving elements 120 _{i, j} (hereinafter, referred to as light receiving elements 120 (x, y)) correspond in order. is input to the parallel processing system 14 via the a / D converter 210 _j to (S101).

The transmitted data is sequentially transferred by the corresponding transfer shift register 410 in each row j (S102). The transfer process is continued until data is transferred to the transfer shift register 410 _{i, j} at the position (i, j) (hereinafter, (x, y)) corresponding to the light receiving element 120 (S103).

When the transfer is completed, the transfer shift register
410 to the corresponding arithmetic element 400 _{i, j}(Hereafter, calculation
Register matrix of element 400 (x, y)
The data I (x, y) of the pixel is transferred to 401
(S104). Specifically, as shown in FIG.
A transfer sheet consisting of a packet (in this case, 4 bits)
Shift register 410 to register matrix 401
And the data is stored in order one bit at a time. Next, S
At 110, by controlling each arithmetic element 400,
And perform necessary parallel processing.

When the transfer shift register 410 completes the data transfer to each operation element 400, each operation element 400
While performing the parallel operation processing of S110,
The process moves to the next frame (S105), and S101 to S101.
By executing S103, the light receiving element array 11, the A / D converter array 13, and the transfer shift register 410 are controlled to perform the input / transfer operation of the next frame. on the other hand,
Regarding the parallel operation processing using each operation element 400, 1
When the processing of the frame (S110) ends, the processing shifts to the processing of the next frame (S106), and the image data of the next frame is transferred from each transfer shift register 410 to the arithmetic element 4
00 to the register matrix 401 (S1
04), the parallel operation processing of the next frame is started (S110). By repeating this, the arithmetic element 400 is operated while the light receiving element array 11, the A / D converter array 13, and the transfer shift register 410 are inputting / transferring data of the next frame (S101 to S103). The used arithmetic processing (S110) can be performed, and unnecessary waiting time can be reduced.

Next, the execution operation of the parallel image processing (S110) using the arithmetic element 400 will be described in detail for some image processing. In these image processing steps,
The CPU 150 of the control circuit 15 controls all the arithmetic elements 400 at the same time in parallel, so that the arithmetic processing is performed at a very high speed.

In this embodiment, the x / y data bus 17
The operation data or the operation control data can be supplied to each operation element at high speed from outside via the CPU. Therefore, even in the case of performing an arithmetic process that requires data other than image information in each arithmetic element 400 at the time of the arithmetic operation in S110, an extremely high-speed arithmetic operation can be performed. For example, in the image processing step (S110), when performing “center of gravity calculation” that requires position information data, the position information is supplied as data from the outside and the center of gravity calculation processing is performed. Hereinafter, the operation when this center of gravity calculation process is executed in the image processing step (S110) will be described in detail.

Here, the gravity center calculation is a calculation based on the calculation of the weighted sum in each of the x direction and the y direction. The barycenter coordinate Gc is obtained by the following formula (1), using the image intensity data at each pixel position (x, y) on the image as I (x, y).

[0093]

(Equation 1)

That is, in order to calculate the center of gravity, it is necessary to multiply the data I (x, y) of the pixel by the position information (x, y) in each arithmetic element 400 to obtain the sum.

When obtaining the x-coordinate of the center of gravity, the x-direction moment Mx = x · I (x, y) is obtained by multiplying the image position information in the x direction by the image intensity I (x, y). Further, the x-coordinate of the center of gravity can be obtained by dividing the sum of x-direction moments ΣΣx · I (x, y) obtained by adding the x-direction moments of all pixels by the sum of image intensity ΣΣI (x, y). . Note that the image intensity sum ΣΣI (x,
y) can be obtained by adding the image intensities of all the pixels.

Similarly, for the y coordinate of the center of gravity, the position information in the y direction of the image and the image intensity I (x,
multiplied by y) and the moment in the y direction My = y · I
(X, y) is obtained, and further, the sum of the y-direction moments ΣΣy ·
It is obtained by dividing I (x, y) by the total image intensity ΣΣI (x, y).

Therefore, in order to obtain the position of the center of gravity of the input image, the center of gravity calculation processing as shown in FIG. 9 (S300)
May be performed in the image processing step S110 (FIG. 8).

In the center-of-gravity calculation processing (S300), first, S
At 350, the image intensity sum ΣΣI (x, y) is obtained. Next, at S400, the x coordinate of the center of gravity is obtained.
At 00, the y coordinate of the center of gravity is determined.

When the center-of-gravity calculation processing (S300) starts, the image data I of each pixel of the input image D
(X, y) is already transferred from the transfer shift register 410 to the register matrix 401 of each arithmetic element 400 (x, y) in S104 (FIG. 8) and stored in a certain area of the register matrix 401. ing.

First, the contents of the operation (S350) for calculating the image intensity sum ΣΣI (x, y) will be described in detail with reference to FIG.

In the image intensity sum calculation process (S350), the CPU 150 first performs a sum calculation process for obtaining the sum of the image intensity values I (x, y) in S360.

Hereinafter, the sum calculation processing (S360) will be described in detail with reference to FIG.

First, the target data (in this case, image data I (x, y)) for which the sum is to be obtained is read from the register matrix 401 into the A latch 402 (S1002). That is, the register matrix 40
The I (x, y) data stored in 1 is transferred to the A latch 402 from the lower bit. Next, each operation element 40
0 (x, y) is the arithmetic element 400 (x + y) existing at the pixel position (x + 1, y) adjacent in the x direction.
1, (y) is stored in the register matrix 4 (image data I (x + 1, y)).
01 and transferred to and stored in the register matrix 401 of the arithmetic element 400 (x, y) (S10).
04). Specifically, the image data value stored in the adjacent pixel is transferred to a vacant area by using the neighbor transfer function of the register matrix 401. Next, the transferred target data (image data I (x + 1, y)) of the adjacent pixel (x + 1, y) is read into the B latch 403 (S1006), and the values of the A latch 402 and the B latch 403 are added. (S1008), and the result of addition is stored in the A latch 402 via the register matrix 401 (S1010).
(S1012). Thereby, each pixel 40
In 0 (x, y), target data for two pixels (in this case,
The sum of the image data I (x, y) and I (x + 1, y)) is stored.

Next, after setting i = 1 as an initial setting for obtaining the sum in the x direction (S1014), each arithmetic element 40
In step S1018, 0 (x, y) is the pixel position (x + n, y) (where n is the second adjacent pixel) in the x direction.
= 2 ⁱ , where n = 2 ¹ = 2)
The calculation result (in this case, I (x + 2, y) + I (x + 3, y)) currently stored in (x + 2, y) is transferred twice between register matrices 401 adjacent in the x direction, thereby obtaining The data is transferred and stored in the arithmetic element 400 (x, y) (S1018). Next, the transferred calculation result data of the second adjacent pixel (x + 2, y) is read into the B latch 403 (S1020), and the values of the A latch 402 and the B latch 403 are added (S102).
2), the addition result is stored in the A latch 402 via the register matrix 401 (S1024) (S102).
6). Thus, each pixel 400 (x, y) has image data I (x, y), I (x + 1,
y), the sum of I (x + 2, y) and I (x + 3, y) is stored.

Next, i is incremented by one (S102).
8), the resulting n = ^{2 i} is determined whether or not exceed N / 2 which is half the value of the number of one row of pixels (S1030), N / 2
If not exceeded (No in S1030), S1018
Return to In S1018, each arithmetic element 400 (x, y)
Is the position (x + n, y) adjacent to the n-th (n = 2 ⁱ ;
In this case, the calculation result data (the addition result of the image data) currently stored in the arithmetic element 400 of n = 2 ² = 4)
Is repeated n times (in this case, four times) between register matrices 401 adjacent in the x direction to the arithmetic element 400 (x, y) and read into the B latch 403 (S1020). (S102)
2 to S1026).

Subsequently, i is incremented by 1 (S
1028), by repeating the processing of S1018 to S1030, 8 (n = 2 ³ ) next, 16 (n = 2 ⁴ )
Next, 32 (n = 2 ⁵ ) neighbors, 64 (n = 2 ⁶ ) neighbors,..., And the addition is repeated until (N / 2) neighbors. As a result,
Addition result I (0, y) + of all image intensities in each row
I (1, y) + I (2, y) +... + I (N-1, y)
Is the A of the arithmetic element 400 (0, y) at the head of the row.
This is obtained in the latch 402 (S1026). If n exceeds N / 2 (Yes in S1030), the flow shifts to S1032.

After S1032, the image intensity addition results obtained for each row are added using the same method as described above, whereby the image intensity sum ΣΣI (x, y) is obtained.

Specifically, j = 0 was set as an initial setting.
(S1032) After that, each arithmetic element 400 (x, y) has y
(X, y + m) (where m
= 2 ^j, In this case, m = 2^j= 1) Arithmetic element
400 (x, y + m) (in this case, 400 (x, y +
1)) is added to the register matrix 401
By transfer, the register mat of the arithmetic element 400 (x, y)
Stored in the RIX 401 (S1034). Then,
The operation result of the adjacent pixel (x, y + 1) is stored in the B latch 403.
Read (S1036), A latch 402 and B latch 4
03 is added (S1038), and the addition result is registered.
It is stored in the star matrix 401 (S1040). This
Thereby, the arithmetic element 400 (0, y) at the head of each row
Stores the sum of the operation results for two rows.

Next, j is incremented by 1 (S104).
4) It is determined whether or not m = 2 ^j has exceeded N / 2, which is a half value of the number of pixels in one column (S1046). If it has not exceeded N / 2 (No in S1046), it is obtained in S1038. After transferring the obtained addition result from the register matrix 401 to the A latch 402 (S1048), the process returns to S1034.

Next, each arithmetic element 400 (x, y) is located at the position (x, y + m) (m = 2 ^j ; in this case, the position (x, y)
+2)) is transferred to the adjacent register matrix 401 by the addition result stored in the arithmetic element 400.
By repeating this operation twice, the data is transferred to the arithmetic element 400 (x, y) (S1034) and read into the B latch 403 (S1034).
1036), the same addition is performed (S1038 to 104).
0).

Subsequently, j is incremented by 1 (S
1044), by repeating the processing of S1046 to S1040, four (m = 2 ² ) next and eight (m = 2 ³ )
Next, 16 (m = ^{2 4)} next, 32 (m = ^{2 5)} next to 6
4 (m = 2 ⁶ ) neighbors,..., And the addition is repeated up to the (N / 2) neighbors, thereby adding the image intensity of all pixels.
ΣI (x, y) is the register matrix 401 of the operation element 400 (0, 0) at the head of the operation element array 40.
(S1040). When m exceeds N / 2, (S
If Yes in 1046), the sum calculation processing ends.

When the summation processing (S360) is completed,
Pixel selection processing for selecting the target pixel position (x1, y1) (in this case, the head pixel position (0, 0)) (S37)
0) (FIG. 10).

Hereinafter, the pixel selection processing (S370) will be described in detail with reference to FIG.

In the pixel selection processing, the CPU 150
First, in S1102, an x data line 170i (hereinafter, “x data line 1”) corresponding to an x address position x1 of a target pixel position (x1, y1) to be selected is selected.
70x "), and data (0) to all remaining x data lines 170x.
In this case, an x data line 170x (x = x1 = x1) corresponding to the x address position x1 of the head pixel position (x1 (= 0), y1 (= 0)) which is the target pixel position to be selected.
Data (1) is transferred to (0), and data (0) is transferred to all the remaining x data lines 170x (x ≠ x1).

Next, the transfer data from the corresponding x-direction data line 170x is stored in the register matrix 401 of each operation element 400 (x, y) (S110).
4). That is, the input data of the register address “31” is stored in a certain area in the register matrix 401. As a result, of all the operation elements 400, the operation element 400 (0, y) whose x address is x1 (= 0) (0 ≦ y ≦
Data (1) is stored only in the register matrix 401 of (N-1), and data (0) is stored in the register matrices 401 of the other arithmetic elements 400.
Next, this data is transferred to the A latch 402 (S11).
06).

In S1102, x data line 1
When data (1) is transferred to 70x (x = x1 = 0),
Connection part 17 to x data line 170x (x = x1 = 0)
The data (1) is also transferred to the y data line 180y (y = x1 = 0) connected via 5x (x = x1 = 0). However, in S1104,
Since the arithmetic element 400 operates to store the input data of the register address “31”, it does not store the input data of the register address “30”. Therefore, data (1) is not input to the corresponding arithmetic element 400 from the y data line 180y (y = x1 = 0). Therefore, the data (1) is input only to the arithmetic element 400 existing in the column x = x1 = 0.

Next, in S1108, the CPU 150 sets the y address position y1 of the target pixel position (x1, y1).
Is transferred to the y-direction data line 180j (hereinafter, referred to as “y-direction data line 180y”), and data (0) is transferred to all the remaining y-direction data lines 180y. Specifically, the CPU 150
Y-direction data line 180 corresponding to address position y1
x-direction data line 170 connected to y (y = y1)
Data (1) is transferred to x (x = y = y1), and data (0) is transferred to all remaining x-direction data lines 170x (x ≠ y (y1)). That is, in this case, the head pixel position (x1
Data (1) is transferred to the y-direction data line 180y (y = y1 = 0) at the y-address position y1 of (= 0), y1 (= 0), and all the remaining y-direction data lines 18
To transfer the data (0) to 0y (y （y1), the data (1) is transferred to the x-direction data line 180x (x = y1 = 0), and all the remaining x-direction data lines 18 are transferred.
Data (0) is transferred to 0x (x ≠ y1).

Next, the transfer data from the corresponding y-direction data line 180y is stored in the register matrix 401 of each arithmetic element 400 (x, y) (S111).
0). That is, the input data of the register address “30” is stored in a certain area in the register matrix 410. As a result, of all the arithmetic elements 400 (x, y),
Arithmetic element 400 (x, 0) with y address y1 (= 0)
Data (1) is stored only in the register matrix 401 of (0 ≦ x ≦ N−1), and the other arithmetic elements 400
The data (0) is stored in the register matrix 401 of FIG. Next, this data is stored in the B latch 403.
(S1112).

It should be noted that also in S1108, the x data line 1
70x (x = x1 = 0) and y data line 180y (y
= Y1 = x1 = 0), the data (1) is transferred. However, in S1110, the arithmetic element 4
00 operates so as to store the input data of the register address “30”, and thus does not store the input data of the register address “31”. Therefore, data (1) is not input from the x data line 170x (x = x1 = 0) to the corresponding arithmetic element 400. Therefore, the data (1) is input only to the arithmetic element 400 existing in the row y = y1 = 0.

Next, in each arithmetic element 400 (x, y), the value of the A latch 402 and the value of the B latch 403 are multiplied by the ALU 404 (S1114), and the arithmetic result is stored in the register matrix 401 (S111).
6). As a result, the operation element 400 (x1, y1) of the target address (x1, y1) (in this case, the head operation element 40
0 (0, 0)), the multiplication result 1 is set, and in the other arithmetic elements 400, the multiplication result 0 is set. Thus, the pixel selection processing (S370) ends.

When the pixel selection processing (S370) is completed,
The process moves to S372 (FIG. 10). In S372, the multiplication result obtained in the pixel selection processing (S370) is transferred from the register matrix 401 to the A latch 402 (S372).
372). Next, the operation result finally obtained in the sum operation processing (S360) is also transferred from the register matrix 401 to the B latch 403 (S374). Next, the ALU 404 multiplies the value of the A latch 402 by the value of the B latch 403 (S376). As a result, the arithmetic element 400 at the start address (0, 0) obtains the total image intensity ΣΣI (x, y) as the result of multiplication of the sum operation result ΣΣI (x, y) and (1). On the other hand, in the other operation elements 400, the sum operation result and 0 (zero)
As a result of the multiplication, zero (0) is obtained. S37
8, the multiplication result is stored in the register matrix 401, and the multiplication result is stored in the output bus 15 from the output address "28" of the register matrix 401 in S380.
5 is output. As a result, S37 in all arithmetic elements 400
6 will be output to a single output bus 155. Here, the operation element 400 (0, 0) at the head position
Only outputs the sum of image intensities ΣΣI (x, y) as the multiplication result, and all the remaining arithmetic elements output zero (0) as the multiplication result. Therefore, the output bus 155 transfers the image intensity sum ΣΣI (x, y), which is the OR logical operation result of the operation results from all the operation elements 400, to the control circuit 15. The CPU 150 stores the received image intensity sum ΣΣI (x, y) in the memory 151.

When the x / y data bus 17 is bidirectional, in S380, the multiplication result is set to x / y
It can be output to the control circuit 15 via the y data bus 17. That is, in this case, the address “30” of the register matrix 401 in the arithmetic element 400
Or, “31” is added to the corresponding y-direction data line 180.
What is necessary is just to use it for the output of the data to the y and x direction data line 170x. Specifically, in S380, the multiplication result is stored in the register matrix 401 at the address “3”.
From "0" or "31", the data is output to the x / y data bus 17. As a result, the multiplication result of S376 in all the operation elements 400 is output to the x / y data bus 17.
Here, only the operation element 400 (0, 0) at the head position outputs the image intensity sum ΣΣI (x, y) as a multiplication result,
All the remaining arithmetic elements output zero (0) as a multiplication result. The CPU 150 executes the corresponding data line 170
_{x = 0} through the received image intensity sum ΣΣI (x,
y) may be stored in the memory 151.

Next, the calculation processing of the x-axis coordinate of the center of gravity (S4
00) will be described in detail with reference to FIG.

First, the CPU 150 executes steps S402 to S41.
0, the x-direction position information (x address data “x”) of each pixel, which is data necessary for the center of gravity calculation, is stored in the memory 151.
, And transfers the data to each of the arithmetic elements 400 so that the x-address data “x” and the image data I
Multiplication with (x, y) is performed.

Here, the transfer of the x address data “x” is performed by transferring each address data to the corresponding data line 170.
This is performed by transferring the lower bits in a bit-by-bit manner in order of 1 bit by x. Where x
The x address data of the pixels connected to the direction data line 170x is binary data having the same value and any one of 0 to N-1. Therefore, in each data line 170x, the binary data of the corresponding x address is transferred by log ₂ (N) bits in order from the lower bit, so that the corresponding x address is transferred to all the operation elements 400 (x, y). It is possible to

In the present embodiment, m (= log ₂ N) addresses n = 0 to m−1 are set in the address data storage area 154 of the memory 151, and each address has an N-bit binary number. Address data is stored. The N-bit binary address data of each address n is “0” to “N−1”.
, And the corresponding bit value of the N binary values. For example, when the number of pixels is N × N = 8 × 8 (N = 8), the address data storage area 154 stores FIG.
, Three (m = log ₂ 8) addresses 0 to 2 are set, and these addresses 0 to 2 are respectively binary 8-bit address data 0101101, 00110.
011000001111 is stored. here,
Address data 0101101 of address 0 is “0” to
It is made up of 0, 1, 0, 1, 0, 1, 0, 1, which is the least significant bit (0th bit) of the binary value of "7 (= N-1)". Also, the address data 00110 of the address 1
011 is composed of 0, 0, 1, 1, 0, 0, 1, 1 which is the first bit of the binary value of “0” to “7 (= N−1)”. Furthermore, the address data 000 of address 2
01111 is 0, 0, 0, 0, 1, which is the most significant (second bit) of the binary value of “0” to “7 (= N−1)”.
1, 1, 1. The CPU 150 reads the memory contents (8-bit address data) while sequentially changing the memory addresses of the address data storage area 154 to 0, 1, and 2, and stores each bit of the read 8-bit address data in the corresponding x data line ₁₇₀ 0-17
And transfers it to the 0 _7. As a result, the x data line 170 ₀
To 170 _7, a corresponding x-address data is transferred one by one bit from the least significant bit. For example, the x data line 170 _0, x address data "000" is transferred from the least significant bit first. Also,
The x data line 170 _6, x address data "11
"0" are sequentially transferred from the least significant bit.
Outputs an instruction to each of the arithmetic elements 400 at the same time as the transfer, stores the transferred address data from the register address “31”, and further outputs the image data I
By performing multiplication with (x, y), the moment Mx
Is calculated.

More specifically, the CPU 150 first executes S4
At 02, n = 0 is initialized. Next, in S404, the memory address of the address data storage area 154 is set to n =
The address is set to 0, and the address data (01010101 when N = 8) stored in the memory address is transmitted via the x / y data bus 17. As a result, the least significant bit (0th bit) of the x address data is transferred to the arithmetic element 400 (x, y) to which each x data line 170x is connected. For example, 400 (0, y) (0 ≦ y
≦ N−1) is 0, 400 (1, y) (0 ≦ y ≦ N−
1 is transferred to 1).

In S406, each arithmetic element 400 (x,
In y), the input data of the register address “31” (the transfer data from the corresponding x data line 170x) is written, and multiplication with the image data I (x, y) is performed. Further, the result of the multiplication, that is, (Xx2 ⁿ ) xI (x,
y) (where n = 0) is assigned to the register matrix 401
Is added to the value M (t) stored in the predetermined area of. Here, the value of M (t) is initialized to 0 here. Then, the operation result M (t + 1) (= (Xx
²ⁿ ) xI (x, y) + M (t)) is stored in the predetermined area of the register matrix.

Next, in S408, n is incremented by one, and the current n and the binary value m (= lo
g ₂ N). If n is smaller than m (S41
0, yes), and returns to S404.

In S404, the address data stored in the current memory address n = 1 (in this case, 00110
011) is transferred to the x / y data bus 17. As a result, the arithmetic element 4 to which each x data line 170x is connected
The first bit of the x address data is transferred to 00 (x, y). For example, 400 (0, y) (0 ≦ y ≦
N-1) is 0, 400 (1, y) (0≤y≤N-1)
0 is also transferred. In S406, each of the arithmetic elements 400
(X, y) is input data of the register address "31" (transfer data from the corresponding x data line 170x)
Is written, and further multiplied by the image data I (x, y). At this time, the multiplication is performed by shifting one bit upward to correspond to the carry from the previous multiplication. In other ^words, it calculates the (Xx2 n) xI (x, y) ( where, n = 1). Further, this multiplication result is compared with the previous multiplication result M
(T) and the operation result M (t + 1) is stored in a predetermined area of the register matrix.

In S408, n is incremented by one again. If n is smaller than m (yes in S410), the flow returns to S404.

In S404, the address data stored in the current memory address n = 2 (00001 in this case)
111) is transferred to the x / y data bus 17. As a result, the arithmetic element 4 to which each x data line 170x is connected
To 00 (x, y), the second bit (the most significant bit in this example) of the x address data is transferred. For example, 400 (0, y) (0 ≦ y ≦ N−1) indicates 0, 4
0 is also transferred to 00 (1, y) (0 ≦ y ≦ N−1). In S406, each arithmetic element 400 (x, y) writes the input data of the register address “31” (transfer data from the corresponding x data line 170x), and further multiplies the image data I (x, y) by Is performed while shifting to the higher order by one bit. The multiplication result ((Xx2 ⁿ )
xI (x, y)) (where n = 2) is added to the previous multiplication result M (t), and the sum M (t + 1) is stored in a predetermined area of the register matrix.

In step S408, when n is incremented by 1, n becomes 3. In this example, since n = m (no in S410), the process proceeds to S420.

Thus, in S402 to S410, each bit is multiplied by the image data I (x, y) while transferring the x address data from the least significant bit to the most significant bit, and the bit is incremented every time the digit is increased. Shift and add. For example, if the image data I (x, y) is “1001”
In the case of the arithmetic element 400 (6, y) (0 ≦ y ≦ N−1) where the x address is x = 6 (“110”), FIG.
5 is performed, and the x moment value x · I (x,
y) is obtained and stored in a predetermined area of the register matrix.

Next, in S420, a total sum calculation process for obtaining the total sum of the x-direction moment values (xI (x, y)) in all the pixels is performed.

In the total sum calculation processing (S420), FIG.
1 is performed using the x-direction moment value (x · I (x, y)) as target data.

More specifically, in S1002, in each operation element, the x-direction moment value (x · I (x, y)), which is the target data for which the sum is to be obtained, is transferred from the register matrix 401 to the A latch 402. I do. Next, S10
At 04, the arithmetic element 400 (x, y) at the position (x + 1, y) adjacent to the arithmetic element 400 (x, y) in the x direction
+1, y) in the x direction ((x + 1) · I (x
+1, y)). The x-direction moment value ((x + 1) .I (x + 1, y)) is stored in the B latch (S1006), and the values of the A latch and the B latch are added to obtain the x-direction moment in the two adjacent pixels. The values are added, and the addition result is stored in the A latch 402 via the register matrix 401 (S10).
08 to S1012). As a result, each pixel 400 (x,
y) is the sum of x-direction moment values for two pixels (x · I
(X, y) + (x + 1) .I (x + 1, y)) will be stored.

Next, i = 1 is set as an initial setting (S1).
014) After that, each of the arithmetic elements 400 (x, y) returns to S101.
8 to S1026, the stored addition result (x ·
I (x, y) + (x + 1) .I (x + 1, y)) and x
Pixel position (x + n, y) adjacent to the second in the direction
(Here, n = 2 ⁱ , in this case, n = 2 ¹ = 2) The addition result ((x + 2) · I (x + 2, y) + (x + 3) stored in the arithmetic element 400 (x + 2, y)・ I (x
+3, y)).

Subsequently, i is incremented by one (S
1028), by repeating the process of S1018～S1030, 4 pieces (n = ^{2 2)} next, eight (n ^{= 2} 3)
Neighbor, 16 (n = 2 ⁴ ) neighbors, 32 (n = 2 ⁵ ) neighbors, 6
4 (n = 2 ⁶ ) neighbors,..., And transfer / addition is repeated up to (N / 2) neighbors. As a result, the addition result of all the x-direction moment values in each row 0 · I (0, y) + 1 · I
(1, y) + 2 · I (2, y) + ... + (N−1) · I
(N-1, y) is the arithmetic element 400 at the head of the row.
(0, y).

Next, j = 0 is set as an initial setting (S1).
032) After that, in S1034 to S1040, each arithmetic element 400 (x, y) adds the addition result to a position (x, y + m) adjacent in the y direction (where m = 2 ^j , in this case, m = 2 ^j = 1) arithmetic element 400 (x, y + m)
(In this case, the addition result of 400 (x, y + 1)) is
Perform transfer / addition processing for addition.

Subsequently, j is incremented by 1 (S
1044) and repeating the processing of S1046 to S1040, two (m = 2 ¹ ) next, four (m = 2 ² )
Next, 8 (m = 2 ³ ) neighbors, 16 (m = 2 ⁴ ) neighbors, 32
Next (m = 2 ⁵ ), 64 (m = 2 ⁶ ), ...
(N / 2) Repeat transfer / addition to the next. As a result, the addition result of the x-direction moment values of all pixels ΣΣx · I (x,
y) is the operation element 40 at the head of the operation element array 40
0 (0, 0), and the sum calculation processing (S420) ends.

When the summation processing (S420) is completed,
The process proceeds to S430 (FIG. 13).

At S430, a pixel selection process for selecting the head pixel position (0, 0) is performed.

In this pixel selection processing, the same processing as the pixel selection processing described with reference to FIG. 12 is performed. as a result,
In S1114 to S1116, the top processing element 400
The multiplication result (1) is set only in (0, 0), and the multiplication result (0) is set in other arithmetic elements 400.

When the pixel selection processing (S430) is completed,
The process moves to S432 (FIG. 13). In S432, the multiplication result obtained in the pixel selection processing (S430) is transferred from the register matrix 401 to the A latch 402. Next, the sum operation result finally obtained in the sum operation processing (S420) is also transferred from the register matrix 401 to the B latch 403 (S434). Then, A
In the LU 404, the value of the A latch 402 and the value of the B latch 403
Is multiplied (S436). As a result, the arithmetic element 400 at the start address (0, 0) has the sum operation result ΣΣ
As a result of multiplication of x · I (x, y) and (1), the total moment in the x direction ΣΣx · I (x, y) is obtained. On the other hand, in another arithmetic element 400, zero (0) is obtained as a result of multiplication of the sum operation result and 0 (zero). Next, in S438, the multiplication result is stored in the register matrix 401, and in S440, the multiplication result is output to the output bus 155 from the output address “28” of the register matrix 401. As a result, all operation elements 40
The result of the multiplication of S436 at 0 will be output to the output bus 155. Here, the operation element 400 at the head position
Only (0, 0) outputs the sum of moments in the x direction ΣΣx · I (x, y) as the multiplication result, and all the remaining arithmetic elements output zero (0) as the multiplication result. Therefore,
The output bus 155 provides a sum of x-direction moments, which is an OR logical operation result of the operation results from all the operation elements 400.
x · I (x, y) is transferred to the control circuit 15.

When the x / y data bus 17 is of a bidirectional type, in S440, the multiplication result is represented by x / y
The data may be output to the control circuit 15 via the y data bus 17. Specifically, in S440, the multiplication result is stored in the address “30” or “31” of the register matrix 401.
Thus, the data is output to the x / y data bus 17. CPU 150
Is the sum of the moments in the x direction 演算 x · I via the data line 170 _{x = 0} corresponding to the arithmetic element 400 (0,0).
(X, y).

Next, in S450, the CPU 150
Is the sum of the received x-direction moments ΣΣx · I
By dividing (x, y) by the total image intensity ΣΣI (x, y), the x coordinate of the center of gravity is obtained.

Next, the process proceeds to S500 and S50.
At 0, the y-coordinate of the center of gravity is determined in the same way as the x-coordinate of the center of gravity is determined.

That is, as shown in FIG.
First, in S502 to S510, the y-direction position information (y-address data) of each pixel, which is data necessary for the center of gravity calculation, is read from the memory 151, and each of the arithmetic elements 40 is read.
0, and causes each arithmetic element 400 to multiply the corresponding y address data by the image data I (x, y).

Here, the transfer of the y address data is also performed for each y address data.
Address data is transferred by the corresponding data lines 170x and 180y via the data buffer 17 in a bit-serial manner, one bit at a time starting from the lower bit. Here, the y address data of the pixel connected to each y direction data line 180y is:
The binary data is equal to each other and has a value of any one of 0 to N-1. Therefore, each data line 180y
In this case, the binary data of the corresponding y address is transferred in order of log ₂ (N) bits from the lower bit, so that all the arithmetic elements 400 (x, y) of the corresponding y address are transferred.
Can be transferred to

In the present embodiment, as described above, the memory 1
The address data storage area 154 of m.
g ₂ N) addresses n = 0 to m−1 each store N-bit binary address data, and this address data is used not only as x address data but also as y address data.
Also used as address data. For example, when the number of pixels is N × N = 8 × 8 (N = 8), 3 (= log ₂ ) is stored in the address data storage area 154 as shown in FIG.
8) binary 8-bit address data 010101
01,00110011,000011111 is address 0
~ 2. Therefore, as in the case of the x-direction center of gravity calculation, the CPU 150 sets the address data storage area 1
While changing the memory address of 54 to 0, 1, 2 and sequentially read the memory contents (8-bit address data), transfer each bit of the 8-bit address data, in the corresponding x data line ₁₇₀ 0-170 ₇ I do. as a result,
The respective bit data via connection ₁₇₅ 0-175 _7, are transferred to the corresponding y data lines ₁₈₀ 0-180 _7. Therefore, each of the y data lines 180 ₀ to 18 ₀
Against 0 _7, so that the corresponding y address data is transferred one by one bit from the least significant bit. For example, the y data lines 180 _0, y address data "000" is transferred from the least significant bit first. Also,
The y data line 180 _6, y address data "11
"0" are sequentially transferred from the least significant bit.
Outputs an instruction to each arithmetic element 400 at the same time as the transfer, stores the transferred address data from the register address “30”, and further stores the image data I
The moment My is calculated by performing multiplication with (x, y).

More specifically, the CPU 150 first
At 502, n = 0 is initialized. Next, in S504, the memory address of the address data storage area 154 is set to n =
The address is set to 0, and the address data (01010101 when N = 8) stored in the memory address is transmitted via the x / y data bus 17. As a result, the least significant bit (0th bit) of the y address data is transferred to the arithmetic element 400 (x, y) connected to each y data line 180y. For example, 400 (x, 0) (0 ≦ x
≦ N−1) includes 0, 400 (x, 1) (0 ≦ x ≦ N−
In 1), 1 is transferred.

In S506, each of the arithmetic elements 400 (x,
y) writes the input data of the register address “30” (the transfer data from the corresponding y data line 180x), and further multiplies the input data by the image data I (x, y). Further, this multiplication result, that is, (Yx2 ⁿ ) x
I (x, y) (here, n = 0) is added to a value M (t) stored in a predetermined area of the register matrix 401. Note that the value of M (t) is initialized to 0. Then, the calculation result M (t + 1) (= (Yx2 ⁿ ) x
I (x, y) + M (t)) is stored in the predetermined area of the register matrix.

Next, in S508, n is incremented by one, and the current n and the binary value m (= lo
g ₂ N). If n is smaller than m (S41
0, yes), and returns to S504.

In S504, the address data stored in the memory address n = 1 (in this case, 0011001)
1) is transferred to the x / y data bus 17. As a result,
Arithmetic element 400 to which each y data line 180y is connected
The first bit of the y address data is transferred to (x, y). For example, 400 (x, 0) (0 ≦ x ≦ N−
0 is transferred to 1), and 0 is also transferred to 400 (x, 1) (0 ≦ x ≦ N−1). In S506, each arithmetic element 400 (x,
y) writes the input data of the register address "30" (the transfer data from the corresponding y data line 180y), and further multiplies the image data I (x, y). At this time, corresponding to the carry from the previous multiplication, 1
The multiplication is performed by shifting the bits upward by bits. That is, (Y
x2 ⁿ ) xI (x, y) (where n = 1) is calculated. Further, the multiplication result is added to the previous multiplication result M (t), and the operation result M (t + 1) is stored in a predetermined area of the register matrix.

In step S508, n is incremented by one.
If n is smaller than m (yes in S410), S again
Return to 504.

In S504, the address data stored in the memory address n = 2 (in this case, 0000111)
1) is transferred to the x / y data bus 17. As a result,
Arithmetic element 400 to which each y data line 180y is connected
The second bit (the most significant bit in this example) of the y address data is transferred to (x, y). For example, 400 (x, 0) (0 ≦ x ≦ N−1) indicates 0, 40
0 is also transferred to 0 (x, 1) (0 ≦ x ≦ N−1).
In S506, each arithmetic element 400 (x, y) writes the input data of the register address “30” (the transfer data from the corresponding y data line 180y), and furthermore,
The multiplication with the image data I (x, y) is performed while shifting to the higher order by one bit. The multiplication result (Yx2 ⁿ ) xI
(X, y) (where n = 2) is the previous multiplication result M
(T), and the sum M (t + 1) is stored in a predetermined area of the register matrix.

In step S508, when n is incremented by 1, n becomes 3. In this example, since n = m,
(No in S510), the process proceeds to S520.

Thus, in S502 to S510, each bit is multiplied by the image data I (x, y) while transferring the y address data from the least significant bit to the most significant bit. Shift and add. For example, if the image data I (x, y) is “1001”
In the case of the arithmetic element 400 (x, 6) (0 ≦ x ≦ N−1) where the y address is y = 6 (“110”), FIG.
5 is performed, and the y moment value y · I (x,
y) is obtained and stored in a predetermined area of the register matrix. As described above, in the present embodiment, the address data storage area 154 having an N-bit width is formed in the memory 151, and m (m = log ₂ N) N-bit binary addresses are stored in the address data storage area 154. Data is stored. The m pieces of N-bit binary address data are used as common address data (x-direction address data and y-direction address data) in the x-direction moment calculation and the y-direction moment calculation.

Next, in S520, a total sum calculation process is performed to obtain the total sum of the y-direction moment values (y · I (x, y)) in all the pixels.

In the total sum calculation processing (S520), FIG.
1 is performed using the y-direction moment value (y · I (x, y)) as target data.

Specifically, in S1002, in each arithmetic element, the y-direction moment value (yI (x, y)), which is the target data for which the sum is to be obtained, is transferred from the register matrix 401 to the A latch 402. I do. Next, S10
At 04, the arithmetic element 400 (x, y) at the position (x + 1, y) adjacent to the arithmetic element 400 (x, y) in the x direction
+1, y) in the y direction (y · I (x + 1,
y)). The y-direction moment value (y · I
(X + 1, y)) is stored in the B latch (S1006),
By adding the values of the A latch and the B latch, the y direction moment values of the two adjacent pixels are added, and the addition result is stored in the A latch 402 via the register matrix 401 (S1008 to S101).
2). As a result, for each pixel 400 (x, y), the sum of the y-direction moment values for two pixels (y · I (x, y) + y ·
I (x + 1, y)) will be stored.

Next, i = 1 is set as an initial setting (S1).
014) After that, each of the arithmetic elements 400 (x, y) returns to S101.
8 to S1026, the stored addition result (y ·
I (x, y) + yI (x + 1, y)) and a pixel position (x + n, y) adjacent to the second pixel in the x direction (where n = 2 ⁱ , in this case, n = 2 ¹ = Arithmetic element 4 of 2)
00 (x + 2, y) and the addition result (y · I
(X + 2, y) + yI (x + 3, y)) is added to the transfer / addition process.

Subsequently, i is incremented by one (S
1028), by repeating the process of S1018～S1030, 4 pieces (n = ^{2 2)} next, eight (n ^{= 2} 3)
Neighbor, 16 (n = 2 ⁴ ) neighbors, 32 (n = 2 ⁵ ) neighbors, 6
4 (n = 2 ⁶ ) neighbors,..., And transfer / addition is repeated up to (N / 2) neighbors. As a result, the addition result y · I (0, y) + y · I of all y-direction moment values in each row
(1, y) + yI (2, y) + ... + yI (N-1,
y) is the operation element 400 (0, y) at the head of the row.
Is obtained.

Next, j = 0 is set as an initial setting (S1).
032) After that, in S1034 to S1040, each arithmetic element 400 (x, y) adds the addition result to a position (x, y + m) adjacent in the y direction (where m = 2 ^j , in this case, m = 2 ^j = 1) arithmetic element 400 (x, y + m)
(In this case, the addition result of 400 (x, y + 1)) is
Perform transfer / addition processing for addition. As a result, the sum (y 加 算 I (0, y) + y ・ I (1, y) + y ・ I) of the addition result for the two rows is stored in the arithmetic element 400 (0, y) at the head position of each row.
(2, y) + ... + yI (N-1, y)) + ((y +
1) · I (0, y + 1) + (y + 1) · I (1, y +
1) + (y + 1) .I (2, y + 1) +... + (Y + 1)
I (N-1, y + 1)) is obtained.

Subsequently, j is incremented by 1 (S
1044) and repeating the processing of S1046 to S1040, two (m = 2 ¹ ) next, four (m = 2 ² )
Next, 8 (m = 2 ³ ) neighbors, 16 (m = 2 ⁴ ) neighbors, 32
Next (m = 2 ⁵ ), 64 (m = 2 ⁶ ), ...
(N / 2) Repeat transfer / addition to the next. As a result, the addition result モ ー メ ン ト y · I (x,
y) is the operation element 40 at the head of the operation element array 40
0 (0, 0), and the sum calculation processing (S520) ends.

When the summation processing (S520) is completed,
The process proceeds to S530 (FIG. 16).

At S530, a pixel selection process for selecting the head pixel position (0, 0) is performed.

In the pixel selection processing, the same processing as the pixel selection processing described with reference to FIG. 12 is performed. as a result,
In S1114 to S1116, the top processing element 400
The multiplication result (1) is set only in (0, 0), and the multiplication result (0) is set in other arithmetic elements 400.

When the pixel selection processing (S530) ends,
The process moves to S532 (FIG. 16). In S532, the multiplication result obtained in the pixel selection processing (S530) is transferred from the register matrix 401 to the A latch 402. Next, the sum operation result finally obtained in the sum operation processing (S520) is also transferred from the register matrix 401 to the B latch 403 (S534). Then, A
In the LU 404, the value of the A latch 402 and the value of the B latch 403
Is multiplied (S536). As a result, the arithmetic element 400 at the start address (0, 0) has the sum operation result ΣΣ
As a result of multiplication of y · I (x, y) and (1), the y-direction total moment ΣΣy · I (x, y) is obtained. On the other hand, in another arithmetic element 400, zero (0) is obtained as a result of multiplication of the sum operation result and 0 (zero). Next, in S538, the multiplication result is stored in the register matrix 401, and in S540, the multiplication result is output to the output bus 155 from the output address “28” of the register matrix 401. As a result, all operation elements 40
The result of the multiplication of S536 at 0 will be output to the output bus 155. Here, the operation element 400 at the head position
Only (0,0) outputs the sum of moments in the y direction ΣΣy · I (x, y) as the multiplication result, and all the remaining arithmetic elements output zero (0) as the multiplication result. Therefore,
The output bus 155 provides a sum of moments in the y direction, which is an OR logical operation result of the operation results from all the operation elements 400.
y · I (x, y) is transferred to the control circuit 15.

When the x / y data bus 17 is bidirectional, in S540, the multiplication result is expressed as x / y data bus.
The data may be output to the control circuit 15 via the y data bus 17. Specifically, in S540, the multiplication result is stored in the register matrix 401 at the address “30” or “31”.
Thus, the data is output to the x / y data bus 17. CPU 150
Is the sum of moments in the y-direction ・ y · I via the data line 170 _{x = 0} corresponding to the arithmetic element 400 (0,0).
(X, y).

Next, in S550, the CPU 150
Is the sum of the received y-direction moments ΣΣy · I
By dividing (x, y) by the total image intensity ΣΣI (x, y), the x coordinate of the center of gravity is obtained.

As described above, the calculation of the center of gravity is performed by the parallel operation mechanism 14 and the control circuit 15 in a shared manner. That is, the parallel operation mechanism 14 performs the sum operation and the moment operation with high parallelism, and the control circuit 15 performs the division based on the moment operation result and the sum operation result. Is to be asked.

The parallel operation method of the present system is a method called SIMD in which the same operation is performed in all operation elements. However, in some cases, a different operation is performed for each pixel, or a special operation is performed only for a certain pixel. Can be performed, more flexible processing becomes possible. Here, according to the present embodiment, by using the x / y data bus 17, it is possible to cause each arithmetic element 400 to perform a different arithmetic operation. x / y data bus 1
This is because arithmetic control data can be transferred to each arithmetic element 400 by using.

For example, when it is desired to perform a special operation only on a certain pixel, the target pixel (for example, (x1, y1)) is set by the x data line 170x and the y data line 180y.
Is transferred to the x data line 170x1 and the y data line 180y1 and 0 is transferred to the other, and this value is multiplied by the value held by the arithmetic element 400, and then the image processing operation is performed. , Image processing operation is performed only by the operation element 400 at the position (x1, y1).

More specifically, the image processing step S110 in FIG.
In FIG. 17, a desired position calculation process as shown in FIG.
0) can be performed.

When the desired position calculation processing (S600) starts, the image data I of each pixel of the input image D
(X, y) is already transferred from the transfer shift register 410 to the register matrix 401 of each arithmetic element 400 (x, y) in S104 (FIG. 8) and stored in a certain area of the register matrix 401. ing.

In the desired position calculation processing (S600),
First, in S610, a desired pixel position (x1, y
A pixel selection process for selecting 1) is performed. In the pixel selection processing (S610), the desired pixel position (x1,
The pixel selection process described with reference to FIG. 12 is performed so as to select y1).

Specifically, the CPU 150 determines in step S1102
In steps S1104 to S1104, the data (1) is transferred to the x-direction data line 170x (x = x1) of the target x address x1, and all the remaining x-direction data lines 170x (x ≠
The data (0) is transferred to x1), and the input data of the register address “31” (the transfer data from the x data line 170x) is stored in all the arithmetic elements 400. In this way, among all the operation elements 400, the data (1) is set only in the operation element 400 (x1, y) (0 ≦ y ≦ N−1) having the x address x1, and the data (1) is set in the other operation elements 400. Set 0).

Next, in S1108 to S1110,
Y-direction data line 180y of target y address y1
(Y = y1), and transfer data (1) to all remaining y
Data (0) on the direction data line 180y (y ≠ x1)
To transfer. That is, the y-direction data line 180y
X-direction data line 17 connected to (y = y1)
0x (x = y1) via y-direction data line 180y
(Y = y1) and transfer the data (1) to all the remaining x
The data (0) is transferred to the y-direction data line 180y (y ≠ y1) via the direction data line 170x (x ≠ y1). Further, the input data of the register address “30” (y data line 170 y
(Transfer data from the server). In this way, of all the operation elements 400, the operation element 400 having the y address y1
Data (1) is set only in (x, y1) (0 ≦ x ≦ N−1), and data (0) is set in other arithmetic elements 400.

Next, in each of the arithmetic elements 400 (x, y), the transfer data from the x-direction data line 170x is multiplied by the transfer data from the y-direction data line 180y (S1114). The result is stored in the matrix 401 (S1116), and the pixel selection processing (S610) ends. As a result, the multiplication result is 1 only in the arithmetic element 400 (x1, y1) of the desired address (x1, y1), and the multiplication result is 0 in the other arithmetic elements 400.

When the selection processing (S610) is completed, S6
The process proceeds to FIG. 12 (FIG. 17). In S612, the multiplication result of the above-described pixel selection processing (S610) is transferred from the register matrix 401 to the A latch 402. Next, target data to be subjected to the calculation (for example, image data I
(X, y)) is transferred from the register matrix 401 to the B latch 403 (S614), and the value of the A latch 402 and the value of the B latch 403 are multiplied (S616). As a result, the arithmetic element 400 at the target pixel position (x1, y1)
, The target data itself is obtained, and the other arithmetic elements 400 obtain zero (0) data. The multiplication result is stored in the register matrix 401 (S61
8) After that, in S620, desired arithmetic processing is performed on the multiplication result. More specifically, the multiplication result of S616 is stored in the register
The data is transferred to the latch 403, and a predetermined arithmetic processing is performed by the ALU 404. As a result, the target pixel position (x1, y1)
The arithmetic processing is performed only on the target data, and the arithmetic processing is performed on the zero (0) data at positions other than the pixel position. The calculation result is output to the control circuit 15 via the output bus 155. As the operation performed in S620, various operation processes such as an edge extraction process can be performed.

In S620, no operation is performed.
The multiplication result obtained in 16 may be output to the control circuit 15 as it is. That is, output from the output address “28” via the output bus 155 or address “30”
Alternatively, the data may be output from “31” via the x / y data bus 17. By doing so, the desired address (x
Only the desired data (for example, image data I (x, y)) obtained in (1, y1) can be output to the control circuit 15.

The desired position calculation processing (S600)
Is performed while selecting the individual arithmetic elements (pixels) while changing the contents of the arithmetic processing (S620), the individual arithmetic elements can execute different arithmetic processing.

Further, in the pixel selection processing (S610),
Instead of selecting only a single pixel, a plurality of pixels may be selected. For example, the data (1) is transferred to the x-direction data line 170x and the y-direction data line 180y corresponding to the x address and the y address of the plurality of pixels,
Data (0) may be transferred to other data lines. S111 using only a plurality of selected pixels
4 (FIG. 12) becomes 1, and as a result, S61
6 (FIG. 17), the target data is obtained as a result of the multiplication. Therefore, in S620, a desired operation on target data can be performed in the selected pixels.

Further, in the pixel selection processing (S610),
All pixels belonging to one column or row may be selected.

In order to select all pixels belonging to one column, in the pixel selection processing (S610), only steps S1102 to S1104 may be performed as shown in FIG. In this case, the CPU 150 determines in S1102
Then, data (1) is transferred to the x-direction data line 170x corresponding to the x address of the column to be selected, and data (0) is transferred to the other data lines. In S1104, each arithmetic element 400 registers the register address “3”.
By storing the data from "1", the transfer data from the x-direction data line 170x is stored. As a result, 1 is set to all the pixels in the selected column, and 0 is set to the pixels in the other columns. By transferring this setting data to the A latch in S612, S6
In 16 (FIG. 17), the target data is obtained as a multiplication result for all the pixels in the selected column. Therefore, in S620, a desired operation on target data can be performed for all pixels in the selected column.

In order to select all pixels belonging to one row, in the pixel selection processing (S610), only steps S1108 to S1110 may be performed as shown in FIG. In this case, the CPU 150
At 108, data (1) is transferred to the y-direction data line 180y corresponding to the y address of the row to be selected, and data (0) is transferred to the other data lines. Each of the arithmetic elements 400 stores the data from the register address “30” in S1110, so that y
The transfer data from the direction data line 180y is stored. As a result, 1 is set to all pixels in the selected row,
0 is set to the pixels in the other rows. S612
In step S616 (FIG. 17), the target data is obtained as a multiplication result for all the pixels in the selected row. Therefore, S
At 620, a desired operation on the target data can be performed for all pixels in the selected row.

Further, by using the x / y data bus 17, after performing a predetermined operation in all the operation elements 400, only the contents (operation result) of the register matrix 401 of one operation element 400 are selectively selected. It is also possible to take it out.

More specifically, the image processing step S110 in FIG.
In FIG. 20, an operation-extraction process as shown in FIG. 20 (S650)
It is possible to do.

When the operation-extraction process (S650) starts, the image data I of each pixel of the input image D
(X, y) is already transferred from the transfer shift register 410 to the register matrix 401 of each arithmetic element 400 (x, y) in S104 (FIG. 8) and stored in a certain area of the register matrix 401. ing.

In the calculation-extraction process (S650), first, in S660, the respective calculation elements 400 are caused to perform a desired calculation on the image data I (x, y). As the desired calculation, various calculation processes such as an edge extraction process can be considered.

Next, a pixel selection process (S680) for selecting a target pixel position (x1, y1) is performed. In the pixel selection processing (S680), the pixel selection processing described with reference to FIG. 12 is performed on the target pixel (x1, y1). As a result, (1) is set as the multiplication result of S1114 only in the target operation element 400 (x1, y1), and (0) is set as the multiplication result of S1114 in the other operation elements 400.

When the selection processing (S680) is completed, S6
The process moves to 82 (FIG. 20). In S682, the multiplication result of the pixel selection processing (S680) is transferred from the register matrix 401 to the A latch 402. Next, the target data to be extracted (the operation result in S660) is transferred from the register matrix 401 to the B latch 403 (S68).
4) The value of the A latch 402 is multiplied by the value of the B latch 403 (S686). As a result, the target pixel position (x
The operation result data itself is obtained only by the operation element 400 of (1, y1), and zero (0) data is obtained by the other operation elements 400. After the multiplication result is stored in the register matrix 401 (S688), S690
At the output address "28" to the output bus 155. As a result of the multiplication result of S686 being output to the output bus 15 from all the operation elements 400, the target pixel 400 (x
The calculation result in (1, y1) is output to the control circuit 15. At S690, the address “3”
The data may be output to the x / y data bus 17 via “0” or “31”. The control circuit 15 obtains an x data line 170x (x = x1 or y1) corresponding to the coordinates x1 or y1 of the target pixel 400 (x1, y1).
Operation results can be received.

Further, in the pixel selection processing (S680),
Instead of selecting only a single pixel, a plurality of pixels may be selected. For example, the data (1) is transferred to the x-direction data line 170x and the y-direction data line 180y corresponding to the x address and the y address of the plurality of pixels,
Data (0) may be transferred to other data lines. S111 using only a plurality of selected pixels
4 (FIG. 12) becomes 1, and as a result, S68
6 (FIG. 20), the operation result data itself is obtained as the multiplication result. Therefore, in S690, the operation result data is output from the selected plurality of pixels.

Here, in the pixel selection processing (S680),
All pixels belonging to one column or row may be selected.

That is, in the pixel selection processing (S680), only the steps of S1102 to S1104 may be executed as shown in FIG. In this case, the CPU
150 transfers the data (1) to the x-direction data line 170x corresponding to the x address of the column to be selected in S1102, and transfers the data (0) to the other data lines. Each arithmetic element 400 stores transfer data from the x-direction data line 170x by storing data from the register address "31".
As a result, 1 is set to all the pixels in the selected column, and 0 is set to the pixels in the other columns. By transferring the setting data to the A latch in S682, in S686 (FIG. 20), the operation result data itself is obtained as a multiplication result for all the pixels in the selected column. Therefore, in S690, the operation result data is output from all the pixels in the selected column. In this case, each arithmetic element 400 is connected to a different y data line 180y. Therefore, each arithmetic element 400 only needs to output the operation result data via the corresponding y data line 180y via its register address "30". The control circuit 15 communicates via a corresponding x data line 170x to which each y data line 180y is connected,
Operation result data from each operation element 400 can be obtained.

Alternatively, in the pixel selection process (S680), only steps S1108 to S1110 may be executed as shown in FIG. In this case, the CPU
150 transfers the data (1) to the y-direction data line 180y corresponding to the y address of the row to be selected in S1108, and transfers the data (0) to the other data lines. Each arithmetic element 400 stores the transfer data from the y-direction data line 180y by storing the data from the register address “30”.
As a result, 1 is set to all the pixels in the selected row, and 0 is set to the pixels in the other rows. By transferring this setting data to the A latch in S682, in S686 (FIG. 20), the operation result data itself is obtained as a multiplication result for all the pixels in the selected row. Therefore, in S690, the operation result data is output to all the pixels in the selected row. In this case, each arithmetic element 400 has a different x data line 170x
It is connected to the. Therefore, each arithmetic element 400
The operation result data may be output via the corresponding x data line 170x via the register address "31". The control circuit 15 can acquire operation result data from the corresponding operation element 400 via each x data line 170x.

Furthermore, if a bidirectional bus is used as the x / y data bus 17, for example, a certain search image (m1 ×
When it is desired to search for (m2 pixels) by parallel operation, the control device 15 can quickly confirm the position where the coincidence signal is obtained through the x / y data bus 17.

A specific example of the image search will be described below.

In this search, when the search pattern P is the input image D
(= I (x, y), where 0 ≦ x ≦ N−1, 0 ≦ y ≦
This is an operation to find out whether the position is within N-1) or, if any, at which position. There are many research examples of matching algorithms. Here, the algorithm that considers the same image when the distance ERROR (p, q) between images represented by the following simplest formula is smaller than a certain threshold value is used. Shall be used. Here, (p, q) is the position of the reference pixel (x, y) in the image D.

[0202]

(Equation 2)

The search processing based on this algorithm (S7
00) is shown in FIG. 21, and the flow of data processing will be described below with reference to FIG.

Here, this search processing (S700) is also executed in the image processing step S110 of FIG. Further, each pixel (x, y) is set as a reference position (p, q) for image search. Further, image data P (i, j) of the search image P (0 ≦ i ≦ m1-1, 0 ≦ j ≦ m2
-1) is stored in the memory 151 of the control circuit 15.

When the search processing (S700) starts, the image data I (x, y) of each pixel of the input image D
(Hereinafter, I (p, q)) has already been transferred from the transfer shift register 410 to each arithmetic element 400 (x, y) (hereinafter, 400 (p, q)) in S104 (FIG. 8). The data is transferred to the register matrix 401 and stored in a certain area of the register matrix 401.

In the search processing (S700), the CPU 150
First, in step S702, an initial state is set. Specifically, the head position (0, 0) is set at the matching detection position (i, j) in the search pattern P, and the calculation result to be stored in the register matrix 401 of each arithmetic element 400 (p, q) Er (p, q) is reset.

In step S703, the current detection position (i, j) in the search pattern P (here, the head position (0,
0)) is read out from the memory 151, and is read via the x / y data bus 17 to each of the arithmetic elements 4 (i, j).
Transfer to 00.

In step S704, in each of the arithmetic elements 400 (p, q), the register matrix 40
1 of the pixel stored in a certain area
The absolute value of the difference between (p, q) and the image data P (i, j) at the matching detection position of the search pattern is obtained, and Er (p,
q). Here, specifically, the image data I
(P, q) and the image data P (0,
0) and the absolute value of the difference
One other area is allocated and stored as Er (p, q).

[0209] In step S705, the CPU 150
The detection position (i, j) is the final position (m1-1, m2-1)
Is determined. Here, since the detection position (i, j) is still the head position (0, 0), it has not reached the final position (No in Step 705), and the process proceeds to Step S706. In step S706, i
In the case of ≠ m1, only the value of i is increased by 1, and i = m1−
If it is 1, i is reset to 0 on the assumption that it has reached the end in the x direction, and the value of j is increased by 1. Here, i = 0, j =
Since it is 0, it is updated to i = 1 and j = 0. Then, in step S707, the image data at the position (p + i, q + j), here, the image data I (p + 1, q) at the position (p + 1, q) is transferred to the register matrix 401 of the arithmetic element 400 (p, q). I do. Specifically, using the neighborhood transfer function of the register matrix 401,
The image data value I (p + 1, q) stored in the adjacent pixel 400 (p + 1, q) is converted to the pixel 400 (p, q).
This transfer is performed by transferring to an empty area.

[0210] When the transfer is completed, the process returns to step S703, and the CPU 150 returns the image data P (i, j) at the current detection position (i, j) (here, position (1, 0)) in the search pattern P. Is read from the memory 151 and transferred to each of the arithmetic elements 400 (p, q) via the x / y data bus 17. In step S704, each arithmetic element 4
00 (p, q) is the image data I (p + 1, q) of the adjacent pixel currently stored in the register matrix 401
And the absolute value of the difference between the image data P (i, j) at the current matching detection position of the search pattern and Er (p, q)
Is added to. The detection position (i, j) is the final position (m1-
1, m2-1), (N at S705)
o), the process proceeds to S706 and the detection position (i, j) is updated.

This processing (steps S703 to S70)
7), the detection position (i, j) is the final position (m1-1, m
Repeat until 2-1) is reached.

As described above, by repeatedly performing the addition in step S704, ERROR (p, q) can be obtained in each arithmetic element 400 (p, q).

The transfer in step S707 may be performed by using the transfer function of the register matrix 401 and sequentially transferring the pixels to adjacent pixels in the x and y directions.

When the detected position reaches the final position (m1, m2) and ERROR (p, q) is obtained, step S705 is performed.
The process moves from (Yes in S705) to step S708. In step S708, the CPU 150 sets the threshold value E _th , and in step S709, the set threshold value E _{th
The th} data is transferred to each arithmetic element 400 via the x / y data bus 17.

In step S710, each arithmetic element 400 (p, q) compares the threshold value E _th with the obtained ERROR (p, q), that is, Er (p, q). Specifically, each arithmetic element 400 calculates ERROR (p, q) _{-threshold Eth} , and outputs the resulting sign bit (positive or negative sign) as a comparison result. That is, Er (p,
If q) is equal to or smaller than the threshold value E _th , the process shifts to step S711. In step S711, 1 is output via the register address “31” at the first timing, and 1 is output via the register address “30” at the second timing. On the other hand, if Er (p, q) is larger than the threshold value E _th , the process moves to step S712. Step S712
Then, at the first timing, the register address "3
0 is output via "1", and at the second timing, 0 is output via the register address "30". Thus, each arithmetic element 400 converts these output data into x / y
Output to the data bus 17. The CPU 150 calculates these x
By taking the total sum of the output signals from the / y data bus 17, the number of arithmetic elements 400 that output 1 is counted. That is, at the first timing, the x data line 17 to which the arithmetic element 400 that has output 1 is connected is connected.
1 appears at 0x. At the second timing, the x data line 170x (x = x) connected to the y data line 180y to which the arithmetic element 400 that has output 1 is connected is connected.
1 appears in y). Therefore, by taking the sum of the output signals of all the x data lines 170x at the first and second timings, it is possible to count the number of operation elements 400 that output 1.

In step S713, the CPU 150
The number of operation elements 400 that output 1 is determined, and if the number is 0, the process proceeds to step S714 to output a determination result indicating that there is no matching image.

When the number of arithmetic elements 400 that output 1 is one, one output signal is obtained only at a single data line 170x at the first timing, and at the second timing, Also a single data line 170 connected to a single data line 180y.
One output signal is obtained only for x (x = y). Therefore, the CPU 150 determines in S715 that the output signal line 170 from which one output signal was obtained at the first timing.
On the basis of the position x of x, the x coordinate p of the arithmetic element 400 that has output 1 is obtained. Further, the CPU 150 outputs the output signal line 170x at which one output signal is obtained at the second timing.
Of the arithmetic element 400 that has output 1 based on the position x of
Find the coordinates q. In this way, the CPU 150 obtains the position data (p, q) of the arithmetic element 400 that has output 1.

Note that in S715, the x / y data bus 1
7, an output bus 155 may be used. That is, each operation element 400 may be multiplied by the output (0 or 1) as the determination result in S710 and the position data (p, q), and the multiplication result may be output to the output bus 155. . In this case, the pixel that has output the output signal 1 as the determination result of S710 (matching position pixel)
Only outputs its position data (p, q). Other pixels output (0) which is a result of multiplication of the output signal (0) and the position data (p, q). Therefore, only the position data (p, q) of the matching position is output bus 15
5 to the control circuit 15. According to such a method, not only the matching position data (p, q) but also other matching calculation results (for example, the absolute value of the difference between the input image D and the search pattern P) are controlled by the control circuit 15.
Can be transferred to

On the other hand, if the number of arithmetic elements 400 that output 1 is two or more, the threshold value E _th is determined in step S716.
Is returned to step S709, and the threshold _Eth is reduced until the number of arithmetic elements 400 that output 1 becomes one, thereby narrowing down.

The high-speed image processing apparatus 1 of the present embodiment described above
According to 0, in the image processing step S110, in addition to the above-described image processing (FIGS. 9 to 21), various image processing (for example, edge extraction, smoothing, thinning, convolution, correlation, and mask processing) It can be performed. According to the present embodiment, these image processing operations can be performed at very high speed by completely parallel processing. Therefore, the conventional image processing apparatus can be applied to fields such as FA robot control, which are limited due to the low processing speed and transfer speed.

The object of the present embodiment is an image processing system having practical high speed and sufficient resolution. The robot control in the FA system requires a resolution in which 128 × 128 or more light receiving elements 120 are arranged. According to the present embodiment, the light receiving element array 11 and the parallel processing mechanism 14 can be separated and the degree of integration of each can be increased, so that this resolution can be sufficiently realized. Further, as a guide of the processing speed, the speed of the robot actuator (1 to 10 milliseconds) is required. In the present embodiment, the processing speed is determined by the A / D converter 210
Although it depends on the D conversion processing speed, it is possible to sufficiently increase the speed.

As described above, the A / D of this embodiment is
The converter 210 performs A / D conversion from the most significant bit.
Therefore, when the conversion is performed to the desired number of bits, the reset signal R is transmitted, and the A / D conversion of the next optical signal is started, whereby the gradation of the A / D conversion can be changed.
This makes it possible to perform complicated processing at higher speed.

However, when the bit length output from the A / D converter is made variable, the transfer shift register needs to adjust the bit length of the input data to a fixed length. This is because, for example, a shift register having a fixed length of 8 bits and the number of pixels in a row (N) is used for a transfer shift register line when the normal data length is 8 bits.
Each shift register divided into 8 bits functions as a transfer shift register for each pixel corresponding to each position. Therefore, if the bit length is not adjusted to 8 bits, the image data will not be correctly transferred to the transfer shift register at the corresponding position. For this reason, the data is transferred correctly by adding a dummy signal at the time of sending to the transfer shift register so that the total becomes 8 bits.

As described above, the high-speed image processing apparatus 10 of the present embodiment includes the parallel processing mechanism 14 including a plurality of arithmetic elements 400 arranged in a plurality of rows and columns. The parallel processing mechanism 14 is provided with an x / y data bus 17 for performing data transfer with the arithmetic element 400. The x / y data bus 17 includes a plurality of column direction data transfer data lines 170 corresponding to each column, and a plurality of row direction data transfer data lines 180 corresponding to each row. The arithmetic element 400 can perform image processing between neighboring pixels at high speed by parallel processing, and can also perform arithmetic processing that requires external data transfer at high speed by using the x / y data bus 17. Can be. Here, each column-direction data transfer data line 170 is connected to one corresponding row-direction data transfer data line 180, and the column-direction data transfer data line and the row-direction data transfer data line are shared. Used for data transfer.

As described above, in the present embodiment, when performing an operation that requires external data, data transfer (transmission / reception) can be performed more efficiently than the x / y data bus 17, so that a high-speed operation can be performed. It is possible. Here, the x / y data bus 17 is connected to the arithmetic elements 4 arranged in a plurality of rows and columns.
In correspondence with 00, a plurality of x data lines 170 and a plurality of y data lines 180 are provided. For example, when the number of pixels is 128 × 128 (N = 128), 128 x data lines and 128 y data lines are provided. In this case, it is necessary to connect these 256 data lines to the control circuit 15. Here, in order to construct a chip having the best miniaturization, it is necessary to connect the input / output pins of these data lines to the control circuit 15.
However, providing a large number of input / output pins not only increases the size of the chip, but also increases the manufacturing cost and reduces the mounting yield. Therefore, in the present embodiment, in order to realize the x / y data bus 17 compactly, one of each of the x data line 170 and the y data line 180 is connected on a circuit inside the x / y data bus 17 to perform communication. The number of communication lines with external devices (the number of input / output pins) is greatly reduced by sharing the lines. In particular, as in the present embodiment, when the arithmetic element 400 performs the SIMD type operation, the input / output of the x data line 170 (access to the register address “31”) and the input / output of the y data line 180 (register address) are performed. Access to “30”) and x data line 170 and y
Even if the data line 180 is connected to the outside by a common signal line (in this case, the x data line 170), the data to be transferred via the x data line 170 and the y data line 180 can be accurately identified, Data transfer can be performed reliably.

The high-speed image processing apparatus 10 according to the present embodiment further includes a one-to-one
A light-receiving element array 11 composed of a plurality of light-receiving elements 120 corresponding to
A / D converter array 13 corresponding to / D converter 210
And is connected to the parallel processing mechanism 14.

The arithmetic element 400, which has a one-to-one correspondence with the light receiving element 120, performs image processing of each pixel generated by the light receiving element 120 in parallel so that image processing operation between neighboring pixels can be performed at high speed. Can be done with Further, since the A / D converter 210 is provided for each row,
As compared with the case where the A / D converter 210 is provided for each light receiving element 120, the number of transmission lines between the light receiving element 120 and the arithmetic element 400 can be reduced, and the light receiving element 120 and the arithmetic element 400
Can be easily manufactured and arranged separately. For this reason, both can optimize the degree of integration, and the high-speed image processing apparatus 10 having a large number of pixels can be easily manufactured.

Further, in the present embodiment, since the transfer shift register 410 is provided corresponding to the arithmetic element 400, the arithmetic processing can be performed independently of the transfer processing, and the arithmetic processing and the transfer processing can be performed efficiently. Can be. Further, since the transfer processing and the arithmetic processing can be performed in parallel, the waiting time of each processing can be reduced, and higher-speed image processing can be performed. That is, by using a transfer shift register when transferring data from the A / D converter to the arithmetic element, it is possible to realize a function that can execute arithmetic processing and transfer independently.
Real-time processing is possible.

Hereinafter, a high-speed image processing apparatus according to a second embodiment of the present invention will be described with reference to FIG.

In the high-speed image processing apparatus 10 according to the second embodiment of the present invention, the control circuit 15 and the x / y data bus 1
7, an x / y data bus data buffer 19 is provided. By providing the data buffer 19 in this manner, a large amount of data transfer between the control circuit 15 and the x / y data bus 17 can be efficiently performed. in this case,
The x / y data bus 17 and the data buffer 19 may be formed on the same substrate as the parallel processing mechanism 14, or may be formed on another substrate. If integrated as one, it becomes easier to increase the data transfer speed with the arithmetic element 400. Also, the N input / output units 170e of the x / y data bus 17 are connected to the x / y data bus data buffer 19, and the single data buffer 19 is commonly used for 2N data lines 170 and 180. Therefore, the entire high-speed image processing apparatus 10 can be downsized.

In the first embodiment, when performing the center of gravity calculation, the address data storage area 15
4 stores the N-bit address data shown in FIG. However, in the case of this embodiment, FIG.
As shown in FIG. 2, an N-bit width memory 190 is connected to the x / y data bus data buffer 19, and the memory contents shown in FIG. In this case, S402 to S410 in FIG. 13 and S50 in FIG.
In steps S2 to S510, memory addresses (addresses 0 to (m-1)) in the memory 190 are sequentially specified, and the contents of the memory are transferred to the x / y data bus 17.
The x address data and the y address data can be sequentially transferred to each arithmetic element from the least significant bit.

As described above, the data in the memory 190 is represented by x
Since the address data and the y-address data can be used in common, the size of the entire device can be reduced.

The memory address is changed from address 0 to (m-
1) A counter (not shown) for automatically designating the address up to the address may be connected to the memory 190. According to such a configuration, in S402 to S410 in FIG. 13 and S502 to S510 in FIG. 16, the memory addresses (addresses 0 to (m-1)) in the memory 190 are automatically specified in order, so that The x address data and the y address data corresponding to the operation elements are automatically transferred from the least significant bit, and the moment operation can be performed at high speed.

Hereinafter, a high-speed image processing apparatus according to a third embodiment of the present invention will be described with reference to FIGS.

In the high-speed image processing apparatus 10 according to the third embodiment of the present invention, as shown in FIG. 23, instead of the x / y data bus data buffer 19, an address selection counter is used as an address data generation counter. 20 are provided. According to the address selection counter 20, an operation of sequentially selecting each column (each row) can be automatically performed. Further, by connecting the N input / output units 170e of the x / y data bus 17 to the address selection counter 20, a single address selection counter 20 is commonly used for 2N data lines 170 and 180. By using this, the entire high-speed image processing apparatus 10 can be downsized.

The address selection counter 20 is, for example,
It comprises an N-bit shift register 200.
Each bit of the shift register 200 corresponds to
x data line 170x. Where
The shift register 200 stores the data of each bit in the adjacent bit.
It has the function of feeding forward. For example, if N = 8,
As shown in FIG. 24, the shift register 200
50 to count the clocks sequentially generated by
Then, the data “1” is sequentially sent to the next bit. did
Therefore, data "1" is first stored in x data line 170.₇
(And the connected y data line 180₇)
And then the data line 170₆(180₆), 170
₅(180₅) ...
170 ₀(180₀) And then again
170₇(180₇).

A shift register 200 having such a function
By using, the operation of selecting all the arithmetic elements in one column (or one row) can be performed while automatically changing the selected column (or row) in order.

For example, by repeatedly performing the operation of selecting all the arithmetic elements in one column described with reference to FIGS. 17 and 18 while sequentially transmitting data in the shift register 200, the columns to be selected are sequentially shifted. However, it is possible to cause the operation elements belonging to the column to perform a desired operation. Specifically, when the desired position calculation process (S600) in FIG. 17 is repeatedly executed, the data “1” in the shift register 200 is automatically forwarded, so that the pixel selection process (S600) is performed.
610: Data “1” in S1102 in FIG. 18)
Can be transferred to the column X1 while the transfer destination X1 is sequentially shifted.

Similarly, the operation of selecting all the arithmetic elements in one row described with reference to FIGS. 17 and 19 is repeatedly performed while sequentially transmitting data in shift register 200, thereby sequentially shifting the selected row. It is also possible to cause the operation elements belonging to the row to perform a desired operation. Specifically, when the desired position calculation process (S600) in FIG. 17 is repeatedly executed, the data “1” in the shift register 200 is automatically forwarded, so that the pixel selection process (S600) is performed.
610: Data “1” in S1108 in FIG. 19)
To the row Y1 can be performed while shifting the transfer destination Y1 in order.

Similarly, the operation of selecting all the arithmetic elements in one column described with reference to FIGS. 20 and 18 is repeatedly performed while sequentially transmitting data in shift register 200, thereby sequentially shifting the selected column. In this way, the operation element belonging to the column can output the operation result. Specifically, the calculation-extraction process of FIG. 20 (S650)
Is repeatedly executed, the data “1” in the shift register 200 is automatically forwarded, so that the transfer of the data “1” to the column X1 in S1102 in the pixel selection processing (S680: FIG. 18) is performed. This can be performed while shifting the destination X1 in order.

Similarly, the operation of selecting all the arithmetic elements in one row described with reference to FIGS. 20 and 19 is repeatedly performed while sequentially feeding data in shift register 200, so that the rows to be selected are sequentially shifted. It is also possible to cause the operation elements belonging to the row to output the operation result. Specifically, the calculation-extraction process of FIG. 20 (S650)
Is repeated, the data "1" in the shift register 200 is automatically forwarded, so that the transfer of the data "1" to the row Y1 in S1108 in the pixel selection processing (S680: FIG. 19) is performed. This can be performed while shifting the tip Y1 in order.

As described above, since the data in the shift register 200 can be commonly used as the column selection and row selection address data, high-speed processing can be achieved while reducing the size of the entire device. .

The high-speed image processing apparatus according to the present invention is not limited to the above-described embodiment, and various modifications and improvements can be made within the scope described in the claims.

For example, in the above-described embodiment, the input / output pin 170e is formed on the x data line 170 among the x data line 170 and the y data line 180 constituting the x / y data bus 17, and 170e was connected to the control circuit 15. However, an input / output pin may be formed on the y data line 180, and the input / output pin may be connected to the control circuit 15.

Further, in the above-described embodiment, in order to obtain the sum of the image intensity and the moment in the x / y direction, FIG.
Is performed, a circuit for calculating the total sum of outputs from the arithmetic elements 400 may be added to the output bus 155, and the sum may be calculated by the circuit.

In the above embodiment, the A / D converter 210 includes the charge amplifier 221. However, the A / D converter 210 and the charge amplifier 221 are provided separately, and As described above, the N charge amplifiers 22
1 is connected to the light receiving element array 11, and the A / D converter 210
The / D converter array 13 may be provided between the amplifier array 12 and the parallel processing mechanism 14. In this case, each amplifier 221 in the amplifier array 12 sequentially converts charges output from a total of N light receiving elements 120 on the corresponding row 110 of the light receiving element array 11 into a voltage signal, and obtains an analog signal. The voltage signal is output to a corresponding A / D converter 210 in the A / D converter array 13. The A / D converter 210 sequentially A / D converts the analog voltage signal from the charge amplifier 221 and supplies the analog voltage signal to the parallel processing mechanism 14.

Furthermore, the light receiving element 120 and the A / D converter 2
The configuration of 10 is not limited to the configuration described in the above embodiment.

In the above embodiment, the transfer of data from the A / D converter 210 to the arithmetic element 400 is performed by the transfer shift register 410. However, the transfer shift register 410 may not be provided. That is, as shown in FIG. 26, each A / D converter 210 is
4, among the arithmetic elements 400 (0, 0,
It may be connected to the register matrix 401 of y). In this case, the pixel data I (x, y) output from the A / D converter 210 in each row includes the arithmetic elements 400 (0, 0) adjacent in the x direction up to the corresponding arithmetic element 400 (x, y). The transfer is performed by sequentially performing transfer between the register matrices 401 of y) to 400 (x, y).

Further, in the above-described embodiment, the parallel processing mechanism 14 is connected to the light receiving element array 11 and the A / D conversion array 13 which are image reading units. However, the parallel processing mechanism 14 need not be connected to such an image reading unit. That is, the parallel processing mechanism 14 can be used as a general-purpose high-speed image processing arithmetic unit. Specifically, the parallel processing mechanism 14 can be connected to an arbitrary image data input device, and can input an arbitrary digital signal image to the plurality of arithmetic elements 400. Then, by connecting the x / y data bus 17 provided in the parallel processing mechanism 14 to an arbitrary control circuit, desired data can be exchanged with the control circuit.

[0250]

According to the first aspect of the present invention, since the data lines in the row direction and the data lines in the column direction are arranged so as to be commonly used, they are suitable for integration by a semiconductor. Flexible image processing capability can be achieved while maintaining a simple architecture.

According to the high-speed image processing apparatus of the present invention, since the light receiving element is provided in one-to-one correspondence with the arithmetic element, the arithmetic element is an image corresponding to the output image signal obtained by the light receiving element. The arithmetic processing can be performed at high speed by parallel processing. Further, by providing the A / D converter for each row, the number of transmission paths can be reduced.

According to the high-speed image processing apparatus of the third aspect, the provision of the data buffer enables high-speed data transfer even if the data transfer speed between the control circuit and the data transfer bus is low. If the parallel processing mechanism, the data transfer bus, and the data buffer are integrated, the speed of data transfer from the arithmetic element to the data buffer can be relatively easily increased.

According to the high-speed image processing apparatus of the fourth aspect, by providing the address data generation counter, it is possible to automatically generate the address data for selecting and controlling the operation element. Control speed can be relatively easily increased.

According to the high-speed image processing apparatus of the fifth aspect, both the transfer processing and the arithmetic processing can be performed efficiently with a reduced waiting time, and the overall processing time can be shortened. As a result, a pipeline-like operation becomes possible, and high-speed image processing, in particular, real-time processing becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a high-speed image processing device according to a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a high-speed image processing device according to the embodiment of FIG. 1;

FIG. 3 is a configuration block diagram of a control circuit included in the high-speed image processing device according to the embodiment of FIG. 1;

FIG. 4 is a circuit configuration diagram of a light receiving element array and an A / D converter array included in the high-speed image processing device according to the embodiment of FIG.

5 is a detailed circuit configuration diagram of an integration circuit provided in the A / D converter array of FIG. 4;

FIG. 6 is a block diagram of an arithmetic element and a transfer shift register included in the high-speed image processing device according to the embodiment of FIG. 1;

FIG. 7 is an explanatory diagram showing a connection state between x data lines and y data lines of an x / y data bus 17 provided in the high-speed image processing device according to the embodiment of FIG. 1;

FIG. 8 is an operation flowchart of the high-speed image processing device according to the embodiment of FIG. 1;

9 is an operation flowchart of a center-of-gravity calculation processing step as an example of step S110 in FIG. 8;

FIG. 10 is an operation flowchart of an image intensity sum calculating process in the centroid calculating process of FIG. 9;

11 is an operation flowchart of a sum calculation processing step of the image intensity sum calculation processing step of FIG. 10;

FIG. 12 is an operation flowchart of a pixel selection processing step of the image intensity sum calculation processing step of FIG. 10;

13 is an operation flowchart of an x-direction coordinate calculation processing step of the centroid calculation processing step of FIG. 9;

FIG. 14 shows an address data storage area 15 of the memory 151.
FIG. 4 is an explanatory diagram showing an example of memory addresses and memory contents inside 4;

FIG. 15 is an explanatory diagram showing a state in which a moment is calculated while carrying one bit at a time.

FIG. 16 is an operation flowchart of a y-direction coordinate calculation processing step of the center-of-gravity calculation processing step of FIG. 9;

FIG. 17 is an operation flowchart of a desired position calculation processing step as an example of step S110 in FIG. 8;

FIG. 18 is a block diagram illustrating a method of selecting all pixels in a desired column;
FIG. 11 is an operation flowchart of a pixel selection processing step in which the pixel selection processing step of FIG.

FIG. 19 is a diagram showing a state in which all pixels in a desired row are selected.
FIG. 11 is an operation flowchart of a pixel selection processing step in which the pixel selection processing step of FIG.

20 is a calculation as an example of step S110 in FIG.
FIG. 5 is an operation flowchart of an extraction processing step.

FIG. 21 is an operation flowchart of an image search processing step as an example of step S110 in FIG. 8;

FIG. 22 is a block diagram showing a high-speed image processing device according to a second embodiment of the present invention.

FIG. 23 is a block diagram showing a high-speed image processing device according to a third embodiment of the present invention.

24 is an explanatory diagram showing a state in which data is sequentially forwarded in a shift register in an x / y bus selection counter in the high-speed image processing device according to the embodiment of FIG. 23;

FIG. 25 is a block diagram showing a high-speed image processing device according to a modification of the embodiment of the present invention.

FIG. 26 is a block diagram showing a high-speed image processing device according to another modification of the embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 high-speed image processing device 11 light receiving element array 13 A / D converter array 14 parallel processing mechanism 15 control circuit 17 x / y data bus 19 x / y data bus data buffer 20 x / y bus selection counter 120 light receiving element 151 Memory 154 Address data storage area 170 x data line 170 e input / output unit 175 connection unit 180 y data line 190 data buffer memory 200 shift register 210 A / D converter 400 operation element 410 transfer shift register

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06T 1/20 G06T 1/60 450E 1/60 450 G06F 7/00 A (72) Inventor Hiroshi Tanaka Shizuoka 1126 Nomachi, Hamamatsu-shi 1 Hamamatsu Photonics Co., Ltd. F-term (reference) 5B022 AA03 BA02 CA02 CA05 FA01 5B045 AA01 BB12 GG12 5B047 AA13 BB01 BC01 EA09 EB12 EB17 5B057 AA05 BA02 CA12 CA16 CH03 CH02 DC06 DC07 DA07 CY16 DX07 GX03 GY15 GZ07 GZ18 GZ42 GZ50 HX02 HX23 JX30

Claims (5)

[Claims] 1. A parallel processing mechanism comprising: a plurality of processing elements arranged two-dimensionally in a plurality of rows and columns; each processing element comprising a parallel processing element array for performing a predetermined operation on a digital image signal; A data line for directional data transfer is provided in one-to-one correspondence with each column of the parallel processing mechanism, and a plurality of data lines for row data transfer is provided in one-to-one correspondence with each row of the parallel processing mechanism. The data line for each column direction data transfer connects a plurality of processing elements existing in the corresponding column and performs data transfer with each processing element in the corresponding column,
Each row-direction data transfer data line connects a plurality of processing elements present in a corresponding row and performs data transfer with each processing element in the corresponding row, and each column-direction data transfer data line corresponds to one corresponding data line. A high-speed image processing apparatus, comprising: a data transfer bus connected to a data line for row direction data transfer. 2. A light-receiving element array in which a plurality of light-receiving elements are two-dimensionally arranged in a plurality of rows and columns in one-to-one correspondence with the plurality of arithmetic elements, and a plurality of A / D converters. Devices are arranged one-dimensionally in a one-to-one correspondence with the plurality of rows of the light receiving element array and the plurality of rows of the arithmetic element array, and each A / D converter is provided with An A / D converter array that performs an analog-to-digital conversion of an output image signal sequentially read from the light receiving elements in one row and outputs the obtained digital image signal to a corresponding row of the arithmetic element array; A control circuit that controls the light receiving element array, the A / D converter array, the parallel processing mechanism, and the data transfer bus, wherein each operation element of the parallel operation element array is the A / D converter Digital image signal transferred from the detector array 2. The high-speed image processing apparatus according to claim 1, wherein a predetermined operation is performed on. 3. The high-speed image according to claim 2, further comprising a data buffer corresponding to both the plurality of column-direction data transfer data lines and the plurality of row-direction data transfer data lines. Processing equipment. 4. The apparatus according to claim 2, further comprising an address data generation counter corresponding to both the plurality of column-direction data transfer data lines and the plurality of row-direction data transfer data lines. High-speed image processing device. 5. The parallel processing mechanism further includes a plurality of transfer shift registers arranged one-to-one with the plurality of A / D converters and the plurality of operation element rows. A shift register for converting a digital image signal corresponding to an output image signal of the light receiving element belonging to the corresponding light receiving element row outputted from the corresponding A / D converter into a predetermined operation belonging to the corresponding row 3. The high-speed image processing apparatus according to claim 2, further comprising a transfer shift register array for sequentially transferring data to the elements.