CN1189648A - Synchronous serial data formwarder - Google Patents
Synchronous serial data formwarder Download PDFInfo
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- CN1189648A CN1189648A CN97118420A CN97118420A CN1189648A CN 1189648 A CN1189648 A CN 1189648A CN 97118420 A CN97118420 A CN 97118420A CN 97118420 A CN97118420 A CN 97118420A CN 1189648 A CN1189648 A CN 1189648A
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Abstract
The invention is to resolve the problem that hardware is changed in order to correspond to the inactive level of the received input data and a clock along different external receiving circuits. When a serial data output device 23 produces transmitted signal, a data control device 25 keeps the line of a data output terminal 11 corresponding to the state data stored in a series data state storing device 24 in advance, which is specified in advance. A clock control device 27 keeps the line of a clock output terminal 12 corresponding to the state data stored in a clock state storing device 26 in advance, which is specified in advance.
Description
The present invention relates to be connected to a plurality of outside receiving circuits, will transmit the synchronous serial data formwarder that these outside received signal circuit are given in the back serial transfer synchronously of data and clock signal.Particularly relate to be used for the final data that transmits data transmit finish the back connect this synchronous mode serial data device and external signal receiving circuit, between the data input and output terminal or the interface between the clock input and output terminal.
Figure 12 is the block diagram of the communication system of the synchronous mode serial data formwarder before expression utilizes.Figure 13 is the block diagram that the inside of this synchronous mode serial data formwarder of expression constitutes.In these figure, the 1st, make and transmit data and the clock signal former synchronous mode serial data formwarder of back serial transfer synchronously, 2a～2n is a plurality of outside receiving circuit of the transmission data sent of this synchronous mode serial data formwarder 1 of reception.The 11st, synchronous mode serial data formwarder 1 sends data output end that transmits data, the 12nd, export output terminal of clock of identical clock signal, the 13rd, in each outside receiving circuit 20～2n, receive data input pin that synchronous mode serial data formwarder 1 sends to the transmission data of data output end 11, the 14th, the clock input terminal of reception synchronizing clock signals.And, the 21st, produce clock signal generating apparatus by the clock signal of output terminal of clock 12 outputs, the 22nd, the input data-switching of the parallel input from the outside become serial data and make it with the clock signal of clock signal generating apparatus 21 synchronously, the serial data output unit exported by data output end 11 as the transmission data then.
The following describes its work.
Synchronous mode serial data formwarder 1 is transformed into serial data with serial data output unit 22 with it after the parallel input input in outside data, and the clock signal that takes place with clock signal generating apparatus 21 is synchronous, generation transmission data.By data output end 11, these transmission data are sent to outside receiving circuit 2a～2n as the appointment that transmits the destination, and send to outside receiving circuit 2a～2n as the appointment of transmission destination by the clock signal that clock generating device 21 takes place clock signal output terminal 12.When finishing this final data that transmits number transmission, as shown in figure 14, in this synchronous mode serial data formwarder 1, data output end 11 is intactly keeping it to transmit the final data of data.
Therefore, in such synchronous mode serial data formwarder 1, be necessary to consider with inferior method, when the input as the outside receiving circuit 2a～2n that transmits the destination receive the inactive level of data, for example for high level the time (to call H in the following text), it is H that the final data that transmits data is set up, or, synchronous mode serial data device 1 usefulness is notified the outside receiving circuit 2a～2n that transmits the destination someway, tell data to transmit and finish, make the outside receiving circuit 2a～2n line disconnection that receives this signal.And, be necessary to change the hardware of this synchronous mode serial data formwarder 1 in that itself and input are received under the corresponding situation of the different outside receiving circuit 2a～2n of the inactive level of data.
On the one hand, the line status that transmits output terminal of clock 12 after finishing at the final data that transmits data is, respectively to be data 1 when the clock signal negative edge enables, to be the state end transmission of data 0 (clock is along illegal state) when rising edge enables.Therefore, when enabling along different outside received signal circuit 2a～2n at once, need to change hardware with clock.
For so former synchronous mode serial data formwarder, for example open in the flat 5-181796 communique on the books the spy.
Because synchronous mode serial data formwarder in the past is above-mentionedly to constitute like that, so there is following problem: the needs consideration is corresponding with the inactive level that the input of the outside received signal circuit 2a～2n of conduct transmission destination receives data, make the final data that transmits data be made as this level usually, perhaps receive information circuit 2a～2n with being notified to someway as the outside of transmitting the destination, tell the transmission that transmits data to finish, make it line disconnection, at the outside receiving circuit 2a～2n different with input received signal data inactive level at once, be necessary to change the hardware of synchronous mode serial data device, and, to making itself and clock enable also to be necessary to change hardware along the different corresponding situations of outside receiving circuit 2a～2n.
The present invention for address the above problem and propose.Even purpose is for obtaining input received signal data inactive level or clock to be enabled along different outside receiving circuits, needn't change the synchronous mode serial data formwarder that hardware also can be mapped.
The synchronous mode serial data formwarder relevant with a first aspect of the present invention, in the moment that the transmission of the final data that transmits data finishes, the serial data output-controlling device is produced transmit end signal, the data control unit that receives this signal makes the line status of data output end remain the specified states corresponding with the status data of serial data status storage stores.
The synchronous mode serial data formwarder relevant with a second aspect of the present invention is being set in the data mode memory storage for the status data that makes the line status that transmits data output end after end signal produces remain data 0.
The synchronous mode serial data formwarder relevant with a third aspect of the present invention is being set in the data mode memory storage for the status data that makes the line status that transmits data output end after end signal produces remain data 1.
The synchronous mode serial transfer device relevant with a fourth aspect of the present invention is being set in the data mode memory storage for the status data that makes the line status that transmits data output end after finishing remain high-impedance state.
The synchronous mode serial transfer device relevant with a fifth aspect of the present invention, in the moment that the transmission of the final data that transmits data finishes, the serial data output-controlling device produce to transmit end signal, the clock control device that receives this signal make the line status of output terminal of clock remain be stored in the clock status memory storage in the corresponding specified states of status data of storing.
The synchronous mode serial data formwarder relevant with a sixth aspect of the present invention is being set in the clock status memory storage for the status data that makes the line status that transmits output terminal of clock after end signal takes place remain 0 level.
The synchronous mode serial data formwarder relevant with a seventh aspect of the present invention is being set in the clock status memory storage for the status data that makes the line status that transmits output terminal of clock after end signal takes place remain state 1.
The synchronous mode data relevant with a eighth aspect of the present invention transmit, and in order to make the line status that transmits output terminal of clock after end signal takes place remain the status data of high-impedance state, are set in the clock status memory storage.
The synchronous mode data link relevant with a ninth aspect of the present invention, when the final data that transmits data transmits end, the serial data output-controlling device produce to transmit end signal, the data control unit that receives this signal the line status of data output end remain be stored in data storage device in the corresponding specified states of status data; Clock control device remains the specified states corresponding with the status data that is stored in the clock status memory storage to the line status of output terminal of clock.
Fig. 1 is a block diagram of representing according to the embodiment of the present invention the communication system of 1 synchronous mode serial data formwarder.
Fig. 2 is the block diagram that is illustrated in the inner structure of the synchronous mode serial data formwarder in the embodiment 1.
Fig. 3 is the input that is illustrated in the outside receiving circuit that is attached thereto in the embodiment 1 transmission data when receiving the data inactive level and being data 0 and the sequential chart of the waveform of clock signal.
Fig. 4 be the input that is illustrated in the outside receiving circuit that is attached thereto in the embodiment 1 when receiving the data inactive level and being data 1 the transmission data and the sequential chart of clock signal waveform.
Fig. 5 be the input that is illustrated in the outside receiving circuit that is attached thereto in the embodiment 1 when receiving the data inactive level and being high-impedance state the transmission data and the sequential chart of clock signal waveform.
Fig. 6 is the block diagram of communication system that expression utilizes the synchronous mode serial data formwarder of this invention embodiment 2.
Fig. 7 is the block diagram of the inner structure of the synchronous mode serial data formwarder in the expression embodiment 2.
Fig. 8 is that the clock that is illustrated in the outside receiving circuit that is attached thereto in the embodiment 2 enables the transmission data when enabling for rising edge and the sequential chart of clock signal waveform.
Fig. 9 is that the clock that is illustrated in the outside receiving circuit that is attached thereto in the embodiment 2 enables the transmission data when enabling for negative edge and the sequential chart of clock signal waveform.
Figure 10 be illustrated in the outside receiving circuit that is attached thereto in the embodiment 2 high-impedance state as clock the transmission data during along illegal state and the sequential chart of clock signal waveform.
Figure 11 is the block diagram of the inner structure of the synchronous mode serial data formwarder in this working of an invention mode 3 of expression.
Figure 12 is the block diagram of the communication system of the synchronous mode serial data formwarder before expression utilizes.
Figure 13 is the block diagram of the inner structure of the synchronous mode serial data formwarder before the expression.
Figure 14 is the transmission data of the synchronous mode serial data formwarder before the expression and the sequential chart of clock signal waveform.
Below, one embodiment of the present invention are described.
Fig. 1 is the block diagram of communication system that expression utilizes the synchronous mode serial data formwarder of embodiment of the present invention 1.Fig. 2 is the block diagram that the inside of this synchronous mode serial data formwarder of expression constitutes.In these figure, the 3rd, transmitting data and clock signal back synchronous mode serial data formwarder serial transfer, embodiment of the present invention 1 synchronously, 4a～4n is a plurality of outside receiving circuit of accepting from the transmission data of these synchronous mode serial data formwarder 3 transmissions.The 11st, synchronous mode serial data formwarder 3 sends data output end that transmits data.The 12nd, output terminal of clock of transmission synchronizing clock signals.The 13rd, synchronous mode serial data formwarder 3 receives data input pin of the transmission data of data output end 11 transmissions in each outside receiving circuit 4a～4n.The 14th, the clock input terminal of reception synchronizing clock signals.
And, the 21st, produce from the clock signal generating apparatus of the clock signal of output terminal of clock 12 outputs, this is the same with the Previous System shown in Figure 13.The 23rd, the serial data output-controlling device, the input data of the parallel input from the outside are converted to serial data, and output after carrying out it synchronously as the clock signal that transmits data and clock-generating device 21, send the transmission end signal in the moment that the final data that transmits data has transmitted simultaneously.The 24th, after serial data output-controlling device 23 sends final data to transmit end signal according to the line status of the setting data setting data lead-out terminal 11 of outside and with it as the serial data memory storage that status data stores, for example use status register according to these setting data hold mode data.The 25th, data control unit, 23 that send from the serial data output unit, output to data output end 11 with the synchronous transmission data of clock signal as transmitting data, simultaneously after the final data that transmits data has transmitted, serial data output-controlling device 23 produces when transmitting end signal, status data according to 24 storages of serial data status storage, the line status of data output end 11 is remained the state of corresponding regulation, for example, use sending end signal switches transmission data and status data as control signal selector switch.
In addition, the synchronous mode serial data formwarder 3 in this embodiment 1 is made up of these clock signal generating apparatus 21, serial data output-controlling device 23, serial data memory storage 24 and data control unit 25.Different with former synchronous mode serial data device 1 shown in Figure 13 in this.
The following describes principle of work.
Fig. 3 is the transmission data synchronous mode serial data device 3 of expression in this invention embodiment 1,11 outputs of data output end and from the sequential chart of the waveform of the clock signal of output terminal of clock 12 outputs to Fig. 5.Fig. 3 is that the inactive level of the input reception data of outside receiving circuit 4a～4n is the situation of data 0, and Fig. 4 is that inactive level is the situation of data 1, and Fig. 5 is that disarmed state is the situation of high-impedance state.
When synchronous mode serial data formwarder 3 received parallel input data from the outside, serial data control device 23 was converted to serial data to it, simultaneously, after the clock signal that takes place with clock output device 21 is carried out synchronously, generated and sent data.These transmission data are delivered to data control unit 25, and data control unit 25 as transmitting data, outputs to it among outside received signal circuit 4a～4n as the appointment that transmits the destination by data output end 11.And the appointment of this transmission destination is to transmit the address of the outside receiving circuit 4a～4n of destination in the head additional representation that transmits data.Meanwhile, the clock signal sent of clock signal generating apparatus 21 also is sent to this outside receiving circuit 4a～4n by lead-out terminal 12.
Serial data output-controlling device 23 sends to data control unit 25 to the transmission data that are converted to serial data till final data, and after sending, generation sends signal and delivers to data control unit 25.After data control unit 25 received that this sends signal, reading and saving was at the status data of serial data status storage 24, and after sending the final data that transmits data, it outputed to data output end 11 as transmitting data.Thus, make the line status of data output end 11 remain on the specified states corresponding with the status data of from serial data status storage 24, reading.And it is to receive the corresponding setting data of data inactive level by input and the input that is connected outside connection circuit 4a～4n to carry out that the status data of this serial data status storage 24 is set.
For instance, when the inactive level that receives data when the input of the outside receiving circuit 4a～4n that is connected with this synchronous mode serial data formwarder 3 is data 0, input is the setting data of data 0 state in order to make the line status that is sending data output end 11 behind the final data that transmits data in serial data status storage 24 in advance, will be to reading of data control device 25 and the status data of output data 0 is preserved.Thus, the status data that data control unit 25 is read from serial data status storage 24 is data 0, and the data control unit 25 that receives the transmission end signal is exported these data 0 after sending the final data that sends data as transmitting data.Like this, after the final data of previous transmission data sends to as the outside receiving circuit (such as 4a) that transmits the destination, as shown in Figure 3, the content of the line status of data output end 11 and this final data has nothing to do, remains the state that receives data inactive levels (being data 0) as the input of the outside receiving circuit (for example outside receiving circuit 4n) that transmits the transmission destination of data next time.
Also having, when the input reception data inactive level of the outside receiving circuit 4a～4n that links to each other with this synchronous mode serial data formwarder 3 is data 1 or high-impedance state, also is the same.That is, when input reception data inactive level is data 1, in serial data status storage 24, preserve the status data that is used for output data 1 in advance.Behind the final data that sends previous transmission data, data control unit 25 outputs are as the data 1 that transmit data.As shown in Figure 4, make the line status of data output end 11 remain the state of data 1.And, when input reception data inactive level is high-impedance state, as shown in Figure 5, in serial data status storage 24, preserve the status data corresponding in advance with high-impedance state, after making it to send the final data of last transmission data, data control unit 25 remains high-impedance state to the line status of data output end 11.
Like this, according to embodiment 1, only need to rewrite the status data that is stored in serial data status storage 24 and just can make the line status of data output end 11 remain on the corresponding state of input reception data inactive level with outside received signal circuit 4a～4n by setting data.Do not change the hardware of synchronous mode serial data formwarder 3, just outside received signal circuit 4a～4n that can be different with input reception data inactive level is corresponding.
Also have, in the serial data status storage 24, not only can keep making the line status of data output end 11 to remain the status data of above-mentioned data 0, data 1 and high-impedance state, but also can be kept for keeping transmitting the status data of the final data of data.If such status data is kept at serial data status storage 24, can guarantee interchangeability these synchronous mode serial data device 3 former states with in the former communication system with former synchronous mode serial data formwarder 1.
In above-mentioned embodiment 1, illustrated the line status of data output end remained on the input of outside received signal circuit to receive the corresponding state of data inactive level.Equally, come corresponding clock to enable by the clock that the line status of output terminal of clock is remained the outside receiving circuit that transmits data next time along illegal state along different outside receiving circuits.
Fig. 6 represents the block diagram of the communication system of synchronous mode serial data formwarder such, that utilize embodiment of the present invention 2.Fig. 7 is the block diagram of the inner structure of this synchronous mode serial data formwarder of expression.In each figure, the 5th, in embodiments of the present invention 2 transmitting the synchronous mode serial data formwarder that data and clock signal back serial are synchronously exported.6n～6n is a plurality of outside receiving circuit that receives from the transmission data of these cotype serial data formwarder 5 transmissions.And, the 11st, data output end, the 12nd, output terminal of clock, the 13rd, data input pin, the 14th, clock input terminal.In the synchronous mode serial data formwarder 5 21 is clock signal generating apparatus, the 23rd, the serial data output-controlling device.And, because those parts that represent with prosign among these parts and Fig. 1 and Fig. 2, in the embodiment 1 are identical, so detailed.
Also have, the 26th, the clock status memory storage, it is according to the setting data of outside, be set in and produce the line status that sends output terminal of clock 12 behind the signal when serial data output unit 23 transmits final data in the data, and it is stored as status data, for example use status register according to setting data hold mode data.The 27th, clock control device, the clock signal that it sends clock signal generating apparatus 21 outputs to output terminal of clock 12, simultaneously, sending the final data that transmits in the data, after serial data output-controlling device 23 produces and sends signal, the line status of output terminal of clock 12 is remained the corresponding specified states of status data (clock that promptly remains the outside receiving circuit 6a～6n that is attached thereto is along illegal state) of storing with clock status memory storage 26, for example use sending signal carries out the switching of clock signal and status data as control signal selector switch.
Have again, the synchronous mode serial data formwarder 5 of present embodiment 2 is by clock signal generating apparatus 21, serial data output-controlling device 23, clock status memory storage 26 and clock control device 27 form, and be different with the synchronous mode serial data formwarder of embodiment shown in Figure 2 in this.
The following describes working condition.
Fig. 8 is to be illustrated in the present embodiment 2 from the transmission data of data output end 11 outputs of synchronous mode serial data device 5 with from the sequential chart of the clock signal waveform of output terminal of clock 12 outputs to Figure 10.Fig. 8 illustrate become the clock that sends the outside receiving circuit 6a～6n of object next time enable along 0 level of clock signal as the situation of clock along illegal state, situation when Fig. 9 illustrates 1 level of clock signal as clock along illegal state, Figure 10 illustrates the situation of high-impedance state as the time clock illegal state.
After synchronous mode serial data formwarder 5 receives parallel input data from the outside, at serial data output-controlling device 23 it is transformed into serial data, simultaneously, the clock signal that itself and clock signal generating apparatus 21 are taken place is synchronous, produces and transmits data.These transmission data are sent to the outside receiving circuit 6a～6n that transmits the destination by data output end 11.On the other hand, the clock signal that clock signal generating apparatus 21 takes place is also delivered to clock control device 27, and clock control device 27 is delivered to the outside receiving circuit 6a～6n that transmits the destination to this clock signal by output terminal of clock 12.
Serial data output-controlling device 23 sends the transmission data 11 that are transformed into serial data by lead-out terminal 11, till final data, generates and sends signal, and it is delivered to clock control device 27.Receive that this clock control device that sends signal 27 reads the status data that remains in the clock status memory storage 26, when sending the final data that transmits data, the corresponding official hour of status data that the line status of output terminal of clock 12 is remained and read from this clock status memory storage 26 is along illegal state.Also have, carry out setting to the status data of clock status memory storage 26 by input and the clock that is connected on outside receiving circuit 6a～6n along the corresponding setting data of illegal state this moment.
For instance, when the clock of the clock signal of the outside receiving circuit 6a～6n that is connected with this synchronous mode serial data formwarder 5 enables when enabling for rising edge, importing in order to make the line status of output terminal of clock 12 behind the final data that is sending the transmission data in clock status memory storage 26 in advance is the setting data of the clock of 0 level along illegal state, will preserve to the status data of reading output data 0 of clock control device 27.Thus, the status data that clock control device 27 is read from clock output memory storage 26 is data 0, therefore, receive that the clock control device 27 that sends signal remains on the clock of 0 level as shown in Figure 8 along illegal state according to the line status that these data 0 will send output terminal of clock 12 behind the final data.
And, when the clock of the clock signal of the outside receiving circuit 6a～6n that links to each other with this synchronous mode serial data formwarder 5 enables when enabling for negative edge, with high-impedance state as clock during along illegal state too, clock control device 27 is read the status data that is kept in advance in the clock status memory storage 26, and, the line status of output terminal of clock 12 behind the final data that sends the transmission data is remained the clock of 1 level shown in Figure 9 or the high-impedance state shown in Figure 10 etc. along illegal state according to this status data.
Like this,, need only rewrite the status data of storage in the clock status memory storage 26, just can remain the clock of outside received signal circuit 6a～6n to the line status of output terminal of clock 12 along illegal state by setting data if according to this embodiment 2.Do not change hardware just can realize can with have any clock and enable the corresponding synchronous mode serial data formwarder 5 of outside receiving circuit 6a～6n on edge.
In above-mentioned embodiment 1, the corresponding state of input reception data inactive level that the line status of data output end is remained the outside receiving circuit that is connected with next time has been described.And, in embodiment 2, illustrated the line status of output terminal of clock is remained the clock of the outside receiving circuit that is connected with next time along illegal state.But also may realize having concurrently the synchronous mode serial data formwarder of these two kinds of functions.
Figure 11 represents the block diagram of the inner structure of the synchronous mode serial data formwarder in the embodiment of the present invention 3.In the drawings, the 11st, data output end, the 12nd, output terminal of clock, the 21st, clock signal generating apparatus, the 23rd, serial data output-controlling device, the 24th, serial data status storage, the 25th, data control unit, the 26th, clock status memory storage, the 27th, clock control device.These are identical with part additional same symbolic representation, in embodiment 1 or the embodiment 2 among Fig. 2 and Fig. 7, so save detailed description.
And, the 7th, make and transmit synchronous mode serial data formwarders data and clock signal serial transfer afterwards synchronously, in the embodiments of the present invention 3.It is formed by these clock signal generating apparatus 21, serial data output-controlling device 23, serial data status storage 24, data control unit 25, clock status memory storage 26 and clock control device 27, transmit data by data control unit 25 outputs, clock signal is through clock control device 27 outputs.From this point, be different with the synchronous mode serial data formwarder 3 of Fig. 2 and embodiment 1 shown in Figure 7 or the synchronous mode serial data formwarder 5 in the embodiment 2.
The following describes working condition
Here, synchronous mode serial data formwarder 3 in basic work and the embodiment 1 and the synchronous serial data in the embodiment 2 situation that transmits data 5 is the same.Promptly, synchronous mode serial data formwarder 7 is behind outside input parallel input data, in serial data output-controlling device 23, it is transformed to serial data, and it is synchronous with the clock signal of clock signal generating apparatus 21 generations, generate and send data, data control unit 25 sends data to this as transmitting data, is sent to the outside receiving circuit that transmits the destination by data output end 11.On the other hand, the clock signal that clock signal generating apparatus 21 takes place is sent to clock control device 27, and clock control device 27 outputs to the outside receiving circuit that transmits the destination by output terminal of clock 12 with it.
Serial data output-controlling device 23 is sending data to data control unit 25, and after sending final data, generation sends signal and it is delivered to data control unit 25 and clock control device 27.After data control unit 25 obtains this and sends signal, read the status data that keeps existing the there, and after sending the final data that transmits data from serial data status storage 24, it as transmitting data by 11 outputs of data output end.Therefore, the line status of this data output end 11 remains the state of the regulation corresponding with the status data of reading from serial data status storage 24.And, when clock control device 27 is received when sending signal, read the status data that has its there from clock status memory storage 26, and after sending the final data that transmits data, the line status of output terminal of clock 12 is remained on the clock corresponding with the status data of reading from this clock status memory storage 26 along illegal state.
And, the same with the situation of embodiment 1 or embodiment 2, setting to the status data of serial data status storage 24, be to receive the corresponding setting data of data inactive level by the input and the input of the outside receiving circuit that connects to carry out, to the setting of the status data of clock status memory storage 26, be to carry out along the corresponding setting data of illegal state by the clock of input with the outside receiving circuit that links to each other.
Like this, if according to this embodiment 3, need only use the status data of rewriting 24 timely mitriform attitude memory storage 26 storages of serial data status storage from the setting data of outside, the input that the line status of data output end 11 is remained on outside receiving circuit receives the corresponding state of data inactive level, and the clock that the line status of output terminal of clock 12 is remained with outside receiving circuit enables along corresponding clock along illegal state.Therefore, needn't change the hardware of synchronous mode serial data formwarder 7, input receives the data inactive level and clock enables along just being connected with any outside receiving circuit.
As mentioned above, according to a first aspect of the invention, constitute at serial data output control dress Buy property and give birth to when sending signal, data control unit remains the line status of data output end The specified states corresponding with the status data of reading from the serial data status storage. Therefore, Have needn't change hardware, only by the status data of serial data status storage is just rewritten Can obtain synchronous mode corresponding to outside receiving circuit different from importing the receive data inactive level The effect of serial data formwarder.
According to a second aspect of the invention, become in the data mode storage device, to set and be used for Make the line status that sends data output end after signal takes place remain the state of data 0 Status data. Therefore, have needn't change hardware just can obtain can with the input receive data do not have The effect level is that the outside of data 0 receives synchronous mode serial data formwarder corresponding to signal circuit Effect.
According to a third aspect of the invention we, constitute in the data mode storage device to set and be used for making The line status of data output end after sending signal and taking place remains the state of data 1 Status data. Therefore, have needn't change hardware just can obtain can with the input receive data invalid Level is the number that 1 outside receives synchronous mode serial data formwarder corresponding to signal circuit According to.
According to a forth aspect of the invention, constitute in the data mode storage device to set and be used for making The line status that sends data output end after letter takes place remains the status number of high-impedance state According to. Therefore, have and do not change hardware just can to obtain with importing the receive data inactive level be high resistant The outside of state receives the effect of synchronous mode serial data formwarder corresponding to signal circuit.
According to a fifth aspect of the invention, constitute at the serial data output-controlling device and send transmission During complete signal, clock control device remains the line status of output terminal of clock and clock status The specified states that the status data of memory device stores is corresponding. Therefore, have needn't change hardware, Only just can obtain enabling the edge not with clock by the status data that changes the clock status storage device Outside together receives the effect of synchronous mode serial data formwarder corresponding to signal circuit.
According to a sixth aspect of the invention, constitute in the clock status storage device to set and be used for making The line status that sends output terminal of clock after signal takes place remains the status number of 0 level According to. Therefore, have and to change hardware and just can obtain enabling along enabling for rising edge with clock The outside effect that receives synchronous mode serial data formwarder corresponding to signal circuit.
According to a seventh aspect of the invention, constitute in the clock status storage device to set and be used for making The line status of output terminal of clock after sending signal and sending remains the state of 1 level Data. Therefore, have and to change hardware and just can obtain enabling along enabling for trailing edge with clock The outside receive the effect of synchronous mode serial data formwarder corresponding to signal circuit.
According to an eighth aspect of the invention, constitute in the clock status storage device to set and be used for making The line status of output terminal of clock after sending signal and sending remains the state of high-impedance state Data. Therefore, have needn't change hardware just can obtain can with high-impedance state is prohibited as clock The effect of the synchronous mode serial data formwarder that only the outside receiving circuit of state is corresponding.
According to a ninth aspect of the invention, constituting the serial data output-controlling device sends During signal, data control unit remains the line status of data output end with data mode and deposits Specified states corresponding to status data that storage device is preserved, clock control device is output terminal of clock Line status remain state corresponding to status data of preserving with the clock status storage device, because of This has the status number of only rewriting serial data status storage and clock status storage device According to and needn't change hardware just can obtain can with any input receive data inactive level and clock Enable the effect of the synchronous mode serial data formwarder that the outside receiving circuit on edge links to each other.
Claims (9)
1. synchronous mode serial data formwarder, it is characterized in that, comprising: sending the serial data output-controlling device of signal to the transmission data of outside receiving circuit serial transfer and clock signal back output synchronously, while generation when sending the final data of these transmission data of clock signal generating apparatus generation from data output end;
Set that described serial output-controlling device produces the line status that sends described data output end behind the signal and with its serial data status storage as the status data storage,
From the output of described serial data output-controlling device, with the synchronous transmission data of clock signal as when transmitting data and output to described data output end, produce when sending signal the data control unit that the line status of described data output end is remained the corresponding specified states of the status data stored with described serial data state memorization device at described serial data output-controlling device.
2. the synchronous mode serial data formwarder of claim 1 record is characterized in that: set the status data that the line status that the serial data output-controlling device is produced data output end after sending signal remains data 0 in the data mode memory storage.
3. the synchronous mode serial data formwarder of claim item 1 record is characterized in that, setting is the status data of data 1 with the line status that the serial data output-controlling device produces data output end after sending signal in the data mode memory storage.
4. the synchronous mode data link of claim item 1 record is characterized in that: set the status data that the line status that the serial data output-controlling device is produced data output end after sending signal remains high-impedance state in the data mode memory storage.
5. synchronous mode serial data formwarder, it is characterized in that, comprising: in the clock signal back output synchronously that transmission data that send to outside receiving circuit serial from data output end and clock signal generating apparatus are produced, generation sends the serial data output-controlling device of signal when sending the final data of these transmission data simultaneously;
Set that described serial output-controlling device produces the line status that sends the described lead-out terminal behind the signal and with its clock status memory storage as the status data storage;
The described clock signal of sending from clock signal generating apparatus outputed to described output terminal of clock, simultaneously producing the clock control device that the line status of described output terminal of clock is remained when sending signal the specified states corresponding with the status data of described clock status memory device stores at described serial data output unit.
6. the synchronous mode serial data formwarder of claim 5 record is characterized in that: set the status data that the line status that will make the serial data output-controlling device produce output terminal of clock after sending signal remains 0 level in the clock status memory storage.
7. the synchronous mode serial data formwarder of claim 5 record is characterized in that: set the status data that the line status that the serial data output-controlling device is produced output terminal of clock after sending signal remains 1 level in the clock status memory storage.
8. the synchronous mode serial data formwarder of claim 5 record, it is characterized in that the line status of output terminal of clock after setting sends signal with the generation of serial data output-controlling device in the clock status memory storage remains the status data of high-impedance state.
9. a synchronous mode serial data formwarder is characterized in that, comprising:
Data output serial data output-controlling device, the clock signal back output synchronously of sending to the transmission data and the clock signal generating apparatus of outside receiving circuit serial transfer from terminal, simultaneously, generation sends signal when sending the final data of these transmission data;
The serial data status storage is set described serial data output-controlling device and is produced the line status that sends described data output end behind the signal, and it is preserved as status data;
Data control unit, the output of described serial data control device, output to described lead-out terminal with the synchronous transmission data of clock signal as transmitting data, simultaneously, when described serial data output-controlling device generation sends signal, the line status of described serial data lead-out terminal is remained the state corresponding with the status data of described serial data memory device stores;
The clock status memory storage is set described serial data output-controlling device and is produced the line status that sends output terminal of clock behind the signal, and it is stored as status data;
Clock control device, the clock signal that described clock signal generating apparatus is produced outputs to described output terminal of clock, simultaneously, when described serial data output-controlling device generation sends signal, the line status of described output terminal of clock is remained the corresponding specified states of status data of storing with described clock status device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97118420A CN1189648A (en) | 1997-01-31 | 1997-09-04 | Synchronous serial data formwarder |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19406/97 | 1997-01-31 | ||
| CN97118420A CN1189648A (en) | 1997-01-31 | 1997-09-04 | Synchronous serial data formwarder |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1189648A true CN1189648A (en) | 1998-08-05 |
Family
ID=5174806
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97118420A Pending CN1189648A (en) | 1997-01-31 | 1997-09-04 | Synchronous serial data formwarder |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1189648A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100349100C (en) * | 2003-09-19 | 2007-11-14 | 三洋电机株式会社 | Interface circuit and a clock output method therefor,data processing circuit and system |
-
1997
- 1997-09-04 CN CN97118420A patent/CN1189648A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100349100C (en) * | 2003-09-19 | 2007-11-14 | 三洋电机株式会社 | Interface circuit and a clock output method therefor,data processing circuit and system |
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