CN118837726B - MEMS chip testing method and system and storage medium - Google Patents
MEMS chip testing method and system and storage medium Download PDFInfo
- Publication number
- CN118837726B CN118837726B CN202411310362.0A CN202411310362A CN118837726B CN 118837726 B CN118837726 B CN 118837726B CN 202411310362 A CN202411310362 A CN 202411310362A CN 118837726 B CN118837726 B CN 118837726B
- Authority
- CN
- China
- Prior art keywords
- mems chip
- fpga board
- mems
- mcu
- test data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 157
- 238000000034 method Methods 0.000 claims abstract description 31
- 238000004458 analytical method Methods 0.000 claims abstract description 15
- 238000010998 test method Methods 0.000 claims description 7
- 238000005259 measurement Methods 0.000 claims description 3
- 230000004044 response Effects 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 description 11
- 238000005538 encapsulation Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 6
- 230000001133 acceleration Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 238000013480 data collection Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000036316 preload Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The application provides a method and a system for testing an MEMS chip and a storage medium. The method comprises the steps that an FPGA board is connected with an MCU and a plurality of MEMS chips through a plurality of interfaces of the FPGA board, each interface is connected with one MEMS chip and is also connected with an upper computer, the FPGA board transmits control instructions received from the upper computer to each MEMS chip in parallel, the FPGA board receives test data transmitted by each MEMS chip in parallel, the FPGA board sends the test data to the MCU so that the MCU analyzes the test data and sends analysis results to the upper computer, or the FPGA board analyzes the test data and sends analysis results to the MCU so that the MCU sends the analysis results to the upper computer. The application can reduce the chip test time, improve the test efficiency and realize targeted automatic calibration according to the difference of each MEMS chip.
Description
Technical Field
The application relates to the field of chip testing, in particular to a method and a system for testing a Micro Electro MECHANICAL SYSTEM (MEMS) chip and a storage medium.
Background
Currently, MEMS chips used to control IMUs (Inertial Measurement Unit, inertial measurement units) or gyroscopes, etc. require testing before shipping to ensure good performance of the MEMS chip that is ultimately marketed. In the prior art, a Micro Controller Unit (MCU) based on a test machine station generally collects data generated by a MEMS chip, and the data may be referred to as "test data", and determines whether the MEMS chip meets factory requirements according to the test data. The MCU and each MEMS chip adopt a serial transmission mode to transmit test data, but the efficiency of the serial transmission mode is slower, generally, each MEMS chip needs to take about 20 minutes in the process of performing inertial angle test and calibration, if the number of MEMS chips to be tested is large, the time spent is longer, and the test efficiency and the delivery efficiency of the MEMS chips are obviously seriously affected.
Disclosure of Invention
In view of this, the application provides a method, a system and a storage medium for testing a MEMS chip, which can at least solve the problem of low testing efficiency of the MEMS chip.
The application provides a testing method of a MEMS chip, which is used for controlling a plurality of shafts of an IMU or a gyroscope, and comprises the following steps:
The FPGA (Field Programmable GATE ARRAY ) board is connected with the MCU, and is connected with a plurality of MEMS chips through a plurality of interfaces of the FPGA (Field Programmable GATE ARRAY), each interface is connected with one MEMS chip, and the MCU is also connected with the upper computer;
The FPGA board transmits control instructions received from the upper computer to each MEMS chip in parallel;
the FPGA board receives test data transmitted by each MEMS chip in parallel;
The FPGA board transmits the test data to the MCU so that the MCU analyzes the test data and transmits an analysis result to the upper computer, or the FPGA board analyzes the test data and transmits an analysis result to the MCU so that the MCU transmits the analysis result to the upper computer.
Optionally, each MEMS chip is arranged on the FPGA board, and the method further comprises:
the FPGA board is provided with a temperature sensor to detect the current temperature of each MEMS chip;
the FPGA board sends the current temperature to an MCU to judge whether the current temperature reaches a preset temperature or not by the MCU, and generates a trigger instruction when the current temperature is determined to reach the preset temperature;
and the FPGA board responds to the trigger instruction received from the MCU, and executes the step of transmitting the control instruction received from the upper computer to each MEMS chip in parallel.
Optionally, the method further comprises:
the FPGA board collects analog signals transmitted in parallel when each MEMS chip is powered on;
the FPGA board is used for carrying out analog-to-digital conversion on the acquired analog signals into digital signals;
and the FPGA board calibrates each MEMS chip according to the digital signals.
Optionally, the test data is obtained by testing each axis of the IMU or gyroscope at a plurality of parameter sites, and the calibrating the each MEMS chip by the FPGA board according to the digital signal includes:
For two adjacent parameter sites, before analog signals are output to the latter parameter site, calibration of the corresponding MEMS chip is completed according to the digital signals generated by the former parameter site.
Optionally, the test data is represented as an encapsulation packet, the encapsulation packet including a data header, a data type, a source number, a data length, and a data content, the source number representing a MEMS chip from which the test data is derived, the method further comprising:
The FPGA board acquires the data of each axis from the test data;
creating a storage queue for each axis of the acquired data and storing the corresponding data;
Judging whether test data of all MEMS chips are received or not according to the source numbers and the number of the storage queues, if yes, determining that acquisition of the test data is completed, and if not, continuously receiving the test data transmitted by all MEMS chips in parallel.
Optionally, the method further comprises:
S11, connecting the interfaces, selecting one MEMS chip to send out an inquiry packet containing self identification and the number of storage queues, wherein the storage queues are created when the data corresponding to each axis are acquired from the test data, and each axis creates a storage queue;
S12, after the rest MEMS chips receive the query packet, comparing the current storage queue number with the storage queue number of one MEMS chip;
S13, for any one of the remaining MEMS chips, if the number of the current storage queues is smaller than that of the one MEMS chip, sending out an inquiry packet;
S14, for any one of the remaining MEMS chips, if the current number of the storage queues is greater than or equal to the number of the storage queues of one MEMS chip, not sending out an inquiry packet;
repeating the steps S11 to S14 until only one MEMS chip remains;
and in response to receiving the package transmitted by the last remaining MEMS chip, judging that test data of all MEMS chips are received, and determining that the acquisition of the test data is completed.
Optionally, the package includes a data header, a data type, a source number, a data length, and a data content, the source number representing a MEMS chip from which the test data is derived and identifying a last remaining MEMS chip, the method further comprising:
the FPGA board determines that the number of the residual MEMS chips is only one according to the source number.
Optionally, the method further comprises:
Acquiring the maximum duration from sending out an interrogation packet from one MEMS chip to receiving the interrogation packet by another MEMS chip;
and when the query packet is detected to exceed the maximum duration from the previous time, determining that only one MEMS chip exists as the rest MEMS chip if any query packet is not received.
The application provides a test system of MEMS chips, which comprises an upper computer, an MCU and an FPGA board, wherein the FPGA board is connected with the MCU, the FPGA board is provided with a plurality of interfaces for being connected with a plurality of MEMS chips, each interface is connected with one MEMS chip, the MCU is connected with the upper computer, and the test of the MEMS chips is executed among the FPGA board, the upper computer and the MCU by the method according to any one of the above.
The storage medium provided by the application stores a test program, and the test program realizes the corresponding steps of the MEMS chip test method when being executed by a processor.
As described above, the application receives the test data generated by each MEMS chip through the FPGA board, and the FPGA board and each MEMS chip transmit the test data in a parallel transmission mode, so that the test data can be transmitted simultaneously through a plurality of lines in the parallel transmission mode, more test data can be transmitted in the same time, thereby reducing the test time of the MEMS chip and improving the test efficiency.
In addition, the application can collect analog signals transmitted in parallel when each MEMS chip is electrified through the FPGA board, so that each MEMS chip is calibrated, and the application can realize targeted automatic calibration according to the difference of each MEMS chip, thereby ensuring the optimal performance of each MEMS chip.
Furthermore, the application can acquire the data of each axis of the IMU or the gyroscope from the test data through the FPGA board, creates a storage queue when the data of one axis is acquired, stores the corresponding data, and then judges whether the test data of all MEMS chips are received or not according to the source number and the number of the storage queues carried in the test data, thereby automatically realizing the determination of whether the acquisition of the test data is completed or not.
The application can also connect a plurality of interfaces through the FPGA board so as to interconnect a plurality of MEMS chips, and the MEMS chips determine whether to send out an inquiry packet by comparing the number of the storage queues, thereby determining whether to be the last MEMS chip sending out the inquiry packet.
Drawings
FIG. 1 is a flow chart of a method for testing a MEMS chip according to an embodiment of the application;
FIG. 2 is a schematic diagram of a testing system of a MEMS chip according to an embodiment of the application;
FIG. 3 is a schematic diagram showing interactions among a MEMS chip, an FPGA board, an MCU and an upper computer in a test process according to an embodiment of the present application;
FIG. 4 is a schematic diagram showing interaction of another MEMS chip, an FPGA board, an MCU and an upper computer in a testing process according to the embodiment of the application;
Fig. 5 is a flowchart illustrating a process of detecting whether test data collection is completed according to an embodiment of the present application.
Detailed Description
In order to solve the problems in the prior art, the application provides a method and a system for testing an MEMS chip and a storage medium. The principles of solving the problems are basically the same or similar based on the same conception, and the embodiments of each of the protection subject matters can be referred to each other, and the repetition is omitted.
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly described below with reference to specific embodiments and corresponding drawings. It will be apparent that the embodiments described below are only some, but not all, embodiments of the application. Under the condition of no conflict, the following embodiments and technical features thereof can be combined with each other and also belong to the technical scheme of the application.
Fig. 1 is a flow chart of a testing method of a MEMS chip according to an embodiment of the application. The test method of the MEMS chip can be simply called as a method or a test method, and the execution body of the test method can be an FPGA board, namely the test board integrated with the FPGA. The MEMS chip is used for controlling a plurality of axes of the IMU or the gyroscope, taking the IMU as an example, the MEMS chip is used for controlling the accelerometers of the three axes and the gyroscope of the three axes to execute corresponding operations.
As shown in fig. 1, the method at least includes the following steps S1 to S4.
S1, the FPGA board is connected with the MCU, a plurality of MEMS chips are connected through a plurality of interfaces of the FPGA board, each interface is connected with one MEMS chip, and the MCU is also connected with an upper computer.
In combination with the scenario shown in fig. 2, the upper computer is connected with the MCU, for example, the upper computer and the MCU are connected through the slip ring, the MCU is connected with the plurality of MEMS chips through a single FPGA board, and the single FPGA board is provided with a plurality of interfaces, so that the single FPGA board can realize the connection with a plurality of MEMS chips with the same number or less than the same number, six MEMS chips are only exemplarily shown in the figure and respectively numbered 1-n, the corresponding eight interfaces can be respectively numbered 1-n, and the MEMS chips with the same number are connected with the interfaces in a one-to-one correspondence. It should be understood that other examples may be provided that a single or more than two other numbers of FPGA boards are connected to an MCU, so as to adapt to the test scenario requirements of other numbers of MEMS chips, and the structures of the FPGA boards may be identical or different, which is not limited by the present application. All the FPGA boards are interconnected, and accordingly data transmission and synchronous control are achieved.
The application refers to an interface connected with the MEMS chip as a first interface and an interface connected with the MCU as a second interface. In an example shown in fig. 2, the FPGA board is a test board with independent data processing and operation capabilities, the first interface may be an interface such as an LPT interface, which has a wide application scenario, the second interface includes, but is not limited to, a TCP/UDP port, TCP is a transmission control protocol, UDP is a user datagram protocol, and corresponding data, for example, log data and command data, may be transmitted in parallel between the FPGA board and the MCU, so as to improve transmission efficiency.
The MEMS chip connected with the FPGA board can be called a chip to be tested, and the upper computer, the MCU and the chips to be tested are connected through the FPGA board.
And S2, the FPGA board transmits the control instruction received from the upper computer to each MEMS chip in parallel.
And S3, the FPGA board receives test data transmitted by each MEMS chip in parallel.
And S4, the FPGA board transmits the test data to the MCU so that the MCU analyzes the test data and transmits an analysis result to the upper computer, or the FPGA board analyzes the test data and transmits an analysis result to the MCU so that the MCU transmits the analysis result to the upper computer.
After step S1 and before step S2, referring to fig. 3 and fig. 4 together, the upper computer (e.g. through its test management program) issues a control instruction to the MCU, and the MCU forwards the control instruction to the FPGA board, where the control instruction is used to test one or more MEMS chips connected to the FPGA board, and specifically may be distinguished according to the carried identifier of each first interface, where the control instruction is issued to which MEMS chip or chips. The control instructions may contain instruction data, but not log data.
Each MEMS chip executes a corresponding test according to the received control instruction and generates corresponding test data including, but not limited to, acceleration values and angular velocity values of each axis of the IMU, wherein the test data can be represented as log data, and then each MEMS chip transmits the test data to the FPGA board through a corresponding first interface. Step S2 may be regarded as a step of collecting test data by the FPGA board. In an example, each first interface may have a buffer function to buffer test data transmitted by a corresponding MEMS chip, where the first interface sends a reminder to the FPGA board when the buffer data is formed, and the FPGA board reads the buffer data after detecting the reminder, so as to implement parallel transmission between each MEMS chip and the FPGA board. The FPGA board can distinguish the corresponding MEMS chip by the reference number of the first interface, taking the scenario shown in fig. 2 as an example, the test data generated and transmitted by the MEMS chip of reference number 3 is transmitted by the first interface of reference number 3.
In one example of step S4, after the test data of all the MEMS chips are transmitted to the FPGA board, the FPGA board packages and sends the test data to the MCU together, and in another example, the FPGA board may send the test data of one MEMS chip to the MCU after receiving the test data of the other MEMS chip.
As described above, the application receives the test data generated by each MEMS chip through the FPGA board, the FPGA board and each MEMS chip transmit the test data in a parallel transmission mode, each MEMS chip and the first interface which is correspondingly connected with the FPGA board can be regarded as a data channel in parallel transmission, and the parallel transmission mode enables the test data to be transmitted simultaneously through a plurality of channels, and more test data can be transmitted in the same time, thereby reducing the test time of the MEMS chips and improving the test efficiency.
The application can send the test data to the MCU by the FPGA board for analysis by the MCU as shown in figure 3, or analyze the test data by the FPGA board as shown in figure 4. The specific process and principle of the MCU or FPGA board for analyzing the test data can refer to the prior art, and will not be described herein. For example, comparing the collected test data with the data obtained by theoretical calculation, and when the difference value of the collected test data and the data exceeds a preset threshold value, considering that the test of the current shaft is unqualified, the upper computer can record the test data and the analysis result to form log data related to the test.
The temperature of the environment where the MEMS chip is located is sensitive to the influence of the test result, so that the MEMS chip is tested, and whether the operation data of each shaft of the IMU at different temperatures meets the preset requirement can be understood, and the current temperature needs to be detected to reach the preset temperature before the test data are collected. Referring to fig. 3 and fig. 4 together, the method further includes:
S101, setting a temperature sensor on an FPGA (field programmable gate array) board, and detecting the current temperature of each MEMS chip through the temperature sensor by arranging each MEMS chip on the FPGA board.
S102, the FPGA board sends the current temperature to the MCU so as to judge whether the current temperature reaches the preset temperature or not by the MCU, and generates a trigger instruction when the current temperature is determined to reach the preset temperature.
The MCU can read the temperature of the FPGA board in real time, and can perform testing after reaching the preset temperature required by testing. When the current temperature does not reach the preset temperature, no trigger instruction is generated, and S101 is continued to be executed.
S103, the FPGA board detects whether a trigger instruction is received from the MCU.
The FPGA board responds to the trigger instruction received from the MCU, and executes the step S2, namely, the control instruction received from the upper computer is transmitted to each MEMS chip in parallel.
The temperature sensor in the prior art is arranged on a platform where the MCU is located, and the temperature obtained by actual test is different from the temperature of the actual position of the MEMS chip, so that the test result is adversely affected. According to the temperature sensor, the temperature sensor is placed on the FPGA board, the FPGA board can directly read the real-time temperature closest to each MEMS chip in real time, and accordingly the real-time temperature can be accurately compensated to reach the theoretical preset temperature, and therefore accuracy of test data is guaranteed.
With continued reference to fig. 3 and 4, the method further includes:
S104, the FPGA board collects analog signals transmitted in parallel when each MEMS chip is powered on.
S105, the FPGA board converts the acquired analog signals into digital signals in an analog-to-digital mode.
And S106, the FPGA board calibrates each MEMS chip according to the digital signals.
Before testing, the present example calibrates each MEMS chip through the FPGA board, the MEMS chip can configure its internal register to output Analog signals through Pin pins during design, and in combination with the example shown in fig. 2, an ADC (Analog-to-Digital Converter ) sampling chip can be additionally arranged on the FPGA board, after each MEMS chip is powered on by accessing the FPGA board, different Analog signals are output, the ADC sampling chip samples, sampled data is sent to the FPGA board, the FPGA board performs real-time data analysis, and then the FPGA board configures the internal calibration register of the MEMS chip to calibrate, and whether the MEMS chip is calibrated is confirmed by comparing the sampled data, so that each MEMS chip can input optimal calibration parameters. In one example, the present application may pre-load empirical values, which may be historical calibration parameters when previously calibrating various types of MEMS chips, to MEMS chips to reduce auto-calibration time and improve auto-calibration efficiency.
In the prior art, all MEMS chips are uniformly loaded with pre-debugged calibration parameters through an MCU (micro control Unit), namely, the loaded calibration parameters of all MEMS chips are identical, the prior art cannot realize targeted automatic calibration according to the difference of each MEMS chip, and the optimal performance of each MEMS chip is difficult to ensure. According to the application, the FPGA board is used for collecting analog signals transmitted in parallel when each MEMS chip is electrified, and accordingly, each MEMS chip is calibrated, so that the application can realize targeted automatic calibration according to the difference of each MEMS chip, and the optimal performance of each MEMS chip is ensured.
In the actual scenario of testing each MEMS chip, the present application may only select a plurality of parameter sites (which may also be referred to as "test points") to test each axis of the IMU or gyroscope, i.e. the test data is obtained by testing each axis at a plurality of parameter sites. Based on the above, in the process that the FPGA board calibrates each MEMS chip according to the digital signal, for two adjacent parameter sites, the former parameter site is called as a 'previous parameter site', the latter parameter site is called as a 'next parameter site', and before the analog signal is output to the next parameter site, the calibration of the corresponding MEMS chip is completed according to the digital signal generated by the former parameter site, where the FPGA board can judge the state of the MEMS chip in real time and adjust the calibration parameters in real time, and when the calibration is completed, thus ensuring that the data acquired at the test point is more accurate.
Before the FPGA board sends the test data to the MCU, or before the FPGA board analyzes the test data, the application can detect whether the acquisition of the test data is finished or not through the FPGA board, namely, whether the acquisition of the test data of all axes of all MEMS chips is finished or not. If yes, executing the step S4, and if not, continuing to collect the test data until the collection is completed.
In an example, the FPGA board may detect whether the collection of the test data is completed according to the test data and the storage manner thereof. Specifically, in an actual scenario, the test data may be represented as an encapsulation packet, where the encapsulation packet includes a data header, a data type, a source number, a data length, and a data content, where the source number indicates a MEMS chip from which the test data comes, where the FPGA board may first parse the encapsulation packet to obtain data corresponding to each axis from the test data, then create a storage queue for each axis from which the data is obtained, and store the corresponding data, and determine, according to the source number and the number of storage queues, whether the test data of all MEMS chips is received.
The data of the shaft 1 is obtained by parsing the encapsulation packet, the storage queue 1 is created, the data of the shaft 2 is obtained by parsing, the storage queue 2 is created, and the like. Taking MEMS chips as an example for controlling the IMU, firstly determining whether test data come from all MEMS chips according to source numbers, if not, determining that the test data of all the MEMS chips are not received currently, if so, detecting whether the number of the storage queues is equal to the total axis number of the IMU, if so, determining that the test data of all the MEMS chips are received, otherwise, for example, analyzing the data of the axes 1-5 currently, creating the storage queues 1-5, and determining that the number of the storage queues is five and is smaller than the total axis number of the IMU (the total axis number of the IMU is six), and determining that the test data of all the MEMS chips are not received currently.
That is, the application can acquire the data of each axis from the test data through the FPGA board, and creates a storage queue when the data of one axis is acquired, and stores the corresponding data, and then judges whether the test data of all MEMS chips are received according to the source number and the number of the storage queues carried in the test data, thereby automatically realizing the determination of whether the test data is acquired.
In other examples, the application can automatically determine whether the test data is completely acquired through the interconnection between the accessed MEMS chips without any one of an FPGA board, an MCU and a host computer. Specifically, as shown in connection with fig. 5, the method further comprises the following steps:
S11, connecting a plurality of interfaces, selecting one MEMS chip to send out an inquiry packet containing self identification and the number of storage queues, wherein the storage queues are created when data corresponding to each axis are acquired from test data, and each axis creates a storage queue;
S12, after the rest MEMS chips receive the query packet, comparing the current storage queue number with the storage queue number of one MEMS chip;
For any of the remaining MEMS chips, it is detected whether the current number of memory queues per se is less than a preset number of memory queues (which may be referred to as a "preset number of memory queues").
S13, for any one of the remaining MEMS chips, if the number of the current storage queues is smaller than that of the one MEMS chip, sending out an inquiry packet;
S14, for any one of the remaining MEMS chips, if the current number of the storage queues is greater than or equal to the number of the storage queues of one MEMS chip, not sending out an inquiry packet;
repeating the steps S11 to S14 until only one MEMS chip remains, and
And S15, in response to receiving the package transmitted by the last residual MEMS chip, judging that the test data of all the MEMS chips are received, and determining that the collection of the test data is completed.
One MEMS chip can be regarded as an MEMS chip which completes data acquisition on all axes of the MEMS chip, and the current number of the storage queues of any other MEMS chip is smaller than the number of the storage queues of the other MEMS chip, which indicates that the other MEMS chip does not complete data acquisition of all axes.
In the embodiment, a plurality of MEMS chips are interconnected through the FPGA board, whether an inquiry packet is sent out is determined by comparing the number of the storage queues, so that the last MEMS chip sending out the inquiry packet is detected, and after the package packet (namely test data) sent out by the last MEMS chip is detected, the acquisition can be determined to be finished, and the acquisition is not required to be executed by any one of the FPGA board, the MCU and the upper computer, so that the calculation amount of any one of the FPGA board, the MCU and the upper computer can be reduced.
The present application determines the manner in which the remaining MEMS chips are only one, including but not limited to one of the following:
Mode 1. Based on the test data being represented as an encapsulation packet, and the encapsulation packet comprising a data header, a data type, a source number, a data length, and a data content, the present example may set the byte of the source number such that the source number represents the MEMS chip from which the test data came and identifies the last remaining MEMS chip, and the FPGA board determines that the remaining MEMS chip is only one according to the source number.
Mode 2 the FPGA board obtains the maximum time period from the sending of the interrogation packet from one MEMS chip to the receiving of the other MEMS chip before step S15, and determines that the remaining MEMS chips are only one if no interrogation packet is received since the previous detection of the interrogation packet exceeding the maximum time period.
The embodiment of the application also provides a test system of the MEMS chips, which comprises an upper computer, an MCU and an FPGA board, wherein the FPGA board is connected with the MCU, the FPGA board is provided with a plurality of interfaces for being connected with a plurality of MEMS chips, each interface is connected with one MEMS chip, the MCU is connected with the upper computer, and the structure of the test system can be shown by referring to figure 2. And the test of the MEMS chip is executed among the FPGA board, the upper computer and the MCU by the method of any example.
The embodiment of the application also provides a storage medium which stores a test program, and the test program realizes the steps corresponding to the test method of the MEMS chip in any example when being executed by a processor.
The storage medium may include a Read Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, an optical disk, or the like.
The steps in the method for testing the MEMS chip according to the embodiment of the present application can be executed by the program stored in the storage medium, so that the beneficial effects of the method for testing the MEMS chip according to the embodiment of the present application can be achieved, as detailed in the previous embodiment.
In addition, the FPGA board, the communication board, the upper computer and the storage medium provided in the embodiment of the present application are respectively complete devices, and also have structures corresponding to known devices. For example, the FPGA board may be provided with a data packing module, a detection module, an acceleration calculating module, an angular velocity calculating module, and an automatic calibration module as shown in fig. 2, where the data packing module may transmit test data or analysis results to the MCU, the detection module may be used to analyze the test data, etc., the acceleration calculating module may be used to obtain acceleration values of respective axes of the MEMS chip through testing, the angular velocity calculating module may be used to obtain angular velocity values of respective axes of the MEMS chip through testing, the automatic calibration module may be implemented by adapting hardware in an actual scenario, for example, two or more modules may be implemented as one piece of hardware, and one module may be implemented by two or more pieces of hardware.
The foregoing description is only a partial embodiment of the present application and is not intended to limit the scope of the present application, and all equivalent structural modifications made by those skilled in the art using the present description and accompanying drawings are included in the scope of the present application.
Step numbers such as S1 and S2 are used herein for the purpose of more clearly and briefly describing the corresponding contents, and not to constitute a substantial limitation on the sequence, and those skilled in the art may perform S2 first and then S1, etc. when implementing the present application, but these should be within the scope of the present application.
Although the terms first, second, etc. are used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. In addition, the singular forms "a", "an" and "the" are intended to include the plural forms as well. The terms "or" and/or "are to be construed as inclusive, or mean any one or any combination. An exception to this definition will occur only when a combination of elements, functions, steps or operations are in some way inherently mutually exclusive.
Claims (4)
1. A method of testing a MEMS chip for controlling a plurality of axes of an inertial measurement unit IMU or gyroscope, the method comprising:
the FPGA board is connected with the MCU and is connected with a plurality of MEMS chips through a plurality of interfaces of the FPGA board, each interface is connected with one MEMS chip, and the MCU is also connected with the upper computer;
the FPGA board collects analog signals transmitted in parallel when each MEMS chip is powered on;
the FPGA board is used for carrying out analog-to-digital conversion on the acquired analog signals into digital signals;
the FPGA board calibrates each MEMS chip according to the digital signals, and comprises the steps of for two adjacent parameter sites, completing calibration of the corresponding MEMS chip according to the digital signals generated by the previous parameter site before outputting analog signals to the next parameter site;
The FPGA board transmits control instructions received from the upper computer to each MEMS chip in parallel;
The FPGA board receives test data transmitted by each MEMS chip in parallel, the test data is obtained by testing each shaft of the IMU or gyroscope at a plurality of parameter sites, the test data is expressed as a package, the package comprises a data head, a data type, a source number, a data length and a data content, and the source number represents the MEMS chip from which the test data comes;
Judging whether the acquisition of the test data is completed or not, including:
The FPGA board acquires the data of each axis from the test data, creates a storage queue for each axis of the acquired data, stores the corresponding data, and judges whether the test data of all MEMS chips are received according to the source number and the number of the storage queues;
And
S11, connecting the interfaces, selecting one MEMS chip to send out an inquiry packet containing self identification and the number of storage queues, wherein the storage queues are created when the data corresponding to each axis are acquired from the test data, and each axis creates a storage queue;
S12, after the rest MEMS chips receive the query packet, comparing the current storage queue number with the storage queue number of one MEMS chip;
S13, for any one of the remaining MEMS chips, if the number of the current storage queues is smaller than that of the one MEMS chip, sending out an inquiry packet;
S14, for any one of the remaining MEMS chips, if the current number of the storage queues is greater than or equal to the number of the storage queues of one MEMS chip, not sending out an inquiry packet;
the S11 to the S14 are repeatedly executed until the number of the residual MEMS chips is only one, wherein the mode of determining that the residual MEMS chips are only one comprises the steps that the source number also indicates the MEMS chips from which the test data come and the last residual MEMS chip is identified, the FPGA board determines that the residual MEMS chips are only one according to the source number, or acquires the maximum duration of sending an inquiry packet from one MEMS chip to the other MEMS chip and determining that the residual MEMS chips are only one when the inquiry packet is detected to be more than the maximum duration from the previous time and the inquiry packet is not received;
In response to receiving the package transmitted by the last remaining MEMS chip, determining whether test data of all MEMS chips are received;
when the test data of all MEMS chips are received, the acquisition of the test data is determined to be completed;
The FPGA board transmits the test data to the MCU so that the MCU analyzes the test data and transmits an analysis result to the upper computer, or the FPGA board analyzes the test data and transmits an analysis result to the MCU so that the MCU transmits the analysis result to the upper computer.
2. The method of claim 1, wherein each MEMS chip is disposed on the FPGA board, the method further comprising:
the FPGA board is provided with a temperature sensor to detect the current temperature of each MEMS chip;
the FPGA board sends the current temperature to an MCU to judge whether the current temperature reaches a preset temperature or not by the MCU, and generates a trigger instruction when the current temperature is determined to reach the preset temperature;
And the FPGA board responds to the trigger instruction received from the MCU, and executes the step that the FPGA board transmits the control instruction received from the upper computer to each MEMS chip in parallel.
3. The system for testing the MEMS chips is characterized by comprising an upper computer, an MCU and an FPGA board, wherein the FPGA board is connected with the MCU, the FPGA board is provided with a plurality of interfaces for being connected with a plurality of MEMS chips, each interface is connected with one MEMS chip, the MCU is connected with the upper computer, and the test of the MEMS chips is executed among the FPGA board, the upper computer and the MCU by the method as set forth in claim 1 or 2.
4. A storage medium having a test program stored thereon, which when executed by a processor implements the method of testing a MEMS chip according to claim 1 or 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411310362.0A CN118837726B (en) | 2024-09-20 | 2024-09-20 | MEMS chip testing method and system and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411310362.0A CN118837726B (en) | 2024-09-20 | 2024-09-20 | MEMS chip testing method and system and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118837726A CN118837726A (en) | 2024-10-25 |
| CN118837726B true CN118837726B (en) | 2024-12-17 |
Family
ID=93148431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411310362.0A Active CN118837726B (en) | 2024-09-20 | 2024-09-20 | MEMS chip testing method and system and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118837726B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118298900A (en) * | 2024-03-28 | 2024-07-05 | 深圳宏芯宇存储技术有限公司 | Memory chip testing method, memory chip testing device and memory medium |
| CN118519011A (en) * | 2024-07-12 | 2024-08-20 | 星沿科技(杭州)有限责任公司 | CP (control program) testing method and system of RFID (radio frequency identification) chip |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5592612A (en) * | 1995-04-28 | 1997-01-07 | Birk; Yitzhak | Method and apparatus for supplying data streams |
| US6281818B1 (en) * | 1999-05-14 | 2001-08-28 | Diamond Systems Corporation | Automatic auto-calibration system |
| CN105681277B (en) * | 2015-12-28 | 2018-12-04 | 中国科学院计算技术研究所 | A kind of media access control method and system of full duplex radio local area network interior joint |
| CN107621271A (en) * | 2017-10-20 | 2018-01-23 | 北京航天控制仪器研究所 | A kind of inertial platform real-time testing system and method for testing |
| CN112241240B (en) * | 2019-07-19 | 2024-09-10 | 伊姆西Ip控股有限责任公司 | Method, apparatus and computer program product for parallel transmission of data |
| CN110595504A (en) * | 2019-09-09 | 2019-12-20 | 武汉元生创新科技有限公司 | Automatic calibration method and automatic calibration system for inertial measurement unit |
| CN113589142B (en) * | 2021-07-16 | 2024-04-19 | 广东利扬芯片测试股份有限公司 | Optical chip testing device and method based on FPGA |
| CN115656769A (en) * | 2022-10-14 | 2023-01-31 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | FPGA multi-chip parallel test method, device and computer equipment |
| CN117079791A (en) * | 2023-10-17 | 2023-11-17 | 深圳华声医疗技术股份有限公司 | Gyroscope data acquisition method, terminal equipment and computer readable storage medium |
| CN117686880A (en) * | 2023-12-08 | 2024-03-12 | 上海菲莱测试技术有限公司 | Temperature control method, temperature control board card, equipment and medium for integrated circuit aging test |
| CN117740034A (en) * | 2023-12-21 | 2024-03-22 | 上海径准科技有限公司 | Automatic test system of optical fiber gyroscope |
| CN118210771A (en) * | 2024-03-12 | 2024-06-18 | 北醒（北京）光子科技有限公司 | Offline log processing method and device, electronic equipment and storage medium |
-
2024
- 2024-09-20 CN CN202411310362.0A patent/CN118837726B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118298900A (en) * | 2024-03-28 | 2024-07-05 | 深圳宏芯宇存储技术有限公司 | Memory chip testing method, memory chip testing device and memory medium |
| CN118519011A (en) * | 2024-07-12 | 2024-08-20 | 星沿科技(杭州)有限责任公司 | CP (control program) testing method and system of RFID (radio frequency identification) chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118837726A (en) | 2024-10-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5266206B2 (en) | Method for testing an embedded radio transceiver with minimal interaction between the radio transceiver and the host processor during testing | |
| US8417856B1 (en) | High speed sensor data transfer interface | |
| CN108762205B (en) | Laboratory instrument data automatic acquisition and intelligent management and control system | |
| US6034948A (en) | System for testing repeating installation | |
| CN118837726B (en) | MEMS chip testing method and system and storage medium | |
| TW201526563A (en) | System and method for data packet transceiver testing after signal calibration and power settling to minimize test time | |
| US20030084363A1 (en) | Bus interface | |
| JP7383053B2 (en) | Bus monitoring methods, storage media and electronic devices | |
| JP2004126688A (en) | Offline diagnosis system | |
| CN111830396A (en) | Chip test system with chip test environment temperature detection function | |
| KR20090030363A (en) | Embedded device test system and method | |
| CN117079791A (en) | Gyroscope data acquisition method, terminal equipment and computer readable storage medium | |
| Khalilzad et al. | FPGA implementation of real-time Ethernet communication using RMII interface | |
| CN112947383B (en) | Satellite simulation test system for data stream multi-directional transmission | |
| Gis et al. | Advanced debugging architecture for smart inertial sensors using sensor-in-the-loop | |
| Weiß | Identification of Bottlenecks in the Control Loop of a Robot and Optimizations | |
| CN1909499B (en) | A multi-channel data acquisition device and method | |
| KR20130131024A (en) | Automation system and method for testing embedded device using independent interface | |
| CN113341227A (en) | Instruction system for measuring Doppler spread spectrum and control method | |
| CN102141411B (en) | Method for asynchronously acquiring data of optical fiber gyroscope | |
| CN112212778B (en) | Deformation monitoring device, application method, equipment and medium | |
| US11589139B2 (en) | Method for checking, evaluation, and/or error diagnosis of a sensor system, sensor system, and system | |
| CN120631665A (en) | Automated test configuration method and system | |
| CN121255549A (en) | Data verification methods, devices, electronic equipment and storage media | |
| US7673121B2 (en) | Circuit for monitoring a microprocessor and analysis tool and inputs/outputs thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |