CN1186992A - Automatic identifying method for high speed moving object mark - Google Patents

Abstract

After the the detector detected object enters the specific region, under the action of trigger signal the detected object transmits the coded signal (word string), which is received by the wireless receiver. Through checking and automatic error-correcting treatment, it is sent to the computer network, then the computer network locates the detected object and conducts the corresponding management treatment. Said invention is suitable for the admini stration of high way vehicles and railway rolling stocks and checking the stolen vehicle by high way system.

Description

A kind of automatic identifying method of high speed moving object mark and system and device thereof

The present invention relates to a kind of automatic identifying method and system and device thereof of high speed moving object mark

By high-speed moving object (mainly being various vehicles) is discerned, and cooperate corresponding management system, just can improve the ability to work and the efficient of existing highway traffic and public security system.What realize similar functions is that 1984, the inventor participated in the monitoring of highway communication over-speed vehicles and the number plate of vehicle photographing optical system of design, has once realized the unmanned of highway part management work.But there is following shortcoming in it:

1, is subjected to the moving object speed limit, especially takes and form under-exposure easily at night;

2, rainy day or muddy road conditions next can't take clear:

3, problem such as display result immediately.

Thereafter also there is same problem in the television pickup system of Chu Xianing.Therefore also limited its range of application.

For overcoming above-mentioned deficiency, the invention provides a kind of practical automatic identifying method and device thereof to high speed moving object mark.

For achieving the above object, the present invention has adopted following technical scheme:

A kind of automatic recognition system device of high speed moving object mark comprises transmitter unit and receiving element, and the transmitter of transmitter unit is installed on the testee by the mechanical fixation method, in order to transmit coded signals; The Communication Control trigger is installed, after entering this district, by the work of fixed frequency emission start trigger signal transmitter at the detection testee on the fixed position in regulation zone; The receiver of receiving element is directly installed on the work ground, is connected with terminal through signal cable.

A kind of automatic identifying method of high speed moving object mark comprises the steps: that a. installs the Communication Control trigger on the fixed position in regulation zone, by fixed frequency emission trigger pip; B. in monitored moving object, transmitter is installed, transmit coded signals under the control of Communication Control trigger; C. transmit monitored moving object numbering by the wireless digital signal communication,,, transmit to computer network through verification and necessary automatic correction process by receiver received code word string; D. computer network is to testee location and carry out corresponding management processing.

The invention will be further described below in conjunction with accompanying drawing

Fig. 1 system of the present invention forms synoptic diagram

The power supply of Fig. 2 transmitter and driving circuit figure

The coding memory of Fig. 3 transmitter and transmitter logic control circuit figure

The radiating circuit figure of Fig. 4 transmitter

Fig. 5 receiver antenna circuit and data head detecting circuit figure

Fig. 6 receiver receiving code buffer-stored and store control logic circuit diagram

The verification of Fig. 7 receiver, error correction circuit and RS232 hardware layer agreement interface circuit figure

Fig. 8 computer management network synoptic diagram

Shown in Fig. 1 frame of broken lines, the native system device comprises by the mechanical fixation method and is installed in transmitter 2 on the testee, the Communication Control trigger on the fixed position in regulation zone, installed 1 and be directly installed on the ground receiver 3 of work, the 1 emission start trigger signal work of Communication Control trigger.Transmitter 2 sends coded signal to receiver 3, and receiver sends computer network to through signal cable and carries out the practical work processing.The Communication Control trigger:

Be used for determining testee enters the trigger of fixed area can be for contact and contactless sensor be arranged, all can as capacitive proximity sensor, light sensor, Hall element etc., environmental baseline decision type selecting (when testee is big by density, but touching the transmitter continuous working) according to the equipment fabricating yard.Sensor detect object (vehicle) near the time, by fixed frequency emission trigger pip, the work of start trigger signal transmitter.

Transmitter:

Transmitter is installed on the testee by the mechanical fixation method.Its power supply also uses standby power supply except that using vehicle power supply, the transmission semiotic function when stopping working with the assurance vehicle.

The embodiment of transmitter circuit such as Fig. 2, Fig. 3, shown in Figure 4:

Fig. 2 is power supply and driving circuit (PKG E1)

1. antenna A1 receives trigger pip process Q1, the Q2 amplification that trigger sends, and integrated circuit (IC) 1 (FSK) driver (resistance R 1 to R6 is delivered in the Q3 detection; Capacitor C 1 to C10; Potentiometer P1, P2 are and realize the necessary device of phase-locked loop circuit).Signal is imported from IC1 the 6th pin.When trigger pip arrived, integrated circuit (IC) 6 the 16th pin was output as high level, made the timing in the 1 beginning T1 time interval of integrated circuit (IC) 6 (monostable oscillator) timer.Integrated circuit (IC) 6 the 3rd pin is a high level in this time interval, and 119:A is reverse through integrated circuit (IC), and integrated circuit (IC) 1 is not powered, and driver is closed.

2. at T1 in the time interval, the input end of integrated circuit (IC) 4:B and IC4:C (Sheffer stroke gate) is "-", and another input end initial state is "-", and then the output of two Sheffer stroke gates is "+".

3.a integrated circuit (IC) 4:C output high level makes the timing in the 2 beginning T2 time intervals of integrated circuit (IC) 7 (monostable oscillator) timer, surveys in the T2 time interval to busy (busy) detector power supply of line.

Whether 3.b integrated circuit (IC) 4:B output high level makes integrated circuit (IC) 2, busy (busy) detector power supply of IC3 (FSK) line enter duty, surveying has other transmitter to send signal and busy channel (during initial state primary channel being surveyed).

4. other transmitter signal transmitted is through antenna A1, amplifier Q1, Q2 amplify, the Q3 detection, deliver to integrated circuit (IC) 2, IC3 (FSK) the 6th pin, make integrated circuit (IC) 2 and IC3 the 16th pin be output as high level, reverse through Sheffer stroke gate integrated circuit (IC) 4:A output low level and integrated circuit (IC) 4:A, the busy high level signal of expression line deliver letters change-over circuit and timer 2.

5.a the line busy signal is delivered to channel switcher, produce positive pulse through Zener diode Z1 and capacitor C 14, go into integrated circuit (IC) 9:B and make channel memory (JK flip-flop) upset, the 12nd pin output positive potential, related switch closure makes resistance R 16, C22 in parallel with R12, C24.The Q3 detection transfers second channel (alternate channel) to.

5.b the line busy signal is delivered to timer 2 the 4th pin timer 2 is resetted, timing restarts timing from 0.Integrated circuit (IC) 2, busy (busy) detector of IC3 (FSK) line are surveyed the alternate channel signal.

If 5.c alternate channel is occupied in the time interval at T2, signal by 5.a, two steps of 5.b, makes channel transfer primary channel to equally; Timing restarts from 0.Because signal transmission time and testee are very little by frequency ratio.This channel switch number of times is not more than three times.

6. wireless busy signal resets timer in the timing time interval of timer 2, timer 2 the 3rd pin is output as low level, 4:D is reverse through the Sheffer stroke gate integrated circuit (IC), power, power to radiating circuit (PKGE3) to coded stack and transmitter logic control circuit (PKG E2) by plug SK2 the 1st pin, close integrated circuit (IC) 2, the busy detector of IC3 line simultaneously by plug SK3 the 1st pin.

7. obtain from PKG E2 when plug SK2 the 2nd pin and send end signal (seeing that PKG E2 introduces), the upset of integrated circuit (IC) 9:A trigger, the 15th pin output positive potential makes integrated circuit (IC) 4:D output low level.PKGE2, PKG E3 quit work.

Since 1 time interval of timer not then as yet, integrated circuit (IC) 1 driver is still closed.Through T1 after the time interval trigger just can be triggered once more.

9. power circuit.When external power supply+12V powers, the triode conducting, related switch adhesive, open the contact, and the back-up source battery is not worked.When external power supply removed, triode ended, and related switch discharges, the closing of contact, and the back-up source battery is started working.

Fig. 3 is coded stack and transmitter logic control circuit (PKG E2)

10. described by 6., after PKG E2 entered emission state, clock was started working.Integrated circuit (IC) 201 (multivibrator) provides cp (time clock).During initial state, integrated circuit (IC) 202, IC203 address counter are 00000.

11.a memory integrated circuit IC204 (EPROM) provides the address moving hand according to address counter, send integrated circuit (IC) 206 (triple gate) with the data order.

11.b when cp was high level, integrated circuit (IC) 206 oppositely was high-impedance state through IC119:F, cp pulse simultaneously makes the address counter counting, and address pointer moves; Integrated circuit (IC) 209 (VCO) obtains voltage by R10, R9 divider resistance and vibrates, and its oscillator signal is a synchronizing signal, send PKG E3 emission radio frequency synchronizing signal by SK2.

11.c when cp is low level, integrated circuit (IC) 206 is sent data-signal to bus, integrated circuit (IC) 208, IC209 obtain the vibration that relevant voltage produces assigned frequency according to the corresponding bit data of bus, send PKG E3 emission rf data head communication protocol signal or data word signal by SK2.

11.d repeat 11.a, 11.b, 11.c step, send whole communication protocol signals or data word signal by turn.

12.a integrated circuit (IC) 206 is sent data-signal by bus to integrated circuit (IC) 210:A to IC213:A odd-even counter (JK flip-flop) to the VCO feed signals simultaneously, makes the odd-even counter upset of bus position correspondence.

12.b (for example address counter is that 01111 agreement finishes) odd-even counter resets when communication protocol signal finishes.Repeat 11.a, 11.b, 11.c step transmission data word signal later on, and data-signal is carried out parity count.

12.c Q2, the Q3 position of integrated circuit (IC) 203 address counters are high level after sending data-signal for the first time and finishing, reverse through integrated circuit (IC) 119:D, IC119:D, give integrated circuit (IC) 214, IC215 (BUFFER incorporate into go here and there out impact damper) the 1st pin pulse through integrated circuit (IC) 206:B, IC119E and D15, C4, R17 differential, with odd-even counter data sending buffer, send out fully as check word.Continue to repeat 11.a, 11.b, 11.c step transmission data word signal later on, data-signal is carried out parity count.

13.a integrated circuit (IC) 119:D, IC119:B are output as low level after sending data-signal for the second time and finishing, integrated circuit (IC) 206:B, IC119:E are reverse, produce verification and allow signal.

13.b verification allows signal to make integrated circuit (IC) 207:B and input end low level of IC207:D, its output is by another input end decision.

13.c it is high level that verification allows signal to make integrated circuit (IC) 206:C the 9th pin, pulse is by integrated circuit (IC) 206:C input, send integrated circuit (IC) 214, IC215 impact damper the 2nd pin, make data serial output in the impact damper, send another input end of integrated circuit (IC) 207:B, D12 and another input end of integrated circuit (IC) 207:D, D13 respectively.When integrated circuit (IC) 214, when IC215 impact damper the 2nd pin is output as high level, VCO is by D12, the D13 power taking living assigned frequency oscillator signal of cutting down output.IC214, when IC215 impact damper the 2nd pin is output as low level, VCO cuts down output by integrated circuit (IC) 207:B output terminal, D11 and IC207:D output terminal, D7 power taking and gives birth to other assigned frequency oscillator signal.

13.d oscillator signal repeats the 13.c step and send PKG E3 emission check word signal by SK2.

14. after check word was sent completely, integrated circuit (IC) 202, IC203 address counter were 110100.Obtain sending the termination request signal through integrated circuit (IC) 119:C, IC119B, IC119:D, IC206:B, IC206:C logical operation, stop sending through SK2 the 2nd pin PKG E1.Fig. 4 is radiating circuit (PKG E3)

15 radiating circuits are got positive potential by SK2 the 1st pin from PKG E1 and are entered duty.Channel selecting signal is obtained from PKG E1 by SK2 the 2nd pin.

16.CRY and L301, R4, integrated circuit (IC) 302:A, IC302:C, IC302:D produce rf oscillation signal.

17.a when channel selecting signal was expressed as primary channel, the RS1 switch disconnected, integrated circuit (IC) 302:A is defeated. go out to be low level.Radio-frequency oscillator produces frequency signal and directly send frequency mixer.

17.b when channel selecting signal was expressed as alternate channel, it was high level that RS1 switch closure, integrated circuit (IC) 302:A are output as the 5th pin.Oscillator signal is through the C3 feed-in, because the effect of integrated circuit (IC) 302:A difference frequency, radio-frequency oscillator produces frequency-doubled signal and send frequency mixer.

18. amplify through integrated circuit (IC) 1 in data head communication protocol signal, data word signal school or test the word signal and obtained from PKG E2 by SK2, with IC302:D output mixing, is sent by Q1 and antenna circuit.

Communications protocol:

Adopt double frequency coding, can calculate in theory more than its encoding scheme quantity.Have 576 kinds for 4 * 4, have 144 kinds for 4 * 3 realize that the hardware design of encoding scheme is countless especially.Can not all enumerate at this.Be the explanation circuit, following three the communication coding layer protocols of special affirmation:

(1) the communication frequency composite design is 4 * 3 tables, as Fig. 2:

Synchronizing pulse adopts the H4 frequency.

(2) serial data of transmitter emission is data head communication protocol signal (16 words), first data word (16 words), retransmission data word (16 words), parity check word (4 words).As Fig. 3.

(3) the coded data head is: #@@#@@#@@@@#@@@@.

(4) clock uses high frequency the 4th frequency (H4).Low-frequency range no signal when clock occurs.

(5) parity check word is made up of four words (4 words), represents four frequencies of low frequency and three frequency odd evens of high frequency numerical value respectively.And H1 and L1 represent odd number respectively.

The course of work of transmitter:

Transmitter receipt starts the transmitter trigger circuit and makes transmitter enter standby condition behind the signal of Communication Control detector, carries out channel and selects; Clock provides pulse signal; Get interior coding by the pointer counter controls from storer, the process bus enters the low-and high-frequency signal oscillator and power amplification, antenna are sent radiofrequency signal.

When launching the prefix of word string, the verification counting is disregarded number.

During emission word string coded signal, the monitor counter counting.

After the coded signal emission was finished, checking signal entered oscillator, frequency mixer, power amplifier and antenna by bus, the emission checking signal.

At last, transmitter cuts out.

The embodiment of acceptor circuit such as Fig. 5, Fig. 6, shown in Figure 7.Fig. 5 is antenna circuit and data head detecting circuit (PKG R1)

1. the transmitter signal transmitted receives through antenna A1, and amplifier Q1, Q2 amplify, and integrated circuit (IC) 106, IC107...IC113 are delivered in Q3 detection (seeing the transmitter circuit introduction for details).All according to being connected into (FSK) circuit shown in the integrated circuit (IC) 106, its centre frequency is corresponding with L1, L2, L3, L4, H1, H2, H3 and H4 frequency for the joining resistance of each integrated circuit, electric capacity, potentiometer, and its frequency range is narrower than the emission frequency range.Advance circuit the 6th pin by the antenna FD feed, every position that is encoded to ＂ 1 ＂, the 16th pin of its corresponding integrated circuit (IC) is output as high level.Integrated circuit (IC) 106 is sent into PKG R2 to the digital signal of integrated circuit (IC) 113 outputs by data bus.

2. integrated circuit (IC) 101 is formed the data head detecting circuit to integrated circuit (IC) 105.According to the regulation of communications protocol, take out signal (L1H1) by integrated circuit (IC) 105:B and IC104:D, send counter integrated IC circuit 102, make it to reset.Take out # signal (L1, H1) by integrated circuit (IC) 105:A and IC104:C, send rolling counters forward.When continuous four " # " of data head 8-11 position appearred in bus, integrated circuit (IC) 102 the 11st pin was a high level.Integrated circuit (IC) 101 Q end is high level.12 of data head signals reset integrated circuit (IC) 102, and data head 13--16 position makes integrated circuit (IC) 102 the 11st pin be high level once more.Reverse through integrated circuit (IC) 103:A and IC103:D, make an integrated circuit (IC) 104:A output data end signal.The data head end signal divides three path effects:

102:B is reverse by integrated circuit (IC), and (RST) sends into PKG R2 through the control line that resets;

103:B is reverse by integrated circuit (IC), makes integrated circuit 1C102:B take out clock signal (integrated circuit (IC) 102:B make pulse signal reverse) from data bus, and (Cp) send PKG R2 through the time clock line;

Cut off other data head signal by the low level that integrated circuit (IC) 104:C and IC104:D output keep.

Fig. 6 is receiving code buffer-stored and store control logic circuit (PKG R2)

3. form positive pulse by capacitor C 3, resistance R 3 and make integrated circuit (IC) 203, IC203 counter O reset by reset reset signal that control line (RST) comes of PKG R1; Make integrated circuit (IC) 210:A, IC 210:B, IC211:A, IC211:B, IC212:A, IC212:B, the zero clearing of IC213:A odd-even counter through integrated circuit (IC) 206:B.

4. the clock pulse signal by PKG R1 time clock line (Cp) send when low level:

Signal send integrated circuit (IC) 203 the 13rd pin, makes the data bus writing data into memory.

Signal send triple gate integrated circuit (IC) 202 the 1st pin and the 15th pin, and the data bus data are counted by sending odd-even counter from triple gate.All is the corresponding JK flip-flop upset of data bit driving of " 1 ".

The clock pulse signal that is come by PKG R1 time clock line (Cp) send the pointer counter at high level, makes pointer add " 1 ", and by address bus control integrated circuit IC202 pen travel.

5. repeat 4. first data word (16 words), retransmission data word (16 words), the parity check word (4 words) of finishing serial data.

6. first data word finishes receiving when 16 pulses of address counter to the (being output as 0,001 0000), and the first data word odd even is taken a sample.Time clock makes integrated circuit (IC) 209:C output high level, forms pulse through resistance R 1, capacitor C 1, send integrated circuit (IC) 214 the 1st pin.The odd-even counter count results is sent into integrated circuit (IC) 214.

7. second data word finishes receiving when 32 pulses of address counter to the (being output as 0,010 0000), to receiving the odd even sampling.Time clock makes integrated circuit (IC) 209:C output high level, through IC218 the result of odd-even counter NAND operation is taken out, when twice reception result is inconsistent, integrated circuit (IC) 218 output low levels, integrated circuit (IC) 216 the 11st pin high level, IC213 the 10th pin low level keeps stable, the memory of integrated circuit (IC) 213 JK flip-flop.

The 32nd pulse (being output as 0,010 0000) forms pulse to the odd-even counter zero clearing by capacitor C 3, resistance R 3.

When address counter IC223 be parity word verification sampling when receiving the 33rd pulse to the 36 pulses (being output as 0,010 0001 to 0,010 0101).

During the 33rd pulse, solve 0,010 0001 address, make data bus L1 value deposit IC210:A in by integrated circuit (IC) 206:A by integrated circuit (IC) 205:G and IC208:D; Make data bus H1 value deposit integrated circuit (IC) 212:A in simultaneously by integrated circuit (IC) 207:A.

During the 34th pulse, solve 0,010 0010 address, make data bus L2 value deposit integrated circuit (IC) 210:B in by integrated circuit (IC) 206:B by integrated circuit (IC) 205:E and 209:A; Make the total H2 value of data deposit integrated circuit (IC) 212:B in simultaneously by integrated circuit (IC) 207:B.

During the 35th pulse, solve 0,010 0011 address, make data bus L3 value deposit integrated circuit (IC) 211:A in by integrated circuit (IC) 206:C by integrated circuit (IC) 205:E, 219:B and IC209:B; The special data bus H3 value that makes deposits integrated circuit (IC) 213:A in by integrated circuit (IC) 207:C.

During the 36th pulse, solve 0,010 0100 address, make data bus L4 deposit IC211:B in by integrated circuit (IC) 206:D by integrated circuit (IC) 205:B.

The 36th pulse back edge is by integrated circuit (IC) 205:B, 219:B and IC215:C, and the output high level forms pulse through resistance R 2, capacitor C 2, send integrated circuit (IC) 215 the 1st pin.The odd-even counter count results is sent into integrated circuit (IC) 215.

So far, PKG R2 takes a sample and has stored three groups of parity datas. comprise first data word odd even sampling (having IC214) in 6.; 7. in by the parity word verification (having IC215) of reception in IC 213 memory and 8..

Fig. 7 is verification error correction circuit and RS232 hardware layer agreement interface circuit (PKG R3)

9. when IC213 the 10th pin high level, the data word that expression receives for the first time is consistent with the data word that receives for the second time.Expression receives correct.

When IC213 the 10th pin low level, the data word that expression receives for the first time is inconsistent with the data word that receives for the second time.Need verification and error correction by turn:

By PKG R2 START, send into pulse to IC303 (JK flip-flop), making 15 pin is high level, makes IC304 produce pulse.Isochrone is busy to be high level (BUSY).Impulse meter IC306 carries out eight step-by-step countings; Pass through the related switch (RELAY SWICH) of single-pole double-throw (SPDT) simultaneously, send pulse to PKG R2 by control line Cp.

The Cp pulse enters IC214 and IC215 the 2nd pin, make the specified number of IC214 and IC215 storage export according to serial, by the bitwise operation of IC217 " XNOR ", compare leaving the first data word odd even sample among the IC214 and the parity check word among the IC215 in.When first data word and the parity check word defeated high level of IC217 simultaneously not, making IC213 the 11st pin through IC216:A is low level.Confirm that the data word that receives for the second time is correct.

When first data word and every homogeneous phase while of parity check word, IC217 fails low level, and making IC213 the 11st pin through IC216:A is high level.Confirm that the data word that receives for the first time is correct.

10. after eight step-by-step countings, high level send PK6 R2 by set line (SET EN), oppositely send IC204 the 12nd pin by IC209:D with IC213 the 11st pin current potential.Realize error correction.

11.IC306 after counting 1000, the Q3 position is a high level, the related switch of single-pole double-throw (SPDT) changes the knot normal opened contact, and pulse send PKG R2 to make IC203, IC204 address counter control IC202 pen travel by the Cp1 control line.

Q3 position high level makes output control line) OE) high level, IC202 the 22nd pin, IC302 the 1st, 19 pin, IC302 the 13rd pin change, and the correct data that receives in the IC202 is transmitted among the IC302.

12. IC308 the 12nd pin saltus step after the transmission of 16 digital data words is finished is exported pulses through four gate circuits of IC301 and is made the upset of IC301 trigger.Terminating number reportedly send.Address pointer keeps original position.

The BUSY line recovers low level.Computer Communication Networks visit ready.

13. when running into the BUSY high level during computer network access receiver, or address pointer is positioned at data when top, computing machine is waited for.

14. after computer network had been got data, address pointer was the data tops.Receiver communication coding regulation must be stipulated identical with transmitter:

Adopt double frequency coding, can calculate in theory more than its encoding scheme quantity.Have 576 kinds for 4 * 4, have 144 kinds for 4 * 3 realize that the hardware design of encoding scheme is countless especially.Can not all enumerate at this.Be the explanation circuit, following five the communication coding layer protocols of special affirmation are example:

(1) news frequency rate composite design is 4 * 3 tables, as Fig. 2;

Synchronizing pulse adopts the H4 frequency.

(2) serial data of transmitter emission is data head communication protocol signal (16 words), first data word (16 words), retransmission data word (16 words), parity check word (4 words).

(3) the coded data head is: #@@#@@#@@@@#@@@@.

(4) clock uses high band the 4th frequency (H4).Low-frequency range no signal when clock occurs.

(5) parity check word is made up of four words (4 words), represents four frequencies of low frequency and three frequency odd evens of high frequency numerical value respectively.And H1 and L1 represent that respectively high band and low-frequency range are odd number.

It is that computing machine at first proposes to collect the signal application under computer network control that receiver transmits the signal operation to computer network, and receiver is replied and realized communication under the situation of permission.Communication is carried out according to procotol.

Can adopt dedicated line, the communication of telephone line frequency division or power carrier mode with computer network communication.

Computer management network

Computer network is an important component part of giving full play to the GCS function.This patent only with regard to network major part---distributed database structure synoptic diagram (Fig. 8) is illustrated:

General distributed computer database system is divided into three layers, and central control computer is made up of the computing machine of or the machine work of several All-China Federation of Taiwan Compatriots, manages with extraneous communication with to some regional computers.Management work comprises issues an order and retrieves, calls data and overall operation status analysis.Should increase hardware in case of necessity and implement, as the vehicle deceleration warning notice etc. of travelling.

Auto Express-way Toll Collector System should be carried out clearing automatically with finance, Banking sector, needs central control computer to be responsible for and extraneous swap data and subpoena.

Every regional computer is downwards in the face of some terminal control units.Database in the regional computer is deposited a considerable amount of data retaining cases, for the management work inquiry; Need finish daily statistics, form and planning.In carrying out search mission (following the trail of stolen vehicle as public security system), regional computer is born definite target location, the task of evaluating objects movement tendency; Between the regional computer and between regional computer and the terminal machine, all be in the duty of real-time control at this moment.

Terminal machine is upward to a certain regional computer, downwards in the face of several receivers.It can store the data of some, and the data of the collection of time in accordance with regulations receiver reception, periodically transmits data to regional computer.When network was carried out search mission, terminal machine was in the real-time working state.

More than be the explanation of system and device, do an explanation with the example that is applied as of freeway management below.

The course of work of single-point sampling application mode:

All vehicles near the location measuring point, trigger under number driving at the detector letter, the transmitter that is installed on the vehicle is launched wireless communication signal to being installed in ground receiver, after receiver received signal and verification, the error correction, by computer system the vehicle coding is implemented login.

In the automatic fare collection system of expressway, expressway entrance and exit all marks off " green channel ", and the login of vehicle coding confirms that vehicle can directly pass through from green channel.Computer network enters and leaves the position of highway according to vehicle, automatically clearing.

The multi-point sampling application mode:

Receiver is installed near highway fixed position along the line (alarm call) is surveyed reception vehicular traffic coded signal.Similar to the course of work of single-point sampling application mode.

Computer simulation system is made up of hardware and computer software.Following four objective relations about vehicle operating and time can be proposed under its software effect:

1. the motion conditions of vehicle on highway is the relation of reflection type of vehicle, vehicle condition, driver's state;

2. same vehicle is in highway motion conditions and time correlation;

3. pass through the vehicle density and the time correlation of each observation station (receiver installation place);

4. concern between adjacent observation station and be correlated with.

Can set up the wagon flow state that norm is described highway according to above-mentioned 4.

When notable difference appears in above-mentioned relation and norm, then must there be following incident to take place and needs and handle:

1. when individual (certain vehicle) when arriving next measuring point in advance, the behavior of driving over the speed limit in this location of this car of network-reporting.

2. when individuality can not arrive next measuring point, this car of network-reporting had fault or accident to take place in this location.

3. when part individual (several cars) in the time of can not arriving next measuring point, this location of network-reporting has accident to take place.

4. when certain measuring point wagon flow was overstocked, there was accident potential in this location of network-reporting.Need dredge.

5. when certain measuring point does not have wagon flow, network-reporting has than major break down in this location and takes place.

The invention has the advantages that:

The present invention is not only applicable to above-mentioned highway administration, also is applicable to seizing of rolling stock management and public security system Look into stolen vehicle, be applicable to that also other need to be to the automatic identification occasion of high speed moving object mark. This device can be applied in expressway tol lcollection mouth (application of single-point sample mode) can realize charging, charge from Movingization; Vehicle discrepancy highway needn't stop, but energy savings reduces and pollutes. Along the line at highway Receiver and corresponding computer simulation system (the multi-point sampling mode is used) are set, can realize highway fortune The row Real-Time Monitoring, block up the forecast and dredge, accident alarming (quality time that acquisition is given first aid to the wounded). Should To be used for public security system can position and follow the trail of stolen vehicle, is applied to railway and can realizes rolling stock Operation monitoring. Can solve left unguarded and the warning of management crossing and level crossing.

Claims (3)

1. the automatic recognition system device of a high speed moving object mark comprises transmitter unit and receiving element, it is characterized in that:

The transmitter of transmitter unit is installed on the testee by the mechanical fixation method, in order to transmit coded signals;

The Communication Control trigger is installed, after entering this zone, by the work of fixed frequency emission start trigger signal transmitter at the detection testee on the fixed position in regulation zone;

The receiver of receiving element is directly installed on the work ground, is connected with terminal through signal cable.

2. the automatic recognition system of high speed moving object mark as claimed in claim 1, it is characterized in that: described trigger can adopt contact and contactless sensor.When testee is big by density, but continuous working.

Transmitter receipt starts the transmitter trigger circuit and makes transmitter enter standby condition behind the signal of Communication Control detector, carries out channel and selects; Clock provides pulse signal: get interior coding by the pointer counter controls from storer, the process bus enters the low-and high-frequency signal oscillator and power amplification, antenna are sent radiofrequency signal.

The receiver trigger circuit adopt discrete component and integrated circuit splicing, its power supply uses outside the 220V power supply, and also standby ups power, receiver start after receiving the prefix signal of transmitter, enter standby condition, detect with clock signal through excessive sign indicating number and separate received encoded signal.

In the receiving course, receiver carries out three check code samplings.Through verification and automatic correction process (if it is wrong to transmit coding), transmit to computer network then.

3. the automatic identifying method of a high speed moving object mark is characterized in that comprising the steps: a, and the Communication Control trigger is installed on the fixed position in regulation zone, by fixed frequency emission trigger pip; B installs transmitter in monitored moving object, transmit coded signals under the control of Communication Control trigger; C transmits monitored moving object numbering by the wireless digital signal communication, by receiver received code word string, through verification and necessary automatic correction process, transmits to computer network; The d computer network is to the testee location and carry out corresponding management processing.

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