CN118629957A - Semiconductor device manufacturing method, semiconductor device, memory and electronic equipment - Google Patents
Semiconductor device manufacturing method, semiconductor device, memory and electronic equipment Download PDFInfo
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Abstract
The application provides a semiconductor device manufacturing method, a semiconductor device, a memory and electronic equipment. The method comprises the following steps: etching the substrate to form at least one active structure; the active structure comprises a first active part and a second active part; forming a first transistor of a first semiconductor structure based on the first active portion; performing subsequent process treatment on the first transistor to form a first interconnection layer, wherein at least one storage structure is formed in the first interconnection layer; the storage structure is connected with the source-drain metal structure of the first transistor; rewinding and removing the remaining substrate to expose the second active portion; forming a second transistor of a second semiconductor structure based on the second active portion; performing subsequent process treatment on the second transistor to form a second interconnection layer; at least one memory structure is formed in the second interconnection layer, and the memory structure is connected with the source-drain metal structure of the second transistor.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a method for manufacturing a semiconductor device, a memory, and an electronic device.
Background
While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors further increase transistor integration density by integrating two or more layers of transistors in vertical space is one of the important technologies continuing the scaling of integrated circuits.
Disclosure of Invention
The application provides a preparation method of a semiconductor device, the semiconductor device, a memory and electronic equipment, so as to improve the integration density of the memory.
According to a first aspect of an embodiment of the present application, there is provided a method for manufacturing a semiconductor device, including:
Etching the substrate to form at least one active structure; wherein the active structure comprises a first active portion and a second active portion; the first active portion is remote from the substrate relative to the second active portion;
forming a first transistor of a first semiconductor structure based on the first active portion; the first semiconductor structure comprises at least one first standard cell, and each first standard cell comprises one first transistor;
Performing subsequent process treatment on the first transistor to form a first interconnection layer; at least one storage structure is formed in the first interconnection layer; the storage structure is connected with the first source-drain metal structure of the first transistor;
rewinding and removing the remaining substrate to expose the second active portion;
Forming a second transistor of a second semiconductor structure based on the second active portion; the second semiconductor structure comprises at least one second standard cell, each second standard cell comprising one of the second transistors;
Performing subsequent process treatment on the second transistor to form a second interconnection layer; at least one storage structure is formed in the second interconnection layer; the memory structure is connected with the second source-drain metal structure of the second transistor.
According to a second aspect of an embodiment of the present application, there is provided a semiconductor device including:
A substrate;
A first semiconductor structure located on a first surface of the substrate, the first semiconductor structure including at least one first standard cell, each of the first standard cells including: a first transistor;
A second semiconductor structure located on the second surface of the substrate, the second semiconductor structure being disposed opposite to the first semiconductor structure, the second semiconductor structure including at least one second standard cell, each of the second standard cells including: a second transistor;
a plurality of memory structures located within a first interconnect layer of the first semiconductor structure and a second interconnect layer of the second semiconductor structure, respectively;
Wherein the memory structure in the first interconnect layer is connected to a first source drain metal structure of the first transistor; the memory structure within the second interconnect layer is connected to a second source drain metal structure of the second transistor.
According to a third aspect of an embodiment of the present application, there is provided a memory including: a semiconductor device according to a second aspect of an embodiment of the present application.
According to a fourth aspect of an embodiment of the present application, there is provided an electronic apparatus including: the circuit board and the memory shown in the third aspect of the embodiment of the application are arranged on the circuit board.
The preparation method of the semiconductor device comprises the steps of etching a substrate to form at least one active structure; and forming a first transistor of a first semiconductor structure based on a first active portion in the active structure; performing subsequent process treatment on the first transistor to obtain a first interconnection layer containing a storage structure; the memory structure in the first interconnection layer is connected with the first source-drain metal structure of the first transistor; after the first semiconductor structure is reworked, forming a second transistor of a second semiconductor structure based on a second active part in the active structure, and performing subsequent process treatment on the second transistor to obtain a second interconnection layer containing a storage structure; the memory structure in the second interconnection layer is connected with a second source-drain metal structure of the second transistor; the first semiconductor structure and the second semiconductor structure are made to be of a back-to-back design, so that the volume of a semiconductor device (e.g., DRAM, RRAM, etc.) comprising at least one transistor and at least one memory structure is reduced, and the integration density is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the present application;
Fig. 2 is a schematic structural view of a semiconductor device according to an embodiment of the present application;
fig. 3 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present application;
Fig. 4 to 10 are schematic views showing a manufacturing process of a semiconductor device according to an embodiment of the present application;
Fig. 11 is a schematic diagram of a semiconductor device according to a second embodiment of the present application;
Fig. 12 is a schematic structural view of a capacitor according to an embodiment of the present application;
fig. 13 is a schematic structural view of a semiconductor device of a plurality of different memory types shown according to an embodiment of the present application.
In the above figures: 10, a semiconductor device; 11, a first semiconductor structure; a second semiconductor structure; 13, a substrate; 14, an active structure; 15, shallow trench isolation; 151, shallow trench isolation layer; 14a, a first active portion; 14b, a second active portion; a first gate trench 16; t1, a first transistor; t2, a second transistor; 17 a storage structure; 171, a capacitor; 171a, a first electrode; 171b, a capacitive dielectric layer; 171c, a second electrode; 172, a resistive memory structure; 173, mtj memory structure; 174, pcm storage structure; 175, ferroelectric capacitor; 111, a first source drain structure; 112, a first interlayer dielectric layer; 113, a first gate structure; 114, a first source drain metal structure; 115, a first gate dielectric layer; 116, first spacers; 117, a first interconnect layer; 1171, a first interconnect dielectric layer; 1172, a first interconnect metal structure; 121, a second source drain structure; 122, a second interlayer dielectric layer; 123, a second gate structure; 124, a second source drain metal structure; 125, a second gate dielectric layer; 126, second spacers; 127, a second interconnect layer; 1271, a second interconnect dielectric layer; 1272, a second interconnect metal structure;
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.
While moore's law is continually deepening, continuing to advance transistor scaling after the technology node of the full-round gate transistor (GAA) is a hot spot problem currently being developed in the industry.
The embodiment of the application provides a semiconductor device and a preparation method thereof, and the preparation method can be used for preparing the semiconductor device. In the embodiment of the application, the semiconductor device can be applied to semiconductor devices such as memories, processors and the like.
In some embodiments, the semiconductor device may be a stacked flip-chip transistor.
The semiconductor device comprises a first semiconductor structure and a second semiconductor structure which are arranged oppositely; it should be noted that, since the first semiconductor structure and the second semiconductor structure are disposed back-to-back and stacked on each other, in the embodiment of the present application, the first semiconductor structure may also be referred to as a front-side transistor, and the second semiconductor structure may also be referred to as a back-side transistor. Accordingly, each device in the front-side transistor may also be referred to as a front-side device, e.g., a first source-drain metal structure in a first semiconductor structure may be referred to as a front-side source-drain metal structure, and similarly, a second source-drain metal structure in a second semiconductor structure may be referred to as a back-side source-drain metal structure.
In the embodiment of the application, the first semiconductor structure and the second semiconductor structure in the semiconductor device can be transistors of the same type, such as any one of the following: planar transistors, fin field effect transistors (FIN FIELD EFFECT transistors, finfets), full-Around Gate transistors (Gate-All-Around FIELD EFFECT transistors, GAAFET), and the like, the types of the first semiconductor structure and the second semiconductor structure are not particularly limited, and the embodiments of the present application may be other types of transistors.
In the following, a first semiconductor structure and a second semiconductor structure are taken as example of FinFET, and fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the present application. For ease of understanding, only the active structure, the gate structure, and the source-drain metal structure are shown in the top view. Fig. 2 is a schematic structural view of a semiconductor device according to an embodiment of the present application; wherein (a) in fig. 2 shows a cross-sectional view of the semiconductor device along the direction of a broken line A-A' in fig. 1; fig. 2 (B) shows a cross-sectional view of the semiconductor device along the direction of a broken line B-B' in fig. 1; fig. 2 (C) shows a cross-sectional view of the semiconductor device along the direction of a broken line C-C' in fig. 1.
As shown in fig. 2, the semiconductor device includes: a substrate 13, a first semiconductor structure 11 and a second semiconductor structure 12; wherein the first semiconductor structure 11 is located on the first surface of the substrate 13; the second semiconductor structure 12 is located at a second surface of the substrate 13. It is understood that the first semiconductor structure 11 and the second semiconductor structure 12 are disposed opposite to each other.
Wherein the first semiconductor structure 11 comprises at least one first standard cell, each of the first standard cells comprising: a first transistor T;
The second semiconductor structure 12 comprises at least one second standard cell, each of the second standard cells comprising: a second transistor T2;
a plurality of memory structures 17 located within the first interconnect layer 117 of the first semiconductor structure 11 and the second interconnect layer 127 of the second semiconductor structure 12, respectively;
The memory structure 17 within the first interconnect layer 117 is connected to the first source drain metal structure 114 of the first transistor T1; the memory structure 17 within the second interconnect layer 127 is connected to the second source drain metal structure 124 of the second transistor T2.
The following describes a method for manufacturing a semiconductor device according to an embodiment of the present application with reference to the semiconductor structure shown in fig. 2.
Fig. 3 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present application. Referring to fig. 3, the preparation method at least includes the following steps:
Step S301, etching a substrate to form at least one active structure; the active structure comprises a first active part and a second active part; the first active portion is remote from the substrate relative to the second active portion;
step S302, forming a first transistor of a first semiconductor structure based on the first active part;
Step S303, performing subsequent process treatment on the first transistor to form a first interconnection layer; at least one memory structure is formed within the first interconnect layer; the memory structure is connected with the first source-drain metal structure of the first transistor;
step S304, rewinding and removing the reserved substrate to expose the second active part;
step S305 of forming a second transistor of a second semiconductor structure based on the second active portion;
step S306, performing subsequent process treatment on the second transistor to form a second interconnection layer; at least one memory structure is formed in the second interconnection layer; the memory structure is connected with the second source drain metal structure of the second transistor.
It should be noted that the steps shown in fig. 1 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations; the steps shown in fig. 1 can be sequentially adjusted according to actual requirements.
Fig. 4 to 10 are schematic views illustrating a process of manufacturing a semiconductor device according to an embodiment of the present application, and for ease of understanding, the drawings in fig. 4 to 10 only show cross-sectional views along the dotted lines A-A ', B-B ' and C-C ' of fig. 1. A first method for manufacturing a semiconductor device according to an embodiment of the present application will be exemplarily described with reference to fig. 2 to 10.
In step S101, referring to fig. 4 and 5, a substrate 13 may be provided first, and at least one active structure 14 may be formed by etching the substrate 13.
In the embodiment of the present application, the substrate may be a silicon substrate, or may be a silicon-on-insulator (SOI) substrate, or may be a substrate of other semiconductor materials, which is not particularly limited in the embodiment of the present application.
The SOI substrate is provided with a buried oxide (Buried Oxide, BOX) layer between a top silicon layer and a back silicon layer. The SOI substrate can realize dielectric isolation of components in the integrated circuit and eliminate parasitic latch-up effect in the bulk silicon CMOS circuit. The integrated circuit prepared by the SOI substrate has the advantages of small parasitic capacitance, high integration density, high speed, simple process, small short channel effect, particular suitability for low-voltage low-power-consumption circuits and the like, and the isolation of the first semiconductor structure and the second semiconductor structure can be effectively realized in the embodiment of the application.
In some embodiments, when the transistor types of the first semiconductor structure, the second semiconductor structure are different, the arrangement of the substrate is correspondingly different. For example, when the first semiconductor structure and the second semiconductor structure are planar transistors or finfets, the substrate may be a silicon substrate. When the first semiconductor structure and the second semiconductor structure are GAAFET, the substrate may be a stack of alternating depositions of silicon and silicon germanium (SiGe).
It should be noted that, the etching process mentioned in the embodiments of the present application may include, but is not limited to, one of the following: dry etching, wet etching, reactive ion etching, and chemical oxide removal processes.
It will be appreciated that the patterning of the active structure is performed by standard process steps and the substrate is etched to obtain at least one active structure.
Here, the active structure may include: a first active portion and a second active portion; wherein the first active portion is farther from the substrate than the second active portion. The first active portion and the second active portion are formed by the same etching process.
When the first semiconductor structure and the second semiconductor structure in the semiconductor device are FinFETs, the active structure is a fin structure; when the first semiconductor structure and the second semiconductor structure in the semiconductor device are GAAFET, the active structure is a nano-sheet structure; when the first semiconductor structure and the second semiconductor structure in the semiconductor device are planar transistors, the active structure is a bulk structure.
In some embodiments, before forming the first semiconductor structure based on the first active portion, the method further comprises:
depositing an insulating material over the active structure and the substrate to form shallow trench isolation (Shallow Trench Isolation STI);
The first portion of the shallow trench isolation is removed to expose a first active portion of the active structure.
As shown in fig. 5, shallow trench isolation 15 is formed by depositing an insulating material over active structure 14 and substrate 13, and it is noted that shallow trench isolation 15 encapsulates active structure 14.
The insulating material forming the shallow trench isolation may be any of the following: silicon nitride (SiN, si 3N4), silicon dioxide (SiO 2), silicon oxycarbide (SiCO), or the like, which is not particularly limited in the embodiments of the present application.
In order to facilitate subsequent processing, after the shallow trench isolation is formed, polishing or chemical-mechanical planarization (CMP) may be performed on the shallow trench isolation, so that when the shallow trench isolation is etched subsequently, the corresponding etching depths of the shallow trench isolation in different areas are the same, so that the heights of the tops of the exposed active structures are the same.
The shallow trench isolation may be divided into an upper portion and a lower portion, and the upper portion (i.e., the first active portion) of the active structure may be exposed by etching the upper portion (i.e., the first portion) of the shallow trench isolation.
In step S102, a previous process (e.g., forming an isolation, a gate structure, a source-drain structure, etc.) may be performed based on the first active portion to form a first transistor of the first semiconductor structure.
It is noted that the first semiconductor structure includes at least one first standard cell, each first standard cell including: a first transistor.
In some embodiments, step S102 includes:
etching a portion of the first active portion corresponding to a gate region of the first transistor to form a first gate trench;
Depositing a semiconductor material on the first active portion to form a first dummy gate structure of the first transistor;
Forming a first source-drain structure of the first transistor based on the first active portion;
depositing a semiconductor material on the first active part and the first source drain structure to form a first interlayer dielectric layer;
Removing the first dummy gate structure to expose the first gate trench;
forming a first gate structure of the first transistor based on the first gate trench;
And removing a part of the first interlayer dielectric layer to form a first source drain metal structure.
In an embodiment of the present application, as shown in fig. 6, after the first active portion 14a of the active structure is exposed, a portion of the first active portion 14a may be etched to form the first gate trench 16.
In some embodiments, a first gate trench is formed in the first active portion at a location corresponding to a gate region of the first transistor.
It is noted that the first gate trench may be formed by etching a portion of the first active portion corresponding to the gate region of the first transistor. The channel of the first transistor is changed into a curve channel instead of a linear channel by utilizing the first grid groove, so that the equivalent grid length of the channel is increased, the electric leakage is reduced, and the holding time is prolonged.
Here, the shape of the first gate trench is not limited in the embodiment of the present application, for example, the first gate trench may be a U-shaped trench.
After forming the first gate trench, the first active portion may be doped, and an active region of the first transistor may be formed. The doping ions of the first active portion may include n-type ions (e.g., nitrogen ions, phosphorus ions, arsenic ions, etc.) and/or P-type ions (e.g., boron ions, gallium ions, indium ions, etc.).
The first gate dielectric layer and the first gate structure can be formed by at least one of the processes of film deposition, etching, thermal oxidation and the like, and the first source drain structure can be formed by at least one of the processes of epitaxy, doping and the like, so that the manufacture of the first transistor is completed.
The material of the first gate dielectric layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, and the like, and the material of the first gate metal structure includes a conductive material, for example, tungsten nitride, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, polysilicon, doped polysilicon, and the like.
It is noted that the first gate structure of the first transistor is located in the first gate trench; the two first source-drain structures of the first transistor are respectively positioned at two sides of the first grid electrode groove.
It should be noted that, for convenience of description, the first source-drain structure in the embodiment of the present application is referred to as simply, and specifically refers to a first source structure and/or a first drain structure. In addition, the second source-drain structure, the first source-drain metal structure, the second source-drain metal structure, the source-drain groove and the like are similar to those of the first source-drain structure, wherein 'source-drain' is abbreviated as 'source electrode and/or drain electrode'.
In an embodiment of the present application, after forming the first gate trench, a gate region of the first transistor may be opened by photolithography, and a semiconductor material (e.g., polysilicon (Poly Si)) may be deposited in the gate region of the first transistor to form a first dummy gate structure of the first transistor.
In some embodiments, as shown in fig. 7, after forming the first dummy gate structure (not shown), an insulating material may be deposited on both sides of the first dummy gate structure to form first spacers 116.
Here, the insulating material forming the first spacer may include, but is not limited to: silicon nitride, silicon carbide, and/or silicon oxynitride, etc.
In some embodiments, as shown in fig. 7, forming the first source-drain structure 111 of the first transistor T1 based on the first active portion 14a includes: along the extending direction of the first active portion 14a, a portion of the first active portion 14a is etched, and a first source-drain structure 111 is formed.
It will be appreciated that a portion of the first active portion may be removed by etching, and a source drain recess of the first transistor may be provided. And forming a strained material such as silicon germanium or silicon carbide in the source-drain groove of the first transistor by using the first spacer as a mask through selective epitaxy so as to fill the source-drain groove of the first transistor, and then forming a first source-drain structure on the strained material through a heavy doping process.
As shown in fig. 7, after forming the first source-drain structure 111, a semiconductor material may be deposited over the first active portion 14a and the first source-drain structure 111, forming a first interlayer dielectric layer 112. Note that the first interlayer dielectric layer 112 may cover the first active portion 14a and the first source drain structure 111.
The first dummy gate structure is removed by etching to expose a gate region of the first transistor to expose a first gate trench in the gate region of the first transistor.
In some embodiments, forming a first gate structure of the first transistor based on the first gate trench includes:
a metal material is deposited in the first gate trench to form a first gate structure of the first transistor.
Here, the metal material forming the first gate structure may include, but is not limited to: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN).
In some embodiments, as shown in fig. 7, before preparing the first gate structure, the method further comprises: a semiconductor material is deposited on the surface of the first active portion 14a to form a first gate dielectric layer 115 of the first transistor T1, the first gate dielectric layer 115 being used to isolate the first active portion 14a from the first gate structure 113.
In some embodiments, as shown in fig. 7, removing a portion of the first interlayer dielectric layer to form a first source drain metal structure includes:
Etching a partial region of the first interlayer dielectric layer 112 above the first source drain structure 111 until the upper surface of the first source drain structure 111 is exposed, so as to form a first source drain metal groove;
A metal material is deposited in the first source drain metal recess to form a first source drain metal structure 114.
In step S303, after the fabrication of the first transistor is completed, a subsequent process may be performed to form a first interconnect layer. The first interconnect layer is used to electrically bring out the first transistor.
In some embodiments, a subsequent process may be performed over the first interlayer dielectric layer to form a first interconnect layer.
It is noted that in embodiments of the present application, the first interconnect layer includes at least one memory structure; each memory structure is connected with a first source drain metal structure of one first transistor.
It should be noted that the memory type of the first semiconductor structure is different, and the memory structure in the first semiconductor structure is different. Illustratively, when the memory type of the first semiconductor structure is a dynamic random access memory (Dynamic Random Access Memory, DRAM), the memory structure within the first semiconductor structure is a capacitor. When the memory type of the first semiconductor structure is a variable resistance random access memory (RESISTIVE RANDOM ACCESS MEMORY, RRAM), the memory structure in the first semiconductor structure may be a memory structure corresponding to the RRAM.
In some embodiments, the memory type of the first semiconductor structure may be, but is not limited to, one of: a DRAM; RRAM; -a magnetoresistive random access memory (Magnetoresistive Random Access Memory, MRAM); a phase change Memory (PHASE CHANGE Memory, PCM); ferroelectric random access memory (Ferroelectric Random Access Memory, feRAM).
In some embodiments, a subsequent process is performed on the first transistor to form a first interconnect layer, comprising:
Performing subsequent process treatment on the upper side of the first source drain structure of the first transistor to form a first interconnection layer; wherein the first interconnect layer comprises: one or more first interconnect dielectric layers, and a first interconnect metal structure within the first interconnect dielectric layers;
Etching a portion of the one or more first interconnect dielectric layers to form a via;
Forming a storage structure based on the through hole; the memory structure is in contact with the first source drain metal structure, or the memory structure is in contact with the first source drain metal structure through at least one first interconnection metal structure.
It will be appreciated that the storage structure may be a columnar or cylindrical storage structure; thus, a via may be formed by selectively etching one or more first interconnect dielectric layers within a first interconnect layer and disposing the memory structure within the via.
In some embodiments, a portion of the plurality of first interconnect dielectric layers may be etched until the first source drain metal structure is exposed, forming a via;
forming the storage structure based on the through hole; the memory structure is in contact with the exposed first source drain metal structure.
In some embodiments, as shown in fig. 8, a portion of at least one first interconnect dielectric layer 1711 may be etched until first interconnect metal structure 1172 is exposed, forming a via; wherein the first interconnect metal structure 1172 is in contact with the first source drain metal structure 114;
forming the storage structure 17 based on the via hole; the memory structure 17 is in contact with the exposed first interconnect metal structure 1172.
In step S304, after the subsequent processing of the first semiconductor structure is completed, a rewinding process may be performed on the first semiconductor structure such that the bottom substrate is placed upward. The substrate is removed to expose the shallow trench isolation and a surface of the second active portion remote from the first semiconductor structure to facilitate subsequent fabrication of the second semiconductor structure.
In some embodiments, the rewinding and removing the remaining substrate to expose the second active portion includes:
depositing an insulating material on top of the first semiconductor structure after forming the first semiconductor structure to form a first insulating layer;
bonding the first insulating layer to the carrier wafer;
rewinding the first semiconductor structure;
the substrate is removed to expose the second active portion.
It is understood that the first insulating layer is bonded to the carrier wafer by forming the first insulating layer on top of the first semiconductor structure; therefore, the bonded carrier wafer is utilized to provide physical support for the first semiconductor structure after rewinding, and the first semiconductor structure is effectively prevented from being broken due to external force in the process of preparing the second semiconductor structure.
In some embodiments, removing the substrate to expose the second active portion includes:
and removing the reserved second parts of the substrate and the shallow trench isolation to expose the second active part.
As shown in fig. 9, after the first semiconductor structure 11 is reworked, the bottom substrate may be removed by a wafer thinning process and a planarization process (e.g., a CMP process), wherein the CMP process stops at the surface of the shallow trench isolation 15 such that the surface of the second active portion 14b is exposed therewith. After the bottom substrate is removed, a second portion of the shallow trench isolation 15 may be removed by etching to expose the second active portion 14b.
As shown in fig. 9, in the process of etching the shallow trench isolation 15, a shallow trench isolation with a predetermined height may be left to be used as the shallow trench isolation 151; it is understood that a shallow trench isolation layer is located between the first gate structure of the first transistor and the second gate structure of the second transistor for isolating the first gate structure and the second gate structure.
In step S305, as shown in fig. 9 and 10, a previous process treatment (e.g., forming an isolation, a gate structure, a source-drain structure, etc.) may be performed based on the second active portion 14b to form a second transistor T2 of the second semiconductor structure 12.
It is noted that as shown in fig. 10, the second semiconductor structure 12 includes at least one second standard cell, each of which includes: a second transistor T2.
In some embodiments, step S305 includes:
Etching a portion of the second active portion corresponding to a gate region of the second transistor to form a second gate trench;
depositing a semiconductor material on the second active portion to form a second dummy gate structure of the second transistor;
forming a second source-drain structure of the second transistor based on the second active portion;
Depositing a semiconductor material on the second active part and the second source drain structure to form a second interlayer dielectric layer;
removing the second dummy gate structure to expose the second gate trench;
forming a second gate structure of the second transistor based on the second gate trench;
and removing a part of the second interlayer dielectric layer to form a second source drain metal structure.
In an embodiment of the present application, after exposing the second active portion of the active structure, a portion of the second active portion may be etched to form a second gate trench.
In some embodiments, a second gate trench is formed in the second active portion at a location corresponding to a gate region of the second transistor.
It is noted that the second gate trench may be formed by etching a portion of the second active portion corresponding to the gate region of the second transistor. The channel of the second transistor is changed into a curve channel instead of a linear channel by utilizing the second grid groove, so that the equivalent grid length of the channel is increased, the electric leakage is reduced, and the holding time is prolonged.
Here, the shape of the second gate trench is not limited in the embodiment of the present application, for example, the second gate trench may be a U-shaped trench.
After forming the second gate trench, the second active portion may be doped, and an active region of the second transistor may be formed. The doping ions of the second active portion may include n-type ions (e.g., nitrogen ions, phosphorus ions, arsenic ions, etc.) and/or P-type ions (e.g., boron ions, gallium ions, indium ions, etc.).
The second gate dielectric layer and the second gate structure can be formed by at least one of the processes of film deposition, etching, thermal oxidation and the like, and the second source drain structure can be formed by at least one of the processes of epitaxy, doping and the like, so that the manufacture of the second transistor is completed. The material of the second gate dielectric layer may be similar to the material of the first gate dielectric layer, and the material of the second gate metal structure may be similar to the material of the first gate metal structure.
It is noted that the second gate structure of the second transistor is located in the second gate trench; two second source-drain structures of the second transistor are respectively positioned at two sides of the second grid electrode groove.
In an embodiment of the present application, after forming the second gate trench, a gate region of the second transistor may be opened by photolithography, and a semiconductor material, such as polysilicon (Poly Si), may be deposited in the gate region of the second transistor to form a second dummy gate structure of the second transistor.
In some embodiments, after forming the second dummy gate structure, an insulating material may be deposited on both sides of the second dummy gate structure to form a second spacer (spacer).
Here, the insulating material forming the second spacer may include, but is not limited to: silicon nitride, silicon carbide, and/or silicon oxynitride, etc.
In some embodiments, forming a second source drain structure of the second transistor based on the second active portion includes: and etching a part of the second active part along the extending direction of the second active part, and forming a second source drain structure.
It will be appreciated that a portion of the second active portion may be removed by etching, and a source drain recess of the second transistor may be provided. And forming a strained material such as silicon germanium or silicon carbide in the source-drain grooves of the second transistor by selective epitaxy by taking the second spacer as a mask so as to fill the source-drain grooves of the second transistor, and then forming a second source-drain structure on the strained material by a heavy doping process.
After forming the second source drain structure, a semiconductor material may be deposited over the second active portion and the second source drain structure to form a second interlayer dielectric layer. It is noted that the second interlayer dielectric layer may cover the second active portion and the second source drain structure.
And removing the second dummy gate structure by etching to expose the gate region of the second transistor so as to expose the second gate trench in the gate region of the second transistor.
In some embodiments, forming a second gate structure of the second transistor based on the second gate trench includes:
A metal material is deposited in the second gate trench to form a second gate structure of the second transistor.
Here, the metal material forming the second gate structure may include, but is not limited to: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN).
In some embodiments, between preparing the second gate structure, the method further comprises: and depositing a semiconductor material on the surface of the second active part to form a second gate dielectric layer of the second transistor, wherein the second gate dielectric layer is used for isolating the second active part and the second gate structure.
In some embodiments, removing a portion of the second interlayer dielectric layer to form a second source drain metal structure includes:
Etching a partial region of the second interlayer dielectric layer above the second source drain structure until the upper surface of the second source drain structure is exposed, so as to form a second source drain metal groove;
And depositing a metal material in the second source-drain metal groove to form a second source-drain metal structure.
In step S306, after the fabrication of the second transistor is completed, a subsequent process may be performed to form a second interconnect layer. The second interconnect layer is for electrically extracting the second transistor.
In some embodiments, a subsequent process may be performed over the second interlayer dielectric layer to form a second interconnect layer.
Notably, at least one memory structure is formed within the second interconnect layer; each memory structure is connected to a second source drain metal structure of one of the second transistors.
It should be noted that the memory type of the second semiconductor structure is different, and the memory structure in the second semiconductor structure is different. Illustratively, when the memory type of the second semiconductor structure is DRAM, the memory structure within the second semiconductor structure is a capacitor. When the memory type of the second semiconductor structure is RRAM, the memory structure in the second semiconductor structure may be a memory structure corresponding to RRAM.
In some embodiments, the memory type of the second semiconductor structure may be, but is not limited to, one of: a DRAM; RRAM; MRAM; PCM; feRAM.
In some embodiments, a subsequent process treatment is performed on the second transistor to form a second interconnect layer, comprising:
Performing subsequent process treatment above the second source drain structure of the second transistor to form a second interconnection layer; wherein the second interconnect layer comprises: one or more second interconnect dielectric layers, and a second interconnect metal structure within the second interconnect dielectric layers;
etching a portion of the one or more second interconnect dielectric layers to form a via;
forming a storage structure based on the through hole; wherein the memory structure is in contact with the second source drain metal structure or the memory structure is in contact with the second source drain metal structure through at least one second interconnect metal structure.
It will be appreciated that the storage structure may be a columnar or cylindrical storage structure; whereby a via may be formed by selectively etching one or more of the second interconnect dielectric layers of the second interconnect layer and the memory structure is disposed within the via.
In some embodiments, a portion of the plurality of second interconnect dielectric layers may be etched until the second source drain metal structure is exposed, forming a via;
forming the storage structure based on the through hole; the memory structure is in contact with the exposed second source drain metal structure.
In some embodiments, a portion of the at least one second interconnect dielectric layer may be etched until the second interconnect metal structure is exposed, forming a via; the second interconnection metal structure is in contact with the first source-drain metal structure;
Forming the storage structure based on the through hole; the memory structure is in contact with the exposed first interconnect metal structure.
As shown in fig. 11 and 12, fig. 11 is a schematic diagram of a semiconductor device according to an embodiment of the present application. Fig. 12 is a schematic structural diagram of a capacitor according to an embodiment of the present application.
In some embodiments, the storage structure 17 is a capacitor 171;
the forming the storage structure based on the through hole includes:
A first electrode 171a, a capacitance medium layer 171b, and a second electrode 171c are sequentially formed in the through hole to constitute the capacitor 171 by the first electrode 171a, the capacitance medium layer 171b, and the second electrode 171 c; wherein the first electrode 171a is in contact with the first interconnect metal structure 1172 or the second interconnect metal structure 1272.
In the embodiment of the present application, the memory types of the first semiconductor structure and the second semiconductor structure may be DRAMs, and the memory structure may be a capacitor.
After forming the through hole, the first electrode may be formed in the through hole first, for example, the first electrode may be formed by deposition;
Here, the first electrode may be selected from, but not limited to, metal such as tantalum nitride, titanium nitride, tungsten, gold, aluminum, or polysilicon. Notably, the first electrode covers the bottom and sidewalls of the via, and the first electrode is in contact with the first interconnect metal structure or the second interconnect metal structure.
After forming the first electrode, an oxide material is deposited over the first electrode to cover the first electrode, forming a capacitive dielectric layer.
In some embodiments, the material of the dielectric layer may be a high dielectric constant (K) material. The material of the high-k dielectric layer includes hafnium oxide (HfO 2), zirconium oxide (ZrO 2), aluminum oxide (Al 2O 3) or tantalum oxide (Ta 2O 5).
Finally, a second electrode is formed on the capacitance medium layer, for example, the second electrode can be formed in a deposition mode.
Here, the second electrode may be selected from, but not limited to, tantalum nitride, titanium nitride, tungsten, gold, aluminum, or the like, or polysilicon, or the like. It is noted that the second electrode covers the capacitive dielectric layer and the second electrode completely fills the via.
It is understood that within the first semiconductor structure, the first electrode of the capacitor is in contact with the first source drain metal structure of the first transistor through the first interconnect metal structure. In the second semiconductor structure, the first electrode of the capacitor is in contact with the second source-drain metal structure of the second transistor through the second interconnection metal structure.
An embodiment of the present application provides a memory, including: the semiconductor device of the above embodiment. The specific limitation of the semiconductor device may be referred to the semiconductor device shown in fig. 2, and will not be described herein.
In some embodiments, the memory may be a DRAM memory.
In other embodiments, the memory may be, but is not limited to being, one of: RRAM memory, MRAM memory, PCM memory, and FeRAM memory.
As shown in fig. 13, fig. 13 is a schematic structural view of a semiconductor device of a plurality of different memory types according to an embodiment of the present application. It should be noted that the drawing in fig. 13 shows only a cross-sectional view along the broken line C-C' in fig. 1. Fig. 13 (a) is a semiconductor device of the RRAM memory type, which is a resistance change memory structure 172; fig. 13 (b) is a semiconductor device of the MRAM memory type, the memory structure being a magnetic tunnel junction (Magnetic Tunnel Junction, MTJ) memory structure 173; fig. 13 (c) is a semiconductor device of the PCM memory type, and the memory structure is a PCM memory structure 174; fig. 13 (d) is a semiconductor device of FeRAM memory type, and the memory structure is a ferroelectric capacitor 175.
An embodiment of the present application provides an electronic device, including: the circuit board and the memory as in the above embodiments, the memory is disposed on the circuit board. The memory includes the semiconductor device described above. The semiconductor structure may be specifically defined by referring to the semiconductor device shown in fig. 2, and will not be described herein.
The semiconductor device and the preparation method thereof provided by the embodiment of the application can be applied to the next generation of integrated circuit manufacturing process and have great application potential.
The features disclosed in the embodiments of the device provided by the application can be combined arbitrarily without conflict to obtain new embodiments of the device.
The methods disclosed in the method embodiments provided by the application can be arbitrarily combined under the condition of no conflict to obtain a new method embodiment.
In the description of the embodiments of the present application, the descriptions of the terms "one embodiment," "an example," "a particular example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in the present application and the features of the various embodiments or examples may be combined by those skilled in the art without contradiction.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (13)
1. A method of manufacturing a semiconductor device, comprising:
Etching the substrate to form at least one active structure; wherein the active structure comprises a first active portion and a second active portion; the first active portion is remote from the substrate relative to the second active portion;
forming a first transistor of a first semiconductor structure based on the first active portion; the first semiconductor structure comprises at least one first standard cell, and each first standard cell comprises one first transistor;
Performing subsequent process treatment on the first transistor to form a first interconnection layer; at least one storage structure is formed in the first interconnection layer; the storage structure is connected with the first source-drain metal structure of the first transistor;
rewinding and removing the remaining substrate to expose the second active portion;
Forming a second transistor of a second semiconductor structure based on the second active portion; the second semiconductor structure comprises at least one second standard cell, each second standard cell comprising one of the second transistors;
Performing subsequent process treatment on the second transistor to form a second interconnection layer; at least one storage structure is formed in the second interconnection layer; the memory structure is connected with the second source-drain metal structure of the second transistor.
2. The method of claim 1, wherein performing a subsequent process on the first transistor forms a first interconnect layer, comprising:
Performing subsequent process treatment on the upper side of the first source drain structure of the first transistor to form a first interconnection layer; wherein the first interconnect layer comprises: one or more first interconnect dielectric layers, and a first interconnect metal structure within the first interconnect dielectric layers;
Etching a portion of the one or more first interconnect dielectric layers to form a via;
Forming the storage structure based on the through hole; wherein the memory structure is in contact with the first source-drain metal structure or the memory structure is in contact with the first source-drain metal structure through at least one first interconnect metal structure.
3. The method of claim 1, wherein performing a subsequent process on the second transistor to form a second interconnect layer comprises:
Performing subsequent process treatment above the second source-drain structure of the second transistor to form a second interconnection layer; wherein the second interconnect layer comprises: one or more second interconnect dielectric layers, and a second interconnect metal structure within the second interconnect dielectric layers;
Etching a portion of the one or more second interconnect dielectric layers to form a via;
Forming the storage structure based on the through hole; wherein the memory structure is in contact with the second source-drain metal structure or the memory structure is in contact with the second source-drain metal structure through at least one second interconnect metal structure.
4. A method according to claim 2 or 3, wherein the storage structure is a capacitor;
the forming the storage structure based on the through hole includes:
Sequentially forming a first electrode, a capacitance medium layer and a second electrode in the through hole to form the capacitor through the first electrode, the capacitance medium layer and the second electrode; wherein the first electrode is in contact with the first interconnect metal structure or the second interconnect metal structure.
5. A method according to any one of claims 1 to 3, wherein the rewinding and removing the retained substrate to expose the second active portion comprises:
depositing an insulating material on top of the first semiconductor structure after forming the first semiconductor structure to form a first insulating layer;
bonding the first insulating layer to the carrier wafer;
rewinding the first semiconductor structure;
the substrate is removed to expose the second active portion.
6. The method of claim 1, wherein forming a first transistor of a first semiconductor structure based on the first active portion comprises:
etching a portion of the first active portion corresponding to a gate region of the first transistor to form a first gate trench;
Depositing a semiconductor material on the first active part to form a first pseudo gate structure of the first transistor;
Forming a first source-drain structure of the first transistor based on the first active portion;
Depositing a semiconductor material on the first active part and the first source drain structure to form a first interlayer dielectric layer;
removing the first dummy gate structure to expose the first gate trench;
forming a first gate structure of the first transistor based on the first gate trench;
And removing a part of the first interlayer dielectric layer to form a first source drain metal structure.
7. The method of claim 1, wherein forming a second transistor of a second semiconductor structure based on the second active portion comprises:
Etching a portion of the second active portion corresponding to a gate region of the second transistor to form a second gate trench;
depositing a semiconductor material on the second active portion to form a second dummy gate structure of the second transistor;
forming a second source-drain structure of the second transistor based on the second active portion;
Depositing a semiconductor material on the second active part and the second source drain structure to form a second interlayer dielectric layer;
removing the second dummy gate structure to expose the second gate trench;
forming a second gate structure of the second transistor based on the second gate trench;
and removing a part of the second interlayer dielectric layer to form a second source drain metal structure.
8. A semiconductor device, characterized in that, the semiconductor device includes:
A substrate;
A first semiconductor structure located on a first surface of the substrate, the first semiconductor structure including at least one first standard cell, each of the first standard cells including: a first transistor;
A second semiconductor structure located on the second surface of the substrate, the second semiconductor structure being disposed opposite to the first semiconductor structure, the second semiconductor structure including at least one second standard cell, each of the second standard cells including: a second transistor;
a plurality of memory structures located within a first interconnect layer of the first semiconductor structure and a second interconnect layer of the second semiconductor structure, respectively;
Wherein the memory structure in the first interconnect layer is connected to a first source drain metal structure of the first transistor; the memory structure within the second interconnect layer is connected to a second source drain metal structure of the second transistor.
9. The semiconductor device of claim 8, wherein the first interconnect layer comprises: one or more first interconnect dielectric layers, and a first interconnect metal structure within the first interconnect dielectric layers;
the second interconnect layer includes: one or more second interconnect dielectric layers, and a second interconnect metal structure within the second interconnect dielectric layers;
a plurality of said memory structures within said first interconnect dielectric layer and said second interconnect dielectric layer, respectively;
A memory structure within the first interconnect dielectric layer is in contact with the first source drain metal structure; or the storage structure in the first interconnection dielectric layer is contacted with the first source-drain metal structure through the first interconnection metal structure;
A memory structure within the second interconnect dielectric layer is in contact with the second source drain metal structure; or the memory structure in the second interconnection dielectric layer is contacted with the second source-drain metal structure through the second interconnection metal structure.
10. The semiconductor device of claim 9, wherein the memory structure is a capacitor; the capacitor includes:
A first electrode located within a via of the first interconnect dielectric layer and/or the second interconnect dielectric layer and covering a bottom and sidewalls of the via; the first electrode is in contact with the first interconnect metal structure or the second interconnect metal structure;
a second electrode on the first electrode;
And the capacitance medium layer is positioned between the first electrode and the second electrode.
11. The semiconductor device according to claim 8, wherein the first transistor comprises:
a first gate trench formed in the first active portion at a position corresponding to a gate region of the first transistor; the first active part is used for forming the first transistor;
A first gate structure located in the first gate trench;
The two first source-drain structures are respectively positioned at two sides of the first grid electrode groove;
The second transistor includes:
a second gate trench formed in a second active portion at a position corresponding to a gate region of the second transistor; the second active portion is used for forming the second transistor;
a second gate structure located in the second gate trench;
and the two second source-drain structures are respectively positioned at two sides of the second grid electrode groove.
12. A memory, comprising: a semiconductor device as claimed in any one of claims 8 to 11.
13. An electronic device, comprising: a circuit board and a memory according to claim 12, the memory being provided to the circuit board.
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