CN118626428A

CN118626428A - Bandwidth allocation method, server, device, medium and program product

Info

Publication number: CN118626428A
Application number: CN202411104838.5A
Authority: CN
Inventors: 陈衍东; 李道童; 艾山彬; 王凯鹏
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2024-08-13
Filing date: 2024-08-13
Publication date: 2024-09-10

Abstract

The invention relates to the technical field of servers, and discloses a bandwidth allocation method, a server, equipment, a medium and a program product, wherein the method comprises the following steps: monitoring a PCIe interface of the central processing unit in an initialization stage of initializing the PCIe device; judging whether the first device information is the same as the second device information or not under the condition that the first device information is acquired based on a first channel of the PCIe interface and the second device information is acquired based on a second channel of the PCIe interface; determining that the first channel and the second channel correspond to the same PCIe device when the first channel and the second channel are the same, and feeding back acknowledgement signals based on the first channel and the second channel respectively; and performing bandwidth allocation according to the corresponding relation between the PCIe interface and the PCIe equipment. The invention obtains the device information uploaded by the corresponding PCIe device based on the channel of the PCIe interface, can determine the related information of the PCIe device, and performs bandwidth allocation, and has simple implementation mode.

Description

Bandwidth allocation method, server, device, medium and program product

Technical Field

The present invention relates to the field of server technologies, and in particular, to a bandwidth allocation method, a server, a device, a medium, and a program product.

Background

PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion card standard, which is mainly used for connecting a CPU (central processing unit) with various expansion cards, such as a video card, a sound card, a network adapter and the like. The bandwidth of PCIe is closely related to its version and Lane number. For example, the theoretical maximum bandwidth of the PCIe x1 slot is 1GB/s, and the PCIe x1 slot is suitable for equipment with low data transmission requirements; the theoretical maximum bandwidth of the PCIe x4 slot is 4GB/s, and the PCIe x4 slot is suitable for equipment with medium bandwidth requirements; the theoretical maximum bandwidth of the PCIe x8 slot is 8GB/s, and the PCIe x8 slot is suitable for equipment with higher requirements on data transmission speed; PCIe x16 slots have the highest theoretical maximum bandwidth of 16GB/s and are widely used for connecting high performance graphics cards.

The PICe interfaces on the server motherboard generally adopt PCIe x8 slots or PCIe x16 slots, when PCIe devices with small Lane numbers are inserted, PCIe devices cannot be identified, PCIe resource waste is caused, and PCIe bandwidth needs to be automatically identified and allocated.

Disclosure of Invention

In view of this, the present invention provides a bandwidth allocation method, server, device, medium, and program product to enable automatic identification and allocation of PCIe bandwidth.

In a first aspect, the present invention provides a bandwidth allocation method, applied to a central processing unit of a server, including:

Monitoring a PCIe interface of the central processing unit in an initialization stage of initializing PCIe equipment;

Judging whether the first device information is the same as the second device information or not under the condition that the first device information is acquired based on a first channel of the PCIe interface and the second device information is acquired based on a second channel of the PCIe interface; the first device information and the second device information are device information of PCIe devices connected with the PCIe interface;

Determining that the first channel and the second channel correspond to the same PCIe device under the condition that the first device information is the same as the second device information, and feeding back acknowledgement signals based on the first channel and the second channel respectively;

And performing bandwidth allocation according to the corresponding relation between the PCIe interface and the PCIe equipment.

In some optional embodiments, the determining that the first channel and the second channel correspond to the same PCIe device when the first device information is the same as the second device information includes:

If the first channel is adjacent to the second channel under the condition that the first device information is the same as the second device information, determining that the first channel and the second channel correspond to the same PCIe device;

If the first channel and the second channel are not adjacent, determining that the first channel, the second channel, and other channels between the first channel and the second channel correspond to the same PCIe device.

In some optional embodiments, if the first channel is not adjacent to the second channel, determining that the first channel, the second channel, and other channels between the first channel and the second channel correspond to the same PCIe device includes:

If the first channel is not adjacent to the second channel and the device information acquired by other channels between the first channel and the second channel is the same as the first device information and/or the second device information, determining that the first channel, the second channel and other channels between the first channel and the second channel correspond to the same PCIe device.

In some alternative embodiments, each lane of the PCIe device is configured to send device information to the central processor, the method further comprising:

And if the first channel and the second channel are not adjacent and a fourth channel which does not receive the equipment information exists between the first channel and the second channel, determining that the fourth channel link is abnormal.

In some alternative embodiments, the method further comprises:

And under the condition that third equipment information is acquired based on a third channel of the PCIe interface and the third equipment information is different from other acquired equipment information, determining one PCIe equipment with the number of corresponding channels of the third channel being 1, and feeding back a confirmation signal based on the third channel.

In some alternative embodiments, the method further comprises:

If the PCIe interface does not receive the device information in the initialization stage of initializing the PCIe device, performing bandwidth allocation based on a default bandwidth allocation policy.

In a second aspect, the present invention provides a bandwidth allocation method, applied to a PCIe device, including:

Acquiring a bandwidth configuration instruction issued by a substrate management controller based on a system management bus;

Transmitting the equipment information of the PCIe equipment to a central processing unit of a server based on the first channel cycle, and transmitting the same equipment information to the central processing unit based on the last channel cycle; the first channel is the first channel of the PCIe device, and the last channel is the last channel of the PCIe device;

And stopping sending the equipment information based on the first channel and the last channel under the condition that acknowledgement signals are acquired based on both the first channel and the last channel.

In some alternative embodiments, the method further comprises:

If the number of channels of the PCIe device is not less than 3, circularly transmitting the same device information to the central processing unit based on other channels except the first channel and the last channel;

and stopping transmitting the equipment information based on the other channels under the condition that the confirmation signal is acquired based on the other channels.

In some optional embodiments, the acquiring, based on the system management bus, the bandwidth configuration instruction issued by the baseboard management controller includes:

monitoring a data frame in the system management bus;

in the case of hearing a data frame with an address identifier of all zeros, it is determined that a bandwidth configuration instruction is acquired.

In some alternative embodiments, the method further comprises:

Reading a manufacturer identification of the PCIe device from a manufacturer identification register, and reading a device identification of the PCIe device from a device identification register;

Generating device information including the vendor identification and the device identification.

In a third aspect, the present invention provides a server comprising: a baseboard management controller and a central processing unit;

the baseboard management controller is used for issuing bandwidth configuration instructions to PCIe equipment based on a system management bus;

The central processing unit is configured to perform the bandwidth allocation method of the first aspect or any implementation manner corresponding to the first aspect.

In a fourth aspect, the present invention provides a computer device comprising: the memory and the processor are in communication connection, the memory stores computer instructions, and the processor executes the computer instructions to perform the bandwidth allocation method according to the first aspect, the second aspect or any implementation manner corresponding to the first aspect or the second aspect.

In a fifth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to perform the bandwidth allocation method of the first aspect, the second aspect or any of its corresponding embodiments.

In a sixth aspect, the present invention provides a computer program product comprising computer instructions for causing a computer to perform the bandwidth allocation method of the first aspect, the second aspect or any of its corresponding embodiments.

When the CPU in the embodiment needs to initialize the PCIe device, the channel based on the PCIe interface acquires the device information uploaded by the corresponding PCIe device, the channel number of the PCIe device can be simply determined based on the same device information, and the pins in the PCIe interface of the CPU can be determined to be inserted into the PCIe device, so that the bandwidth allocation can be automatically performed. The method is realized based on the link between the PCIe equipment and the PCIe interface, does not occupy external resources, and has simple realization mode; in addition, the bandwidth allocation table does not need to be set, so that the bandwidth allocation efficiency can be improved. Based on the device information uploaded by each channel, the CPU can identify the specific slot position connected with the PCIe device, the identification precision is high, and the detection mechanism is stable and reliable.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the related art, the drawings that are required to be used in the description of the embodiments or the related art will be briefly described, and it is apparent that the drawings in the description below are some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a schematic diagram of a framework for bandwidth allocation by a CPU according to an embodiment of the present invention;

fig. 2 is a flow chart of a bandwidth allocation method according to an embodiment of the present invention;

Fig. 3 is a flow chart of another bandwidth allocation method according to an embodiment of the present invention;

fig. 4 is a detailed flow diagram of implementing bandwidth allocation according to an embodiment of the present invention;

fig. 5 is a block diagram of a bandwidth allocation apparatus according to an embodiment of the present invention;

Fig. 6 is a block diagram of another bandwidth allocation apparatus according to an embodiment of the present invention;

Fig. 7 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

A baseboard management controller (Baseboard Management Controller, BMC for short) is a hardware component dedicated to monitoring and managing servers and other computer systems. The system is located on the main board as an independent system, has own processor and memory, can run independently of the host system, and can be accessed remotely through a network interface. The main functions and features of BMC include:

1. Remote monitoring and management: BMC allows an administrator to remotely monitor the health of the server, including temperature, fan speed, power status, hard disk status, cabinet lid on-off status, etc., and manage even when the operating system is not working.

2. Fault diagnosis and alarm: when a system anomaly, such as overheating, voltage anomaly, or hardware failure is detected, the BMC can generate an alarm and send the alarm to the management system through the network, facilitating quick response and troubleshooting.

3. Hardware control: the BMC can control operations such as starting up, shutting down, restarting and the like of the server, and adjust hardware configurations such as fan rotating speed and the like, so that system performance and energy efficiency are optimized.

4. Event log record: all important events during system operation, including hardware state changes, error information, etc., are recorded, providing historical data for system maintenance.

5. Updating firmware: the BMC itself also supports firmware updates to fix vulnerabilities, add new functionality, or optimize performance, often by remote updates over a network.

6. Compliance with industry standards: BMC follows standards such as Intelligent Platform Management Interface (IPMI) and the like, and ensures interoperability between hardware and management software of different manufacturers.

7. Safety characteristics: given the remote access capabilities of BMCs, modern BMC designs typically include security measures such as encrypted communications, access Control Lists (ACLs), authentication mechanisms, etc., to protect servers from unauthorized access and attacks.

In summary, baseboard management controllers are an integral part of modern data centers and enterprise IT infrastructure that greatly enhance the efficiency of server maintenance and reliability of the system by providing powerful remote management capabilities.

PCIe has taken fundamental changes in bus architecture, mainly in two ways: firstly, a parallel bus is changed into a serial bus; and secondly, point-to-point interconnection is adopted. A bus of the original parallel bus structure, which is connected with devices under a bridge, is changed into a link, one link can comprise one or more paths, each path consists of two pairs of differential signal lines to form a double-simplex serial transmission channel, no special data, address, control and clock lines exist, and various transactions on the bus are organized into information packets to be transmitted. Another feature of PCIe breakthroughs over traditional buses is the adoption of point-to-point interconnect methods, where each device is connected by an independent link, sharing bandwidth alone, which is an effective solution to increase transmission rate.

The PICe interface on the server main board generally adopts a PCIe x8 slot or a PCIe x16 slot, so that different types of expansion cards can be conveniently inserted in the later stage, and even if the golden finger on the expansion card is x2 or x4, the golden finger can be inserted in the PCIe x8 slot or the PCIe x16 slot; however, at present, the bandwidth directly provided by the CPU to the PCIe x8 slot or the PCIe x16 slot is the maximum bandwidth, so that the expansion card with small Lane number cannot be effectively identified when inserted, the CPU also allocates the maximum bandwidth, which results in PCIe resource waste and CPU function loss. For example, two PCIE x8 devices are inserted into slots of PCIE x16, and cannot implement PCIE devices that support two PCIE x8 slots in one PCIE x16 slot, i.e., cannot implement PCIE automatic identification and bandwidth allocation.

Currently, GPIO (General Purpose Input Output ) expansion devices can be used for dynamic configuration of bandwidth, or resistance control current or voltage detection on a physical detection circuit board is adopted. However, whether the expansion device detects or the physical resistance detects, a bandwidth allocation table needs to be additionally arranged, after the change data is obtained, the value of the bandwidth allocation table needs to be matched with the corresponding Lane number, and then the CPU analyzes the corresponding bandwidth to allocate. The data simulation of different expansion cards needs to be counted in the early stage to build a table, the types and types of corresponding expansion cards are fixed, after the expansion card data which are not in the table are inserted, identification errors exist, the table needs to be matched during use, and the overall identification and bandwidth allocation efficiency is low.

The embodiment of the invention provides a bandwidth allocation method, wherein a BMC informs each PCIe device mounted on a server to carry out bandwidth configuration by using a system management Bus (SYSTEM MANAGEMENT Bus, SMBus), and each PCIe device circularly reports own device information based on own channels, so that a CPU of the server can determine which pins in a PCIe interface are inserted into PCIe devices based on whether the acquired device information is the same or not, and can determine the channel number of the PCIe devices, thereby carrying out bandwidth allocation on the PCIe devices.

Fig. 1 shows a schematic diagram of a framework for bandwidth allocation by a CPU of a server. As shown in fig. 1, the server includes a central processing unit (i.e., a CPU) and a baseboard management controller (i.e., a BMC), when bandwidth allocation is required, the BMC sends a bandwidth configuration instruction to a PCIe device mounted on the server, so that the PCIe device can report its own device information through each channel (Lane), so that the CPU can determine the number of channels of the PCIe device, and further perform bandwidth allocation based on the number of channels.

In this embodiment, a bandwidth allocation method is provided, which may be applied to PCIe devices, such as PCIe devices shown in fig. 1. Fig. 2 is a flow chart of a bandwidth allocation method according to an embodiment of the present invention, it should be noted that the steps shown in the flow chart of the drawings may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is shown in the flow chart, in some cases the steps shown or described may be performed in an order different from that shown herein.

As shown in fig. 2, the bandwidth allocation method includes the following steps S201 to S203.

Step S201, obtaining a bandwidth configuration instruction issued by the baseboard management controller based on the system management bus.

In this embodiment, in the case where the bandwidth needs to be reconfigured, the BMC may issue an instruction for reconfiguring the bandwidth, that is, a bandwidth configuration instruction, to the system management bus (SMBus); the PCIe device may obtain the bandwidth configuration instruction based on the system management bus.

The bandwidth configuration instruction is a trigger instruction, and after receiving the bandwidth configuration instruction, the PCIe device does not perform bandwidth configuration itself, but cooperates with a CPU of the server to implement bandwidth configuration. For example, the bandwidth configuration instruction may be a mode switch instruction, and when the PCIe device receives the bandwidth configuration instruction, the PCIe device enters a bandwidth configuration mode.

Table 1 shows the interface definition of the front-end power interface portion in PCIe slot pins, with sides a and B being contact slots on both sides.

TABLE 1

As shown in table 1, the PCIe slot is reserved with SMBus interfaces, i.e., SMCLK (system management bus clock) and SMDAT (system management bus data). The BCM can broadcast bandwidth configuration instructions to the system management bus, so that each PCIe device can acquire the bandwidth configuration instructions broadcast by the BMC by monitoring the system management bus.

Optionally, after the BMC of the server is powered on, it may be determined whether the bandwidth needs to be reconfigured; specifically, the BMC may determine whether the AC power (AC power) outage has occurred at the server, and whether the chassis cover has been opened; specifically, the BMC can determine whether the case cover has been opened or not by monitoring the opening/closing state of the case cover. If the ac power to the server is turned off and the enclosure cover is opened, it indicates that the server may have a PCIe device plugged in (e.g., a PCIe device is replaced), so that the CPU is required to reconfigure the bandwidth, i.e., the BMC broadcasts a bandwidth configuration instruction to the system management bus.

In some optional embodiments, the step S201 "obtain, based on the system management bus, the bandwidth configuration instruction issued by the baseboard management controller" may specifically include: monitoring a data frame in a system management bus; in the case of hearing a data frame with an address identifier of all zeros, it is determined that a bandwidth configuration instruction is acquired.

In this embodiment, when the BMC broadcasts a bandwidth configuration instruction to the system management bus, in order to enable all PCIe devices to respond to the bandwidth configuration instruction, the address identifier of the bandwidth configuration instruction is set to all zeros, that is, the address identifier of the bandwidth configuration instruction is all zeros.

In this embodiment, the address identifier of the bandwidth configuration instruction is set to all zeros, so that each PCIe device may respond to the bandwidth configuration instruction without sequentially sending the bandwidth configuration instruction to each PCIe device. And, the data frame with the address identifier of all 0 also has the highest processing priority, so that each PCIe device can process the bandwidth configuration instruction preferentially.

After the PCIe device is powered on, the system management bus can be monitored, and if a certain data frame is monitored, whether the data frame is a bandwidth configuration instruction or not is judged based on the address identifier of the data frame; if the address identifiers of the data frames are all 0, the PCIe device may determine that a bandwidth configuration instruction was received.

In general, after receiving a certain data frame based on the system management bus, the PCIe device needs to feed back an ACK (Acknowledge character ); for example, the PCIe device may pull the corresponding data line SMDAT one bit down. In this embodiment, since the address identifier of all 0 is also different from the address of the PCIe device itself, after receiving the bandwidth configuration instruction, the PCIe device does not need to feed back an ACK, which accords with the specification of the SMBus protocol, and none of the PCIe devices feeds back an ACK, which is equivalent to that no slave device with all 0 addresses exists, so that normal operation of the system management bus can be ensured.

Step S202, device information of PCIe devices is sent to a central processing unit of a server based on the first channel cycle, and the same device information is sent to the central processing unit based on the last channel cycle; the first lane is the first lane of the PCIe device and the last lane is the last lane of the PCIe device.

Each PCIe Device has unique Device information, which may specifically include Vendor identification (Vendor ID) of the PCIe Device, device identification (Device ID), and the like.

Optionally, the process of acquiring the device information may specifically include: reading a manufacturer identification of the PCIe device from the manufacturer identification register, and reading a device identification of the PCIe device from the device identification register; device information including vendor identification and device identification is generated. The PCIe device maintains a manufacturer identification register and a device identification register, which are both read-only memories; after PCIe equipment is powered on (or after receiving a bandwidth configuration instruction), manufacturer identification and equipment identification of the PCIe equipment can be determined by reading the two registers, and then equipment information needing to be reported is generated.

In this embodiment, the PCIe device is connected to a PCIe interface of the CPU, as shown in fig. 1, where the PCIe device may be provided with a gold finger, and the PCIe interface of the CPU may be plugged into the gold finger through the gold finger; and, each Lane (Lane) of data on the PCIe device is transferred to the CPU. The number of lanes may be different for different PCIe devices; for example, if the golden finger of the PCIe device is x4, the number of channels is 4, that is, only four channels perform data transmission with the CPU.

The pin distinction of PCIe x1/x4/x8/x16 slots is described in conjunction with tables 2 to 5 below, based on table 1 above.

Table 2 shows the data interface definitions for PCIe x1 slots. As shown in Table 2, a PCIe x1 slot includes only one lane, lane 0. It will be appreciated that the pins of tables 1 and 2 together constitute pins of a PCIe x1 socket, in other words, a PCIe x1 socket contains 18 pins.

TABLE 2

Table 3 shows the subsequent data interface definitions for PCIe x4 slots. As shown in table 3, three pairs of differential signals and corresponding ground lines form three channels, and together with channel 0 shown in table 2, all channels forming a PCIe x4 slot, i.e., PCIe x4 slot includes four channels, i.e., channels 0-3. Similarly, the pins of tables 1,2, and 3 collectively constitute pins of a PCIe x4 slot, in other words, the PCIe x4 slot contains 32 pins.

TABLE 3 Table 3

Table 4 shows the subsequent data interface definitions for PCIe x8 slots. As can be seen from tables 1 through 4, the PCIe x8 slot includes eight lanes, lanes 0 through 7.

TABLE 4 Table 4

Table 5 shows the subsequent data interface definitions for PCIe x8 slots. As can be seen from tables 1 through 5, the PCIe x16 slot includes sixteen lanes, i.e., lanes 0-15.

TABLE 5

In this embodiment, for ease of description, the first lane of the PCIe device is referred to as the "first lane" and the last lane of the PCIe device is referred to as the "last lane". For example, if the PCIe device is a x8 device having lanes 0-7, then the first lane is lane 0 and the last lane is lane 7.

In the bandwidth configuration mode, after acquiring the device information, the PCIe device sends the device information to the CPU of the server at least on the first-bit lane and the last-bit lane, that is, the information sent by the first-bit lane and the last-bit lane is the same. In addition, in order to avoid failure of receiving the device information caused by incomplete startup of the server, the PCIe device periodically reports the device information on the first channel and the last channel, for example, every time a period (for example, 0.5s, 1s, etc.), that is, reports the device information once, so as to ensure that the server can receive the device information. The device information is used by the CPU to determine the number of lanes of the PCIe device, as will be explained later.

It will be appreciated that if the PCIe device is an x1 device, which has only one channel, the first channel and the last channel are one channel, and only a unique channel is needed to upload device information.

In step S203, in the case where the acknowledgement signal is acquired based on both the first channel and the last channel, the transmission of the device information based on both the first channel and the last channel is stopped.

In this embodiment, after the CPU of the server receives the device information, an acknowledgement signal (ACK signal) is fed back to the PCIe device through each channel. If the PCIe device obtains the acknowledgement signal based on the first channel and the last channel, the PCIe device may determine that the CPU has successfully received the device information sent by each channel, and the PCIe device may stop sending the device information.

The PCIe device may also set a total duration for sending device information, for example, the PCIe device may set a duration of the bandwidth configuration mode, for example, 10s. After receiving the bandwidth configuration instruction, the PCIe device enters a bandwidth configuration mode with the duration of 10 s; and in the bandwidth configuration mode, circularly reporting the device information, and if the ACK signal fed back by the CPU is received or the bandwidth configuration mode is exited due to the fact that the time reaches 10s, stopping the transmission of the device information by the PCIe device.

Optionally, each lane of the PCIe device is used to upload device information. Specifically, the method further includes the following steps A1 to A2.

And step A1, circularly sending the same device information to the central processing unit based on other channels except the first channel and the last channel under the condition that the channel number of the PCIe device is not less than 3.

And step A2, stopping transmitting the equipment information based on the other channels when the confirmation signal is acquired based on the other channels.

For example, if the PCIe device is a x4 device, it has lanes 0-3, and the PCIe device sends device information based on lane 0 (first lane) and lane 3 (last lane), and also sends device information based on lane 1 and lane 2 in the middle, respectively, so that the CPU can receive device information uploaded by all lanes. Similarly, if the intermediate channel 1 and channel 2 also respectively acquire the acknowledgement signals fed back by the CPU, the PCIe device stops sending device information to the CPU.

In addition, if the partial lanes of the PCIe device do not receive the acknowledgement signal, it may be determined that the links of the partial lanes are abnormal, and lane granularity link detection may be implemented.

Optionally, the method further comprises: converting the equipment information into abnormal information when one of the first channel and the last channel receives the confirmation signal and the other channel does not receive the confirmation signal; the exception information is sent to the central processor based on the first channel or last channel that has received the acknowledgement signal.

In this embodiment, after the device information is sent based on the first channel and the last channel, if one channel a (e.g., the first channel) receives the acknowledgement signal fed back by the CPU, but another channel B (e.g., the last channel) does not receive the acknowledgement signal fed back by the CPU later, it may be determined that the link corresponding to the other channel B is abnormal. Since the CPU may not receive the device information of the other channel B at this time, the CPU may not be aware of the problem of the link abnormality; in addition, since the CPU does not receive the device information of the other channel B, misjudgment on the number of channels of the PCIe device may also be caused.

In the above case, the PCIe device converts the original device information into the abnormality information. For example, since the device information includes a vendor identifier and a device identifier, and the device identifier is generally set to be invalid when the device identifier is all 1, the device identifier in the device information may be set to be all 1, for example, the device identifier is changed to 0xFFFF, so that the abnormality information in which the device identifier is invalid is generated. And, the PCIe device sends the anomaly information to the CPU based on the channel a that has received the acknowledgement signal, so that after the CPU receives the anomaly information, the CPU may determine that an abnormal link exists, and may further attempt to determine an abnormal link, or generate alarm information to alert an operation and maintenance person to check the link.

If the first channel and the last channel both receive the confirmation signal, but the other channels in the middle do not receive the confirmation signal, the CPU can determine that an abnormal link exists in the middle based on the first channel and the last channel, so that the PCIe device does not need to inform the CPU of abnormal links in a mode of uploading abnormal information.

According to the bandwidth allocation method provided by the embodiment, after the PCIe device receives the bandwidth configuration instruction sent by the BMC based on the system management bus, unique device information is circularly sent to the CPU of the server by utilizing the first channel and the last channel, so that the CPU can determine the channel number of the PCIe device based on the device information and determine which pins in the PCIe interface of the PCIe device are inserted into the PCIe device, and therefore bandwidth allocation can be automatically carried out. The method can be realized based on a system management bus, does not need to occupy GPIO resources, does not need to occupy additional communication interfaces such as I2C (Inter-INTEGRATED CIRCUIT, integrated circuit bus) and the like, and has simple realization mode; in addition, the bandwidth allocation table does not need to be set, so that the bandwidth allocation efficiency can be improved.

In addition, the address identifier of the bandwidth configuration instruction is all zero, so that each PCIe device can acquire the bandwidth configuration instruction and can preferentially process the bandwidth configuration instruction. Each channel of the PCIe device is used for uploading device information, so that accuracy of CPU to PCIe device identification can be further improved, whether a PCIe device link is reliable or not can be detected, and channel granularity link detection is realized.

In this embodiment, a bandwidth allocation method is provided, which can be applied to a central processing unit (i.e., CPU) of a server, such as the central processing unit shown in fig. 1. Fig. 3 is a flowchart of a bandwidth allocation method according to an embodiment of the present invention, which includes the following steps S301 to S304, as shown in fig. 3.

Step S301, monitoring a PCIe interface of the central processing unit in an initialization stage of initializing the PCIe device.

In this embodiment, after the server system is powered on, for example, after a power-on button signal of the server is triggered, a BIOS (Basic Input Output System, basic input/output system) program of the server starts to run, and when the execution is performed to the time of initializing the PCIe device, the CPU may monitor the PCIe interface of itself, so as to enter a state of receiving the device information uploaded by each channel. Wherein, the CPU generally includes a plurality of PCIe interfaces, specifically PCIe Root ports (PCIe Root ports).

Step S302, judging whether the first device information is the same as the second device information or not under the condition that the first device information is acquired based on a first channel of a PCIe interface and the second device information is acquired based on a second channel of the PCIe interface; the first device information and the second device information are device information of PCIe devices connected with the PCIe interface.

In this embodiment, for a certain PCIe interface of the CPU, it includes multiple lanes, for example, if the PCIe interface is a x16 interface, it includes 16 lanes. For the first channel and the second channel, if both channels acquire the device information sent by the PCIe device, the two device information may be compared. For convenience of description, the device information acquired by the first channel is referred to as first device information, and the device information acquired by the second channel is referred to as second device information.

Specifically, the CPU determines whether the first device information and the second device information are the same by using the uniqueness of the device information, and if the first device information is the same as the second device information, it indicates that the first channel and the second channel are connected to the same PCIe device, and if the first device information is different from the second device information, it may be said that the first channel and the second channel are connected to different PCIe devices.

If a certain channel of the PCIe interface does not receive the device information, the device information may be considered to be null, or the device information may be all 0.

In step S303, when the first device information is the same as the second device information, it is determined that the first channel and the second channel correspond to the same PCIe device, and acknowledgement signals are fed back based on the first channel and the second channel, respectively.

As described above, if the first device information is the same as the second device information, the device information of the different PCIe devices is different, that is, the device information has uniqueness, so that the first channel and the second channel of the PCIe interface can be determined at this time, and the same PCIe device is connected. And, the CPU also feeds back acknowledgement signals (ACK signals) based on the first channel and the second channel respectively, so as to inform the PCIe device that the device information is successfully received, and can instruct the PCIe device to stop uploading the device information.

It will be appreciated that if the first device information is the same as the second device information, the first device information may be device information uploaded by the PCIe device based on its first channel, and the second device information may be device information uploaded by the PCIe device based on its last channel.

If the PCIe device is a device of x1, the CPU acquires device information through only one channel. Specifically, the method may further include: and under the condition that third equipment information is acquired by a third channel based on the PCIe interface and the third equipment information is different from other acquired equipment information, determining one PCIe equipment with the number of channels being 1 corresponding to the third channel, and feeding back a confirmation signal based on the third channel.

In this embodiment, if only one channel of the PCIe interface obtains device information, that is, the third channel obtains third device information, but all device information obtained by other channels are different from the third device information, the CPU may determine that the PCIe device accessing the third channel is a device of x1, and the number of channels is 1. Similarly, the CPU may also feedback an acknowledgement signal based on the third channel to inform the PCIe device to stop sending device information.

In some optional embodiments, step S303 "determines that the first channel and the second channel correspond to the same PCIe device" includes the following steps B1 to B2 when the first device information is the same as the second device information.

And B1, if the first channel is adjacent to the second channel under the condition that the first device information is the same as the second device information, determining that the first channel and the second channel correspond to the same PCIe device.

And B2, if the first channel and the second channel are not adjacent, determining that the first channel, the second channel and other channels between the first channel and the second channel correspond to the same PCIe device.

In this embodiment, for a certain PCIe interface of the CPU, if the first device information received by the first channel is the same as the second device information received by the second channel, it may be determined that the first channel and the second channel are connected to the same PCIe device.

If the first channel is adjacent to the second channel, it may be determined directly that the first channel and the second channel correspond to the same PCIe device. For example, if the first lane is lane 0 of the PCIe interface, the second lane is lane 1 of the PCIe interface, and no device information is received by lane 2 of the PCIe interface (or the device information received by lane 2 is different from the first device information), it may be determined that the PCIe device has only two lanes, i.e., the number of lanes is 2.

If the first channel and the second channel are not adjacent, the golden finger of the PCIe device is an integral body, so that the first channel, the second channel and other channels between the first channel and the second channel correspond to the same PCIe device. At this time, the number of channels may be determined based on all channels corresponding to the PCIe device.

For example, if the first channel is channel 0 of the PCIe interface and the second channel is channel 3 of the PCIe interface, channels 1 and 2 between the two channels also correspond to the same PCIe device, that is, the PCIe devices correspond to channels 0 to 3, so the number of channels of the PCIe device is 4.

In this embodiment, the CPU may simply and quickly determine the number of channels of the PCIe device by using the first channel and the second channel to receive the same device information, and even if other channels exist between the first channel and the second channel, the identifying result is not affected, and reliability of identification may be ensured.

Optionally, step B2 "if the first channel and the second channel are not adjacent, determining that the first channel, the second channel, and other channels between the first channel and the second channel correspond to the same PCIe device" may include the following step B21.

And step B21, if the first channel and the second channel are not adjacent, and the equipment information acquired by other channels between the first channel and the second channel is the same as the first equipment information and/or the second equipment information, determining that the first channel, the second channel and the other channels between the first channel and the second channel correspond to the same PCIe equipment.

In this embodiment, each channel of the PCIe device is configured to send device information to the central processing unit, and at this time, if the first channel and the second channel are not adjacent, it is further required to determine whether the device information acquired by other channels between the first channel and the second channel is the same as the first device information and/or the second device information, so as to further improve reliability of identification. Under normal conditions, if two non-adjacent channels upload the same equipment identifier, other channels between the two channels upload the same equipment identifier.

Optionally, each lane of the PCIe device is configured to send device information to the central processor, and the method further comprises the following step C1.

And C1, if the first channel and the second channel are not adjacent and a fourth channel which does not receive the equipment information exists between the first channel and the second channel under the condition that the first equipment information and the second equipment information are the same, determining that a fourth channel link is abnormal.

In this embodiment, if the first channel and the second channel that receive the same device information are not adjacent, that is, there are other channels between the two channels; and, if each lane of the PCIe device is configured to send device information to the central processor, then other lanes between the two should also be able to receive the same device information. For convenience of description, a channel between the first channel and the second channel is referred to as a fourth channel; it will be appreciated that the number of fourth channels may be one or more; since there are no x3 devices, the fourth channel is typically multiple.

If the fourth channel between the first channel and the second channel does not receive any device information, the CPU may determine that the link between the fourth channel and the PCIe device is abnormal, thereby implementing channel granularity link detection.

Furthermore, optionally, if the first channel and the second channel correspond to a first channel and a last channel of the PCIe device, the CPU may accurately determine the number of channels of the PCIe device even if the intermediate fourth channel does not receive device information uploaded by the PCIe device. However, if the first channel or the second channel does not correspond to the first channel or the last channel of the PCIe device, or the CPU only receives the device information through the third channel, the PCIe device is actually a multi-channel device, and at this time, the result of determining the number of channels of the PCIe device by the CPU may be inaccurate.

In this embodiment, if the CPU does not correctly receive the device information sent by the first channel and the last channel of the PCIe device, since the CPU does not feed back the corresponding ACK signal, the PCIe device may determine whether the link is abnormal by determining whether the first channel and the last channel receive the ACK signal, and then feed back the corresponding information to the CPU. As described above, in the case where one of the first channel and the last channel of the PCIe device receives the acknowledgement signal and the other channel does not receive the acknowledgement signal, the PCIe device converts the own device information into the exception information; the exception information is sent to the central processor based on the first channel or last channel that has received the acknowledgement signal.

And, the CPU also performs the following steps: after the fifth channel based on the PCIe interface acquires the fifth device information and feeds back the confirmation signal based on the fifth channel, if the fifth channel acquires the abnormal information different from the fifth device information, determining that an unidentified channel connected with the PCIe device exists.

In this embodiment, the fifth channel may be the third channel, or the first channel or the second channel; if the CPU acquires the corresponding device information (i.e., the fifth device information) based on the fifth channel, and then acquires the exception information different from the fifth device information, it may be determined that the first channel or the last channel of the PCIe device does not receive the ACK signal, that is, a link of at least one channel is abnormal, that is, a channel not recognized by the CPU exists between the CPU and the PCIe device, and at this time, the determined number of channels is inaccurate.

The CPU may attempt to correct the determined number of lanes of the PCIe device; for example, if the number of lanes of the PCIe device is currently determined to be 14 and the anomaly information is received, since there is no x15 device, the PCIe device is a x16 device, and the number of lanes of the PCIe device may be corrected to be 16. If the number of channels cannot be corrected, generating an alarm message to remind operation and maintenance personnel of maintenance; if the number of lanes cannot be corrected, then, when bandwidth allocation is performed, the number of lanes determined at this time is used as the minimum number of lanes of the PCIe device, and bandwidth allocation is performed based on this.

Step S304, bandwidth allocation is performed according to the corresponding relation between the PCIe interface and the PCIe device.

In this embodiment, after determining the correspondence between each channel of the PCIe interface and the PCIe device, PCIe bandwidth allocation may be performed based on the correspondence, which is not limited to a specific allocation process.

Optionally, if the PCIe interface does not receive the device information during an initialization phase of initializing the PCIe device, bandwidth allocation is performed based on a default bandwidth allocation policy.

Fig. 4 shows a detailed flowchart for realizing bandwidth allocation, and as shown in fig. 4, the process of bandwidth allocation includes the following steps S401 to S405.

In step S401, after the BMC of the server is powered on, it is determined whether bandwidth needs to be allocated.

For example, the BMC determines whether the server has been powered off by AC power and whether the enclosure lid has been opened; if the AC power supply of the server is cut off and the case cover is opened, the bandwidth allocation is determined to be needed.

In step S402, when the bandwidth needs to be allocated, the BMC sends a bandwidth configuration instruction to the PCIe device by using the system management bus.

If the bandwidth does not need to be allocated, the BMC is started normally. After the PCIe device is powered on, the BMC sends the bandwidth configuration instruction again.

In step S403, after receiving the bandwidth configuration instruction based on the system management bus, the PCIe device circularly sends its own device information to the CPU of the server based on each channel.

In step S404, after the CPU receives the device information based on the channel of the PCIe interface, the CPU feeds back a corresponding ACK signal based on the channel.

In step S405, the CPU determines a correspondence between the PCIe interface and the PCIe device according to the received device information, and performs bandwidth allocation.

According to the bandwidth allocation method provided by the embodiment, when the CPU needs to initialize the PCIe device, the device information uploaded by the corresponding PCIe device is acquired based on the channels of the PCIe interface, the channel number of the PCIe device can be simply determined based on the same device information, and the pins in the PCIe interface of the CPU can be determined to be inserted into the PCIe device, so that the bandwidth allocation can be automatically performed. The method is realized based on the link between the PCIe equipment and the PCIe interface, does not occupy external resources, and has simple realization mode; in addition, the bandwidth allocation table does not need to be set, so that the bandwidth allocation efficiency can be improved. Based on the device information uploaded by each channel, the CPU can identify the specific slot position connected with the PCIe device, the identification precision is high, and the detection mechanism is stable and reliable.

The present embodiment also provides a server, as shown in fig. 1, including: a baseboard management controller and a central processing unit; the baseboard management controller is used for issuing bandwidth configuration instructions to PCIe equipment based on the system management bus; the central processing unit is configured to execute the bandwidth allocation method provided in the foregoing embodiment.

Optionally, the baseboard management controller is specifically configured to: judging whether the AC power supply of the server is cut off or not, and judging whether the case cover is opened or not; if the AC power supply of the server is disconnected and the case cover is opened, broadcasting a bandwidth configuration instruction to the system management bus; the address identifier of the bandwidth configuration instruction is all zero.

The functional description of the server is the same as that of the corresponding embodiment, and will not be repeated here.

The present embodiment also provides a bandwidth allocation device, which is used to implement the foregoing embodiments and preferred embodiments, and will not be described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements the intended function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

The present embodiment provides a bandwidth allocation apparatus, which is applied to a central processing unit of a server, as shown in fig. 5, including:

A monitor module 501, configured to monitor a PCIe interface of the central processor in an initialization stage of initializing a PCIe device;

A judging module 502, configured to judge whether the first device information and the second device information are the same when the first device information is acquired based on a first channel of the PCIe interface and the second device information is acquired based on a second channel of the PCIe interface; the first device information and the second device information are device information of PCIe devices connected with the PCIe interface;

A processing module 503, configured to determine that the first channel and the second channel correspond to the same PCIe device and respectively feed back acknowledgement signals based on the first channel and the second channel when the first device information is the same as the second device information;

and the bandwidth allocation module 504 is configured to allocate bandwidth according to the correspondence between the PCIe interface and the PCIe device.

In some optional embodiments, the processing module 503 determines that the first channel and the second channel correspond to the same PCIe device if the first device information is the same as the second device information, including:

In some alternative embodiments, if the first channel and the second channel are not adjacent, the processing module 503 determines that the first channel, the second channel, and other channels between the first channel and the second channel correspond to the same PCIe device, including:

In some alternative embodiments, each lane of the PCIe device is configured to send device information to the central processor, and the processing module 503 is further configured to:

In some alternative embodiments, the processing module 503 is further configured to:

In some alternative embodiments, bandwidth allocation module 504 is further configured to:

The present embodiment provides a bandwidth allocation apparatus, which is applied to PCIe devices, as shown in fig. 6, including:

an obtaining module 601, configured to obtain a bandwidth configuration instruction issued by the baseboard management controller based on the system management bus;

The information sending module 602 is configured to send device information of the PCIe device to a central processor of a server based on a first-bit lane cycle, and send the same device information to the central processor based on a last-bit lane cycle; the first channel is the first channel of the PCIe device, and the last channel is the last channel of the PCIe device;

and a response module 603, configured to stop sending the device information based on the first channel and the last channel when the acknowledgement signal is acquired based on both the first channel and the last channel.

In some alternative embodiments, the information sending module 602 is further configured to: if the number of channels of the PCIe device is not less than 3, circularly transmitting the same device information to the central processing unit based on other channels except the first channel and the last channel;

the response module 603 is further configured to: and stopping transmitting the equipment information based on the other channels under the condition that the confirmation signal is acquired based on the other channels.

In some optional embodiments, the obtaining module 601 obtains, based on a system management bus, a bandwidth configuration instruction issued by a baseboard management controller, including:

monitoring a data frame in the system management bus;

In some optional embodiments, the apparatus further comprises an information generation module for:

Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.

The bandwidth allocation device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application SPECIFIC INTEGRATED Circuit) Circuit, including a processor and a memory executing one or more software or fixed programs, and/or other devices that can provide the above-mentioned functions.

The embodiment of the invention also provides a computer device which is provided with the bandwidth allocation device shown in the figure 5 or the figure 6.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 7, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 7.

The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further comprise, among other things, an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.

Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown in implementing the above embodiments.

The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.

The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.

The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.

Portions of the present invention may be implemented as a computer program product, such as computer program instructions, which when executed by a computer, may invoke or provide methods and/or aspects in accordance with the present invention by way of operation of the computer. Those skilled in the art will appreciate that the form of computer program instructions present in a computer readable medium includes, but is not limited to, source files, executable files, installation package files, etc., and accordingly, the manner in which the computer program instructions are executed by a computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Herein, a computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by a computer.

Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims

1. A method of bandwidth allocation, applied to a central processor of a server, the method comprising:

2. The method of claim 1, wherein determining that the first channel and the second channel correspond to the same PCIe device if the first device information is the same as the second device information comprises:

3. The method of claim 2, wherein determining that the first channel, the second channel, and other channels between the first channel and the second channel correspond to the same PCIe device if the first channel and the second channel are not adjacent, comprises:

4. The method of claim 2, wherein each lane of the PCIe device is configured to send device information to the central processor, the method further comprising:

5. The method as recited in claim 1, further comprising:

6. The method as recited in claim 1, further comprising:

7. A method of bandwidth allocation, for use with a PCIe device, the method comprising:

8. The method as recited in claim 7, further comprising:

9. The method of claim 7, wherein the obtaining, based on the system management bus, the bandwidth configuration instruction issued by the baseboard management controller, comprises:

monitoring a data frame in the system management bus;

10. The method as recited in claim 7, further comprising:

11. A server for a server, which comprises a server and a server, characterized by comprising the following steps: a baseboard management controller and a central processing unit;

the central processor is configured to perform the bandwidth allocation method of any one of claims 1 to 6.

12. The server of claim 11, wherein the baseboard management controller is specifically configured to:

Judging whether the server is powered off by an alternating current power supply or not and whether a case cover is opened or not;

If the AC power supply of the server is disconnected and the case cover is opened, broadcasting a bandwidth configuration instruction to a system management bus; the address identifier of the bandwidth configuration instruction is all zero.

13. A computer device, comprising:

A memory and a processor communicatively coupled to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the bandwidth allocation method of any of claims 1 to 10.

14. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the bandwidth allocation method of any of claims 1 to 10.

15. A computer program product comprising computer instructions for causing a computer to perform the bandwidth allocation method of any of claims 1 to 10.