CN118606214A - Load debugging method, driving chip and electronic equipment - Google Patents

Abstract

The embodiment of the application discloses a load debugging method, a driving chip and electronic equipment, and relates to the field of testing. The application realizes the functions of updating codes and monitoring running states of the driving chip under the condition that a download port and a debugging port are not required to be independently arranged by dynamically configuring the functions of the IO pins and adopting an interrupt-driven communication mode, improves the use efficiency of the IO pins, and ensures that the system is more flexible, efficient and reliable.

Description

Load debugging method, driving chip and electronic equipment

Technical Field

The present application relates to the field of testing, and in particular, to a load debugging method, a driving chip, and an electronic device.

Background

At present, debugging and downloading of special driving chips such as a touch driving chip and a brushless motor driving IC are necessary means, and based on the characteristics of the special driving chips, scheme debugging is required to be carried out on a corresponding circuit board. Now, for cost reasons, many circuit boards are single-sided boards, so the more functions the more difficult the board is to route, if one design board needs to leave both a programming port and a debugging port, the more difficult the board is to route and the more IO resources are wasted. The download port and the debug port are separately reserved in the drive chip, and IO resources are wasted in this way.

Disclosure of Invention

The embodiment of the application provides a load debugging method, a driving chip and electronic equipment, which can solve the problem that the number of IO pins occupied when a driving circuit debugs a load in the related art is more. The technical scheme is as follows:

In a first aspect, an embodiment of the present application provides a method for debugging a load, where the method includes:

receiving a code update instruction from an upper computer;

responding to the code updating instruction, and setting the first IO pin and the second IO pin as downloading ports;

receiving a load driving code from the upper computer through the download port;

after the integrity of the load driving code is verified, driving a load to work by using the current control parameter value in the load driving code;

detecting a current operating state parameter value of the load at a current control parameter value;

Switching the first IO pin and the second IO pin into UART ports, and sending the current running state parameter values to the upper computer through the UART ports; the upper computer generates a next control parameter value according to the difference value between the current running state parameter value and the target running state parameter value, and sends the next control parameter value to a driving chip through the UART port;

And receiving a next control parameter value from the upper computer through the UART port by adopting an interrupt mode, and driving the load to work by utilizing the next control parameter.

In a second aspect, an embodiment of the present application provides a driving chip, including:

the receiving and transmitting unit is used for receiving a code updating instruction from the upper computer;

The setting unit is used for responding to the code updating instruction and setting the first IO pin and the second IO pin as downloading ports;

The receiving and transmitting unit is further used for receiving a load driving code from the upper computer through the downloading port;

The driving unit is used for driving a load to work by using the current control parameter value in the load driving code after the integrity of the load driving code is verified;

A detection unit for detecting a current operation state parameter value of the load under a current control parameter value;

the setting unit is further configured to switch the first IO pin and the second IO pin to UART ports, and send the current running state parameter value to the upper computer through the UART ports; the upper computer generates a next control parameter value according to the difference value between the current running state parameter value and the target running state parameter value, and sends the next control parameter value to a driving chip through the UART port;

The driving unit is further configured to receive a next control parameter value from the upper computer through the UART port in an interrupt mode, and drive the load to work by using the next control parameter.

In a third aspect, embodiments of the present application provide a computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the above-described method steps.

In a fourth aspect, an embodiment of the present application provides a driving chip, which may include: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the above-mentioned method steps.

In a fifth aspect, an embodiment of the present application provides an electronic device, including the driving chip described above, where the electronic device may be a communication device, a computer device, a vehicle-mounted device, or other devices.

The technical scheme provided by the embodiments of the application has the beneficial effects that at least:

By dynamically configuring the function of the IO pin and adopting the communication mode of interrupt driving, the functions of updating codes and monitoring the running state of the driving chip under the condition that a downloading port and a debugging port are not required to be independently arranged are realized, the use efficiency of the IO pin is improved, and the system is more flexible, efficient and reliable.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a network block diagram provided by an embodiment of the present application;

Fig. 2 is a flow chart of a load debugging method according to an embodiment of the present application;

Fig. 3 is a schematic structural diagram of a driving chip according to an embodiment of the present application;

Fig. 4 is a schematic structural diagram of an apparatus according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the following detailed description of the embodiments of the present application will be given with reference to the accompanying drawings.

When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the application as detailed in the accompanying claims.

In the description of the present application, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art. Furthermore, in the description of the present application, unless otherwise indicated, "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

Referring to fig. 1, a network architecture diagram provided in an embodiment of the present application includes: the upper computer 11, the circuit board 12, the driving chip 13 and a load (not shown in fig. 1), wherein the load can be a motor, a touch screen or the like, the number of the load can be one or more, and the driving chip 31 is arranged in a socket of the circuit board 12.

The host computer 11 of the present application has a display device. The communication manner among the upper computer 11, the circuit board 12 and the motor 13 may be a wired communication manner (for example, a serial communication manner), and the wired communication manner includes, but is not limited to, a USB cable, a URAT cable, a network cable, a coaxial cable, or other cables.

Referring to fig. 2, a flow chart of a load debugging method according to an embodiment of the present application is shown. As shown in fig. 2, the method according to the embodiment of the present application may include the following steps:

S201, receiving a code update instruction from an upper computer.

The driver chip is initialized first, including initialization of internal resources, registers, and communication interfaces (such as UART, SPI, etc.). Parameters of the communication interface, such as baud rate, data bit, stop bit, check bit, etc., are configured to ensure smooth communication with the host computer. The driver chip initiates a listening process to continuously monitor the data on the communication interface. The listening process follows a predetermined communication protocol to identify and respond to instructions from the host computer. When the upper computer sends a code updating instruction, the driving chip receives the instruction through the communication interface. The code update instruction may contain a specific identifier or flag bit for identifying that it is a code update request. The driver chip analyzes the received update instruction, and extracts key information in the instruction, such as a code version number, an update file size, a checksum and the like. The parsing process ensures the integrity and correctness of the instruction for subsequent code update operations. And according to the instruction information obtained by analysis, the driving chip prepares to receive a new load driving code.

S202, in response to an update code instruction, the first IO pin and the second IO pin are set as downloading ports.

The first IO pin and the second IO pin are any two different IO pins in the driving chip, and can be selected according to actual requirements. The driving chip sets the first IO pin as the CLK clock pin of the downloading port, which relates to configuring the first IO pin into an output mode and setting the electrical properties (such as output level, driving capability and the like) of the first IO pin to adapt to the requirement of a clock signal. The second IO pin is set to the DATA DATA pin of the download port. Also, it involves configuring the second IO pin to output (or bi-directional if the data pin needs to receive data) mode and setting its electrical properties to accommodate the requirements of the data signal. The driver chip may generate the CLK clock signal and output it through a first IO pin (CLK pin), if necessary. The clock signal is used for synchronous data transmission, and the frequency and the duty ratio of the clock signal need to be set according to a specific downloading protocol. The DATA signal is ready to be transmitted or received through the second IO pin (DATA pin). The data signal contains a new load driving code or other relevant data and needs to be transmitted according to a predetermined format and timing.

S203, receiving a load driving code from the upper computer through the download port.

After the IO pins are configured, the driving chip enters a downloading mode and waits for the upper computer to send a new load driving code. In the download mode, the driver chip may disable or adjust other functions associated with motor control to ensure successful code updating. When the upper computer starts to send a new load driving code, the driving chip receives DATA through the DATA pin.

At the same time, the reception of data is synchronized according to the clock signal on the CLK pin. After the data is received, the driving chip performs integrity check on the data so as to ensure the accuracy of the data. If the data check passes, the driver chip loads the new code into its internal memory. After loading is completed, the driver chip may need to perform a reboot or reset operation to validate the new code. After restarting, the driving chip starts to execute a new load driving code to control the operation of the motor. After the code updating is completed, the driving chip exits the downloading mode, and the normal motor control function is recovered. Meanwhile, the first and second IO pins may be reconfigured for other purposes or remain in an idle state.

S204, after the integrity of the load driving code is checked, the load is driven to work by using the current control parameter value in the load driving code.

After receiving the new load driving code, the driving chip firstly performs integrity check on the new load driving code. The verification method may include calculating a checksum of the code, using a hash function or other digital signature technique to ensure that the code has not been tampered with during transmission. If the verification fails, the driving chip does not execute subsequent operations and can send error feedback to the upper computer. If the code integrity check passes, the driver chip will parse the new load driver code to extract the control parameter values therein. The control parameter values may include target rotational speed, direction, power, etc., loop PID parameters, etc. The parsing process needs to follow the parameter formats and coding rules defined in the code. The driving chip configures the control parameter value obtained by analysis into an internal control system. May involve updating register values, setting parameters of the control loop, etc. After the configuration is completed, the driving chip performs subsequent motor control operation according to the new control parameter value. After the control parameters are configured, the driving chip starts the load driving process. May include sending PWM (pulse width modulation) signals, direction signals, etc. to the motor driver to drive the motor to operate in accordance with the set control parameter values.

S205, detecting the current operation state parameter value of the load under the current control parameter value.

Wherein the load may be a motor or a touch screen.

When the load is a motor, the driving chip reads control parameter values for the motor from an internal register or a storage unit, including PID parameter values (proportional, integral, differential coefficients), power settings, and the like. Using the read control parameter values, the driving chip controls the motor driver through PWM (pulse width modulation) signals, direction signals, etc., and starts the motor. The driving chip monitors the running state parameters of the motor in real time through a sensor interface or a special circuit, including a current value, a voltage value, a rotating speed value and the like. These parameters may be read by analog signals (e.g., ADC conversion) or digital signals (e.g., serial communication). The read operation state parameter value can be subjected to unit conversion, filtering, calibration and other processes so as to improve the accuracy and reliability of the data.

When the load is a touch screen, the driving chip reads control parameter values aiming at the touch screen from an internal register or a storage unit, wherein the control parameter values comprise charge-discharge capacitance shift, resistance shift, touch filtering parameter setting, channel triggering threshold setting and the like. And using the read control parameter values, the driving chip configures hardware parameters of the touch screen, such as charge and discharge capacitance, resistance and the like, and software parameters, such as filtering parameters, triggering thresholds and the like. The driving chip monitors the operation state parameter values of the original data, the baseline data, the channel difference value and the like of the touch screen in real time through the touch screen interface. The read operating state parameter values may require noise suppression, threshold comparison, difference calculation, etc. to identify valid touch events.

S206, switching the first IO pin and the second IO pin into UART ports, and sending the current running state parameter values to the upper computer through the UART ports.

Wherein, the driving chip configures the first IO pin and the second IO pin as TX (transmitting) and RX (receiving) pins of the UART port. To setting the IO pin to UART functional mode and configuring the relevant electrical characteristics (e.g., level, impedance, etc.). The driving chip reads the running state parameter values of the current load, such as current value, voltage value, rotation speed value (motor) or original data, baseline data, channel difference value (touch screen) and the like, from an internal register or a sensor interface. And the driving chip encapsulates the read running state parameter value into a data frame format specified by the UART communication protocol. And the driving chip sends the data frame to the upper computer through a TX pin of the UART port.

The upper computer receives the data frame from the driving chip through the UART interface. The upper computer analyzes the received data frame and extracts the current running state parameter value sent by the driving chip. And the upper computer compares the current running state parameter value with the target running state parameter value to calculate a difference value. And generating a next control parameter value by the upper computer according to the calculated difference and a preset control strategy or algorithm. And the upper computer encapsulates the generated next control parameter value into a data frame format specified by the UART communication protocol. And the upper computer sends the data frame to the driving chip through a TX pin of the UART interface.

The driving chip receives the data frame from the upper computer through the RX pin of the UART interface. The driving chip analyzes the received data frame and extracts the next control parameter value sent by the upper computer. The driving chip applies the extracted next control parameter value to the load control to update the internal register or the control logic. According to the new control parameter value, the driving chip adjusts the control of the load, such as adjusting the duty ratio of the PWM signal, changing the gear of the charge-discharge capacitor, etc.

The upper computer can display the received current running state parameter value on the display screen, and then manually adjust the next control parameter value according to the current running state parameter value.

In some embodiments of the present application, the driver chip includes a DMA controller therein, which needs to be initialized first, and parameters of DMA transfer, such as source address, destination address, transfer length, trigger mode, etc., are configured. And a data buffer area is arranged in the driving chip and is used for storing the current running state parameter value to be transmitted. And the UART interface is connected with the DMA controller to ensure that the DMA controller can correctly transmit the data from the buffer zone to the UART sending buffer zone. The driver chip reads the current load's operating state parameter values from the internal registers or sensor interface and writes them into a previously set data buffer. After the data in the data buffer is ready, the driver chip initiates a DMA transfer. The DMA controller will automatically read the data from the data buffer and transfer it to the UART send buffer. The UART interface reads data from the transmission buffer area and transmits the data to the upper computer through the TX pin.

The DMA transmission mode does not need the participation of a CPU, can directly carry out data movement, greatly lightens the burden of the CPU and improves the efficiency of data transmission. Due to independence of DMA transmission, data can be sent to the UART interface to be sent more quickly, and therefore instantaneity of the system is improved. In the DMA transmission process, data is directly transmitted from a source address to a target address, so that the number of times of data transmission between a CPU and a memory is reduced, and the possibility of data errors is reduced.

In some embodiments of the present application, the driver chip switches the first IO pin and the second IO pin to UART mode based on a mode switching instruction of the host computer.

The drive chip continuously monitors the communication of the upper computer connected with the UART port. When the upper computer sends a mode switching instruction, the driving chip receives the instruction through the UART port. The instruction typically contains a specific identifier for identifying that this is a mode switch request. The driver chip parses the received mode switch command to determine specific parameters in the command, including the mode type to be switched (UART mode in this example) and related configuration parameters (e.g., baud rate, data bits, stop bits, etc.).

After the instruction is parsed, the driver chip needs to verify the validity and correctness of the instruction. This may include checking whether the instruction format is correct, whether the parameters are legal, etc. And according to the analyzed and verified instruction content, the driving chip writes a specific value into an internal mode register so as to set the first IO pin and the second IO pin as UART modes. This value is defined by the driver chip vendor to indicate that the IO pin should be configured for UART functionality. After writing the mode register, the driver chip should verify whether the configuration was successful. This may be achieved by reading the value of the mode register and comparing it to an expected value.

S207, receiving the next control parameter value from the upper computer through the UART port by adopting an interrupt mode, and driving the load to work by utilizing the next control parameter.

The driver chip enables the UART to receive the interrupt, and configures an interrupt trigger condition, such as receiving a specific byte or a frame of data. An Interrupt Service Routine (ISR) is written that will automatically execute when the UART receives data. The UART interface begins to wait for data to be received and when data is received, an interrupt is triggered. Upon receiving the data, the UART interface triggers an interrupt and the CPU jumps to interrupt service routine execution. In the interrupt service routine, data is read from the UART receive buffer. And analyzing the read data, and extracting the next control parameter value sent by the upper computer. And verifying the extracted control parameter value to ensure the integrity and correctness of the data. The verified correct control parameter values are saved to an internal register or control logic of the driver chip. The new next control parameter value is read from an internal register or control logic. And according to the new control parameter value, configuring control parameters of the load, such as adjusting the duty ratio of the PWM signal, changing the gear of the charge-discharge capacitor, and the like. The load is driven to operate using the new control parameter values. After the interrupt service routine is executed, the flag bit of the UART receiving the interrupt is cleared to allow a new interrupt trigger. After the interrupt service routine is executed, the CPU returns to the main routine to continue executing other tasks. The UART interface continues to wait to receive new data until the next interrupt trigger.

In some embodiments of the present application, the driver chip implements the operation mode on the first IO pin and the second IO pin by modifying the mode register, the operation mode including a download mode and a debug mode.

The mode register is a special register inside the driving chip and is used for storing and configuring the functional modes of the IO pins. During the initialization phase, the mode register needs to be set to an initial value that typically indicates a default IO pin function mode (e.g., standard GPIO mode). And determining the functional mode (a downloading mode or a debugging mode) of the first IO pin and the second IO pin to be configured according to the system requirement.

A specific value is written to the mode register to set the functional modes of the first IO pin and the second IO pin. These values are typically defined by the driver chip manufacturer, with different values corresponding to different functional modes. After writing the mode register, the system should verify whether the configuration was successful. This may be achieved by reading the value of the mode register and comparing it to the written value.

Download mode: if the first IO pin and the second IO pin are configured in download mode, they will be used as code download ports. At this time, the driver chip should be ready to receive the code update instruction from the host computer, and receive the load driving code through the two pins. The received code should be subjected to integrity check and used for updating the code inside the driver chip after the check is successful.

Debug mode: if the first IO pin and the second IO pin are configured in debug mode, they will be used as debug communication ports (e.g., UART ports).

The beneficial effects of the application include:

And dynamically setting the first IO pin and the second IO pin as a downloading port by responding to a code updating instruction of the upper computer, wherein the downloading port is used for receiving a load driving code from the upper computer. After the code updating is completed, the pins can be switched back to the UART port for communication with the upper computer, and the current running state parameter value of the load is transmitted.

The traditional driving chip design often needs to set a special downloading port and a special debugging port for code downloading and debugging, which not only increases the complexity of hardware design, but also limits the use efficiency of IO pins. According to the technical scheme, through dynamically configuring the functions of the IO pins, the limitation is avoided, and the IO pins can be flexibly switched between different functions according to the needs.

The driving chip can send the current running state parameter value of the load to the upper computer in real time through the UART port. And the upper computer generates a next control parameter value according to the difference value between the parameters and the target running state parameter value, and sends the next control parameter value to the driving chip through the UART port. The real-time feedback and adjustment mechanism enables the system to respond to changes quickly and optimize the running state of the load.

The interrupt mode is adopted to receive the next control parameter value from the upper computer through the UART port, so that the driving chip can respond to the instruction of the upper computer in real time, and the load is driven to work by quickly applying the new control parameter value. The communication mode not only improves the real-time performance of the system, but also reduces the occupancy rate of the CPU.

The following are examples of the apparatus of the present application that may be used to perform the method embodiments of the present application. For details not disclosed in the embodiments of the apparatus of the present application, please refer to the embodiments of the method of the present application.

Referring to fig. 3, a schematic diagram of a driving chip according to an exemplary embodiment of the application is shown. The driving chip 3 includes: a transceiver unit 301, a setting unit 302, a driving unit 303, and a detecting unit 304.

A transceiver 301, configured to receive a code update instruction from an upper computer;

a setting unit 302, configured to set the first IO pin and the second IO pin as download ports in response to the update code instruction;

the transceiver 301 is further configured to receive a load driving code from the host computer through the download port;

the driving unit 303 is configured to perform integrity verification on the load driving code, and then drive a load to work by using a current control parameter value in the load driving code;

A detection unit 304 for detecting a current operation state parameter value of the load under a current control parameter value;

The setting unit 302 is further configured to switch the first IO pin and the second IO pin to UART ports, and send the current running state parameter value to the upper computer through the UART ports; the upper computer generates a next control parameter value according to the difference value between the current running state parameter value and the target running state parameter value, and sends the next control parameter value to a driving chip through the UART port;

the driving unit 303 is further configured to receive a next control parameter value from the host computer through the UART port in an interrupt mode, and drive the load to operate by using the next control parameter.

In one or more embodiments, the integrity check includes: calculate a checksum of the load driving code, or use a hash function.

In one or more embodiments, a mode register is provided in the driver chip, and a functional mode of the first IO pin and the second IO pin is configured through the mode register, where the functional mode is a download mode or a debug mode.

In one or more embodiments, the current operating state parameter values are transferred to the host computer using a DMA mode.

In one or more embodiments, the load is a motor or a touch screen.

In one or more embodiments, the sending the current running state parameter value to the upper computer through the UART port includes:

and packaging the read current running state parameter value into a data frame format specified by a UART communication protocol, and transmitting the data frame to the upper computer through a TX pin of a UART port.

In one or more embodiments, the switching the first IO pin and the second IO pin to UART ports includes:

And switching the first IO pin and the second IO pin into UART ports according to a mode switching instruction from the upper computer.

It should be noted that, when the method for debugging the load is executed by the driving chip provided in the above embodiment, only the division of the above functional modules is used for illustration, in practical application, the above functional allocation may be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the load debugging method provided in the above embodiment and the load debugging method embodiment belong to the same concept, which embody the detailed implementation process in the method embodiment, and are not repeated here.

The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

The embodiment of the present application further provides a computer storage medium, where the computer storage medium may store a plurality of instructions, where the instructions are adapted to be loaded by a processor and execute the steps of the method shown in the embodiment of fig. 2, and the specific execution process may refer to the specific description of the embodiment shown in fig. 2, which is not repeated herein.

Referring to fig. 4, a schematic structural diagram of a driving chip is provided in an embodiment of the present application. As shown in fig. 4, the driving chip 400 may be the circuit board 12 of fig. 1, and the driving chip 400 may include: at least one processor 401, at least one communication interface 403, a memory 404, and at least one communication bus 402.

Wherein communication bus 402 is used to enable connected communications between these components.

The communication interface 403 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others.

Wherein the processor 401 may include one or more processing cores. The processor 401 connects various parts within the entire driver chip 400 using various interfaces and lines, performs various functions of the driver chip 400 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 404, and calling data stored in the memory 404. Alternatively, the processor 401 may be implemented in at least one hardware form of digital signal Processing (DIGITAL SIGNAL Processing, DSP), field-Programmable gate array (Field-Programmable GATEARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 401 may integrate one or a combination of several of a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), a modem, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It will be appreciated that the modem may not be integrated into the processor 401 and may be implemented by a single chip.

The Memory 404 may include a random access Memory (RandomAccess Memory, RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 404 includes a non-transitory computer readable medium (non-transitory computer-readable storage medium). Memory 404 may be used to store instructions, programs, code, sets of codes, or instruction sets. The memory 404 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the above-described various method embodiments, etc.; the storage data area may store data or the like referred to in the above respective method embodiments. The memory 404 may also optionally be at least one memory driver chip located remotely from the aforementioned processor 401. As shown in FIG. 4, an operating system, network communication modules, and application programs may be included in memory 404, which is a type of computer storage medium.

In the driver chip 400 shown in fig. 4, a processor 401 may be used to invoke an application program of a configuration application program interface stored in a memory 404 and to specifically perform the following steps of operating the method embodiment shown in fig. 2.

The concept of the present embodiment is the same as that of the method embodiment of fig. 2, and the technical effects brought by the concept are the same, and the specific process may refer to the description of the embodiment of fig. 2, which is not repeated here.

Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory, a random access memory, or the like.

The foregoing disclosure is illustrative of the present application and is not to be construed as limiting the scope of the application, which is defined by the appended claims.

Claims (10)

1. The chip debugging method is characterized by comprising the following steps of:

receiving a code update instruction from an upper computer;

responding to the code updating instruction, and setting the first IO pin and the second IO pin as downloading ports;

receiving a load driving code from the upper computer through the download port;

after the integrity of the load driving code is verified, driving a load to work by using the current control parameter value in the load driving code;

detecting a current operating state parameter value of the load at a current control parameter value;

Switching the first IO pin and the second IO pin into UART ports, and sending the current running state parameter values to the upper computer through the UART ports; the upper computer generates a next control parameter value according to the difference value between the current running state parameter value and the target running state parameter value, and sends the next control parameter value to a driving chip through the UART port;

And receiving a next control parameter value from the upper computer through the UART port by adopting an interrupt mode, and driving the load to work by utilizing the next control parameter.

2. The method of claim 1, wherein the integrity check comprises: calculate a checksum of the load driving code, or use a hash function.

3. The method according to claim 1 or 2, wherein a mode register is provided in the driver chip, and the functional modes of the first IO pin and the second IO pin are configured through the mode register, and the functional modes are a download mode or a debug mode.

4. A method according to claim 3, characterized in that the current operating state parameter values are transferred to the host computer using DMA.

5. The method of claim 1 or 2 or 4, wherein the load is a motor or a touch screen.

6. The method of claim 5, wherein said sending the current operating state parameter value to the host computer via the UART port comprises:

and packaging the read current running state parameter value into a data frame format specified by a UART communication protocol, and transmitting the data frame to the upper computer through a TX pin of a UART port.

7. The method of claim 6, wherein the switching the first IO pin and the second IO pin to UART ports comprises:

And switching the first IO pin and the second IO pin into UART ports according to a mode switching instruction from the upper computer.

8. A driver chip for a load, comprising:

the receiving and transmitting unit is used for receiving a code updating instruction from the upper computer;

The setting unit is used for responding to the code updating instruction and setting the first IO pin and the second IO pin as downloading ports;

The receiving and transmitting unit is further used for receiving a load driving code from the upper computer through the downloading port;

The driving unit is used for driving a load to work by using the current control parameter value in the load driving code after the integrity of the load driving code is verified;

A detection unit for detecting a current operation state parameter value of the load under a current control parameter value;

the setting unit is further configured to switch the first IO pin and the second IO pin to UART ports, and send the current running state parameter value to the upper computer through the UART ports; the upper computer generates a next control parameter value according to the difference value between the current running state parameter value and the target running state parameter value, and sends the next control parameter value to a driving chip through the UART port;

The driving unit is further configured to receive a next control parameter value from the upper computer through the UART port in an interrupt mode, and drive the load to work by using the next control parameter.

9. A driver chip, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the method steps of any of claims 1-7.

10. An electronic device comprising the driver chip as claimed in claim 8 or 9.