CN118574418A

CN118574418A - Memory and manufacturing method thereof, and read-write method

Info

Publication number: CN118574418A
Application number: CN202310161017.4A
Authority: CN
Inventors: 唐怡
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-02-21
Filing date: 2023-02-21
Publication date: 2024-08-30

Abstract

The embodiment of the disclosure provides a memory, a manufacturing method thereof and a reading and writing method. The memory provided by the embodiment of the disclosure is a 2T0C memory formed by a first junction-free transistor and a second junction-free transistor, wherein a charge trapping layer is arranged on one surface (second surface) of the second junction-free transistor, which is away from a gate structure, and the charge trapping layer can be used as an electron trap (electron trap) to trap and store charges when the second junction-free transistor is conducted; when the first non-junction transistor is turned on, the charge stored in the charge trapping layer can affect the first non-junction transistor turn-on current (i.e., drain current), and thus the storage state of the memory can be determined by the change of the first non-junction transistor turn-on current. The 2T0C memory does not need a capacitor, does not have large power consumption and large area caused by the capacitor, greatly reduces the size and the power consumption of the memory, has simple manufacturing process and is convenient to popularize and apply.

Description

Memory and manufacturing method thereof, and read-write method

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to a memory, a method for manufacturing the same, and a method for reading and writing the same.

Background

For memories, faster speeds, lower power consumption and higher storage densities are always sought after. A common dynamic random access memory (DRAM, dynamic Random Access Memory) cell is a 1TlC structure consisting of a Transistor (Transistor) and a Capacitor (Capacitor), the logic state being distinguished by whether or not a charge is stored on the Capacitor. However, the current market places increasing demands on memory performance and cell size, which presents serious challenges for memory design and manufacturing.

Disclosure of Invention

The technical problem to be solved by some embodiments of the present disclosure is to provide a memory, a manufacturing method thereof, and a read-write method thereof, which can meet the demand of miniaturization of the memory and reduce the power consumption of the memory.

To solve the above-described problems, an embodiment of the present disclosure provides a memory including: a substrate; a first junction-free transistor disposed on the substrate, comprising a first semiconductor layer having a first channel region; a charge trapping layer disposed on a surface of the first channel region of the first semiconductor layer; the second junction-free transistor comprises a second semiconductor layer and a gate structure, wherein the second semiconductor layer is provided with a second channel region, the second semiconductor layer is insulated and isolated from the first semiconductor layer, the gate structure is arranged on the first surface of the second channel region of the second semiconductor layer, the charge trapping layer is arranged on the second surface of the second channel region of the second semiconductor layer, and the first surface and the second surface are arranged oppositely.

In one embodiment, the charge trapping layer comprises: a first insulating layer disposed on a surface of the first channel region of the first semiconductor layer; a charge trap layer disposed on a surface of the first insulating layer; and a second insulating layer on a surface of the charge trap layer, the second insulating layer being in contact with the second surface of the second channel region of the second semiconductor layer.

In an embodiment, the charge trap layer is a nitride layer, and a contact interface between the second insulating layer and the charge trap layer is a nitrogen-rich interface.

In an embodiment, the first semiconductor layer further has a first source region and a first drain region, the first source region and the first drain region are respectively disposed on two sides of the first channel region in a direction parallel to the surface of the substrate, the first junction-free transistor further includes a first source electrode and a first drain electrode, the first source electrode is disposed on the surface of the first semiconductor layer and is in contact with the first source region, and the first drain electrode is disposed on the surface of the first semiconductor layer and is in contact with the first drain region.

In an embodiment, in a direction parallel to the substrate surface, the first source region and the first drain region respectively include a protruding region protruding from the second semiconductor layer, the first source electrode is disposed in the protruding region of the first source region, and the first drain electrode is disposed in the protruding region of the first drain region.

In an embodiment, the protruding regions of the first source region and the first drain region are located on the same side of the first channel region and are independent of each other; or the first source region and the protruding region of the first drain region are located on different sides of the first channel region.

In an embodiment, the second semiconductor layer further has a second source region and a second drain region, the second source region and the second drain region are respectively disposed at two sides of the second channel region, the second junction-free transistor further includes a second source electrode and a second drain electrode, the second source electrode is disposed on the first surface of the second semiconductor layer and is in contact with the second source region, and the second drain electrode is disposed on the first surface of the second semiconductor layer and is in contact with the second drain region.

In an embodiment, the second semiconductor layer includes a first region and a second region disposed along a direction parallel to the surface of the substrate, the second region has a doping concentration greater than that of the first region, the second source region is located in the first region, the second drain region is located in the second region, and at least a portion of the second channel region is located in the first region.

In an embodiment, the second semiconductor layer includes a third region, a first region and a second region disposed along a direction parallel to the surface of the substrate, the second region and the third region have a doping concentration greater than that of the first region, the second source region is located in the third region, the second drain region is located in the second region, and the second channel region is located in part of the first region and in part of the second channel region is located in the second region.

In an embodiment, the front projection of the gate structure on the substrate surface completely overlaps with the front projection of the charge trapping layer on the substrate surface, or the front projection of the charge trapping layer on the substrate surface is located within the front projection of the gate structure on the substrate surface.

In an embodiment, the semiconductor device further comprises an isolation layer disposed between the first semiconductor layer and the second semiconductor layer to insulate the second semiconductor layer from the first semiconductor layer, and the charge trapping layer is disposed within the isolation layer.

The embodiment of the disclosure also provides a method for manufacturing the memory, which comprises the following steps: forming a first semiconductor layer on a substrate, the first semiconductor layer being used to form a first junction-free transistor; forming a charge trapping layer on the first semiconductor layer, wherein a region of the first semiconductor layer, which is in contact with the charge trapping layer, is a first channel region; forming a second semiconductor layer overlying the charge trapping layer and insulated from the first semiconductor layer, the second semiconductor layer for forming a second junction-free transistor; and forming a gate structure on the surface of the second semiconductor layer, wherein the contact area of the second semiconductor layer and the gate structure is a second channel region.

In one embodiment, the step of forming a charge trapping layer on the first semiconductor layer includes: sequentially forming a first insulating material layer, a trap material layer and a second insulating material layer on the first semiconductor layer; and patterning the second insulating material layer, the trap material layer and the first insulating material layer to form a second insulating layer, a charge trap layer and a first insulating layer, wherein the second insulating layer, the charge trap layer and the first insulating layer form the charge trapping layer.

In one embodiment, the step of forming a charge trapping layer on the first semiconductor layer further comprises: forming an isolation layer that covers a portion of the first semiconductor layer and exposes the charge trapping layer; and forming the second semiconductor layer on the surfaces of the isolation layer and the charge trapping layer.

In an embodiment, the first semiconductor layer includes a first source region and a first drain region disposed on both sides of the first channel region, the second semiconductor layer includes a second source region and a second drain region disposed on both sides of the second channel region, the method further comprising: the method comprises the steps of forming a first source electrode, a first drain electrode, a second source electrode and a second drain electrode, wherein the first source electrode is arranged on the surface of the first semiconductor layer and is in contact with the first source region, the first drain electrode is arranged on the surface of the first semiconductor layer and is in contact with the first drain region, the second source electrode is arranged on the surface of the second semiconductor layer and is in contact with the second source region, and the second drain electrode is arranged on the surface of the second semiconductor layer and is in contact with the second drain region.

In one embodiment, the step of forming the second semiconductor layer includes: forming a second semiconductor material layer covering the charge trapping layer and insulated from the first semiconductor layer; and doping part of the second semiconductor material layer to form a first region and a second region with different doping concentrations, wherein the doping concentration of the second region is larger than that of the first region.

The embodiment of the disclosure also provides a read-write method of the memory, which comprises the steps of; when a write operation is executed, applying a starting voltage to the second junction-free transistor to control the second junction-free transistor to be conducted, and applying a write voltage to the second junction-free transistor, wherein the charge trapping layer captures and stores charges so that the memory is changed from a first storage state to a second storage state; and when a read operation is executed, applying a read voltage to the first junction-free transistor, and determining the storage state of the memory according to the drain current of the first junction-free transistor.

In an embodiment, determining the storage state of the memory from the drain current of the first junction-free transistor comprises: comparing the drain current of the first junction-free transistor with a preset value, if the drain current is smaller than the preset value, the memory is in the second storage state, and if the drain current is larger than or equal to the preset value, the memory is in the first storage state.

In an embodiment, further comprising: when an erase operation is performed, an erase voltage is applied to the second junction-free transistor, the erase voltage being opposite in electrical property to the write voltage, and the charge stored by the charge trapping layer is released, so that the memory is changed from the second storage state to the first storage state.

The memory provided by the embodiment of the disclosure is a 2T0C memory formed by a first junction-free transistor and a second junction-free transistor, wherein a charge trapping layer is arranged on one surface (a second surface of a second channel region) of the second junction-free transistor, which is away from a gate structure, and the charge trapping layer can be used as an electron trap (electron trap) to trap and store charges when the second junction-free transistor is conducted; when the first non-junction transistor is turned on, the charge stored in the charge trapping layer can affect the first non-junction transistor turn-on current (i.e., drain current), and thus the storage state of the memory can be determined by the change of the first non-junction transistor turn-on current. The 2T0C memory does not need a capacitor, does not have large power consumption and large area caused by the capacitor, greatly reduces the size and the power consumption of the memory, has simple manufacturing process and is convenient to popularize and apply.

Drawings

FIG. 1A is a schematic diagram of a memory according to an embodiment of the present disclosure, and FIG. 1B is a schematic diagram of a cross section along line A-A' in FIG. 1A;

FIG. 2 is a schematic diagram showing a relationship between a first channel region and a first source region and a first drain region of a memory according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram showing a relationship between a first channel region and a first source region and a first drain region of a memory according to another embodiment of the present disclosure;

FIG. 4 is a schematic diagram showing a relationship among a first source electrode, a second source electrode, a first drain electrode and a second drain electrode of a memory according to an embodiment of the present disclosure;

FIG. 5 is a schematic cross-sectional view of a memory provided by another embodiment of the present disclosure;

FIG. 6 is a schematic cross-sectional view of a memory provided by yet another embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a memory provided in an embodiment of the present disclosure in a second memory state;

FIG. 8 is a schematic diagram of a memory provided in an embodiment of the present disclosure in a first memory state;

FIG. 9 is a schematic diagram of steps in a method of fabricating a memory according to an embodiment of the present disclosure;

Fig. 10A to 10C are schematic views of a semiconductor structure formed by main steps of a method for manufacturing a memory according to an embodiment of the present disclosure.

Detailed Description

For a 1T1C structure dynamic random access memory (DRAM, dynamic Random Access Memory) consisting of a Transistor (Transistor) and a Capacitor (Capacitor), capacitor leakage affects the memory sensing result, so a timed refresh (refresh) is required, but on one hand, the timed refresh increases the power consumption of the device, and on the other hand, the refresh circuit occupies the area of the memory cell, which hinders the size reduction of the DRAM.

In view of this, embodiments of the present disclosure provide a memory, which is a 2T0C memory formed by a first junction-free transistor and a second junction-free transistor, the memory being provided with a charge trapping layer on a side of the second junction-free transistor facing away from the gate structure (a second surface of the second channel region), the charge trapping layer being capable of trapping and storing charge when the second junction-free transistor is turned on; when the first non-junction transistor is turned on, the charge stored in the charge trapping layer can affect the on-current (i.e. drain current) of the first non-junction transistor, so that the storage state of the memory can be determined by the change of the on-current of the first non-junction transistor. The 2T0C memory does not need a capacitor, does not have large power consumption and large area caused by the capacitor, greatly reduces the size and the power consumption of the memory, has simple manufacturing process and is convenient to popularize and apply.

Specific embodiments of a memory, a method for manufacturing the same, and a method for reading and writing provided by the present disclosure are described in detail below with reference to the accompanying drawings.

Fig. 1A is a schematic structural diagram of a memory according to an embodiment of the present disclosure, and fig. 1B is a schematic sectional view taken along a line A-A' in fig. 1A, referring to fig. 1A and 1B, the memory includes a substrate 100, a first junction-free transistor disposed on the substrate 100, a charge trapping layer 11, and a second junction-free transistor. The first junction-free transistor includes a first semiconductor layer 101, the first semiconductor layer 101 having a first channel region 101C; the charge trapping layer 11 is provided on the surface of the first channel region 101C of the first semiconductor layer 101; the second junction-free transistor includes a second semiconductor layer 121 and a gate structure 124, the second semiconductor layer 121 has a second channel region 121C, the second semiconductor layer 121 is insulated from the first semiconductor layer 101, the gate structure 124 is disposed on a first surface of the second channel region 121C of the second semiconductor layer 121, the charge trapping layer 11 is disposed on a second surface of the second channel region 121C of the second semiconductor layer 121, and the first surface is disposed opposite to the second surface. The charge trapping layer 11 is used to trap and store charge when the second junction-free transistor is turned on, and the charge stored in the charge trapping layer 11 can affect the on-current of the first junction-free transistor. In this embodiment, the first surface and the second surface are disposed opposite to each other in a direction perpendicular to the surface of the substrate 100 (e.g., a Z direction in the drawing).

The first non-junction transistor and the second non-junction transistor form a 2T0C memory, the charge trapping layer 11 is disposed on a side of the second non-junction transistor facing away from the gate structure 124 (i.e., the second surface of the second channel region), and when the second non-junction transistor is turned on, the charge trapping layer 11 can be used as an electron trap (electron trap) to trap charges, thereby storing charges; meanwhile, the charge trapping layer 11 is further disposed on the first semiconductor layer 101, so that the charge stored in the charge trapping layer 11 can affect the magnitude of the on-current of the first junction-free transistor, and thus the storage state of the memory can be determined by the change of the on-current of the first junction-free transistor.

In some embodiments, when the second junction-free transistor is turned on, hot carriers (positive charges in fig. 1B) generated in the second semiconductor layer 121 may accumulate at the bottom of the second channel region 121C, thereby inducing charges opposite to the Hot carriers in the charge trapping layer 11, and capturing the charges by the charge trapping layer 11.

For example, in the present embodiment, the second junction-free transistor is an NMOS transistor, and when an on voltage (positive voltage) and an operating voltage (positive voltage) are applied to the second junction-free transistor to turn on, electrons are transferred to the second drain region 121D of the second semiconductor layer 121 and collide to generate hot carriers (positive charges) that can accumulate on the second surface of the second channel region 121C and induce negative charges in the charge trapping layer 11, thereby realizing trapping of positive charges and storage of negative charges by the charge trapping layer 11. Since the charge stored in the charge trapping layer 11 is negative, when an operating voltage (positive voltage) is applied to the first junction-free transistor, the negative charge stored in the charge trapping layer 11 will reduce the operating voltage, so that the on current (i.e. drain current) of the first junction-free transistor becomes smaller, and further, whether the negative charge is stored in the charge trapping layer 11 can be determined by the magnitude of the on current of the first junction-free transistor, i.e. the storage state of the memory can be determined.

In some embodiments, the charge trapping layer 11 is a composite layer structure that includes a first insulating layer 111, a charge trapping layer 112, and a second insulating layer 113. The first insulating layer 111 is disposed on the surface of the first channel region 101C of the first semiconductor layer 101 in a direction perpendicular to the surface of the substrate 100 (e.g., Z direction in the drawing); the charge trap layer 112 is provided on the surface of the first insulating layer 111; the second insulating layer 113 is disposed on the surface of the charge trap layer 112, and the second insulating layer 113 is in contact with the second surface of the second channel region 121C of the second semiconductor layer 121. That is, the first insulating layer 111, the charge trap layer 112, and the second insulating layer 113 are stacked in this order in a direction perpendicular to the surface of the substrate 100 (e.g., in the Z direction in the drawing).

The charge trap layer 112 serves to trap and store charges. Specifically, when the second junction-free transistor is turned on, hot carriers accumulated on the second surface of the second channel region 121C induce opposite charges in the charge trap layer 112.

In some embodiments, the charge trap layer 112 may be a nitride layer, such as a silicon nitride layer, which is rich in nitrogen particles, and is more likely to induce charges for charge storage. The contact interface between the second insulating layer 113 and the charge trap layer 112 is a nitrogen-rich interface.

The first insulating layer 111 and the second insulating layer 113 may be made of the same material or different materials. If the first insulating layer 111 and the second insulating layer 113 are made of the same material, the memory manufacturing process can be simplified; if the first insulating layer 111 and the second insulating layer 113 are made of different materials, a potential barrier can be formed at the interface between the two materials, so that charge trapping can be more easily realized.

In some embodiments, the first insulating layer 111 is a high dielectric constant layer (i.e., a high K dielectric layer), or a silicon dioxide layer, or a silicon oxynitride layer, the second insulating layer 113 is a high dielectric constant layer (i.e., a high K dielectric layer), or a silicon dioxide layer, or a silicon oxynitride layer, i.e., a structure in which the charge trapping layer 11 is an oxide-nitride-oxide (ONO structure), the high K dielectric layer may include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, and the like. When the second insulating layer 113 is a high dielectric constant layer, it has better ability to control leakage, further improving reliability of the memory.

The substrate 100 may include a silicon substrate, a Germanium (Ge) substrate, a silicon Germanium (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc.; the substrate 100 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, silicon carbide, or the like, and the substrate 100 may also be a stacked structure, such as a silicon/germanium-silicon stack or the like; in addition, the substrate 100 may be an ion doped substrate, may be P-doped, or may be N-doped; the substrate 100 may also have formed therein a plurality of peripheral devices such as field effect transistors, capacitors, inductors, and/or diodes, etc. In the present embodiment, the substrate 100 is a silicon substrate, and may further include other device structures, such as a transistor structure, a metal wiring structure, and the like, but is not illustrated because it is irrelevant to the embodiments of the present disclosure.

In some embodiments, the first semiconductor layer 101 further has a first source region 101S and a first drain region 101D, and the first source region 101S and the first drain region 101D are disposed on both sides of the first channel region 101C, respectively, in a direction parallel to the surface of the substrate 100. For example, in the embodiment shown in fig. 1A and 1B, the first source region 101S, the first channel region 101C, and the first drain region 101D are sequentially disposed along the X direction, that is, along the X direction, and the first source region 101S and the first drain region 101D are disposed on both sides of the first channel region 101C.

The first source region 101S, the first channel region 101C, and the first drain region 101D have the same doping type. In some embodiments, the first source region 101S, the first channel region 101C and the first drain region 101D are made of the same material and have the same doping concentration, for example, the first semiconductor layer 101 is uniformly ion-doped to form the first source region 101S, the first channel region 101C and the first drain region 101D having the same doping concentration; in other embodiments, in order to further improve the performance of the memory, for example, to reduce the contact resistance, in addition to uniformly doping the first semiconductor layer 101, additional ion doping is performed on the first source region 101S and the first drain region 101D, so that the doping types of the first source region 101S, the first channel region 101C and the first drain region 101D are the same, and the doping concentration of the first source region 101S and the first drain region 101D is greater than the doping concentration of the first channel region 101C.

In some embodiments, the first junction-free transistor further includes a first source electrode 102 and a first drain electrode 103, where the first source electrode 102 is disposed on the surface of the first semiconductor layer 101 and contacts the first source region 101S, as an electrical extraction structure of the first source region 101S, and the first drain electrode 103 is disposed on the surface of the first semiconductor layer 101 and contacts the first drain region 101D, as an electrical extraction structure of the first drain region 101D.

In some embodiments, the first source region 101S and the first drain region 101D include protruding regions S1 and S2 protruding from the second semiconductor layer 121, respectively, in a direction parallel to the surface of the substrate 100, the first source electrode 102 is disposed at the protruding region S1 of the first source region 101S, and the first drain electrode 103 is disposed at the protruding region S2 of the first drain region 101D.

For example, as shown in fig. 1B, the protruding region S1 of the first source region 101S and the protruding region S2 of the first drain region 101D are located on both sides of the first channel region 101C in the X direction, respectively. As another example, as shown in fig. 2, fig. 2 is a schematic diagram showing a relationship between a first channel region 101C and a first source region 101S and a first drain region 101D of a memory according to an embodiment of the disclosure, where a protruding region S1 of the first source region 101S and a protruding region S2 of the first drain region 101D are located at two sides of the first channel region 101C along a Y direction, where the Y direction is a direction parallel to a memory surface and perpendicular to an X direction.

For another example, the protruding region S1 of the first source region 101S and the protruding region S2 of the first drain region 101D are located on the same side of the first channel region 101C and are independent from each other. Specifically, as shown in fig. 3, fig. 3 is a schematic diagram showing a relationship between a first channel region 101C and a first source region 101S and a first drain region 101D of a memory according to another embodiment of the present disclosure, in this embodiment, a protruding region S1 of the first source region 101S and a protruding region S2 of the first drain region 101D are located at one side of the first channel region 101C along the Y direction, and the protruding region S1 of the first source region 101S and the protruding region S2 of the first drain region 101D are not contacted, so as to avoid direct conduction of the first source region 101S and the first drain region 101D, wherein the Y direction is a direction parallel to the surface of the substrate 100 and perpendicular to the X direction.

The second semiconductor layer 121 is disposed over the first semiconductor layer 101 and is insulated from the first semiconductor layer 101. In some embodiments, referring to fig. 1A and 1B, the memory further includes an isolation layer 13, the isolation layer 13 is disposed between the first semiconductor layer 101 and the second semiconductor layer 121, so that the second semiconductor layer 121 is insulated from the first semiconductor layer 101, and the charge trapping layer 11 is disposed in the isolation layer 13. The material of the isolation layer 13 includes, but is not limited to, an oxide such as silicon dioxide or silicon oxynitride.

In some embodiments, the material of the second semiconductor layer 121 may be the same as or different from the material of the first semiconductor layer 101. For example, in some embodiments, the first semiconductor layer 101 may be a Si layer, a SiGe layer, or an oxide semiconductor layer, such as a material layer of zinc tin oxide (ZnxSnyO, commonly referred to as "ZTO"), indium zinc oxide (InxZnyO, commonly referred to as "IZO"), zinc oxide (ZnxO), indium gallium zinc oxide (InxGayZnzO, commonly referred to as "IGZO"), indium gallium silicon oxide (InxGaySizO, commonly referred to as "IGSO"), or the like, and the second semiconductor layer 121 is a polysilicon layer or an oxide semiconductor layer, such as an IGZO layer.

With continued reference to fig. 1A and 1B, in some embodiments, the second semiconductor layer 121 further includes a second source region 121S and a second drain region 121D, and the second source region 121S and the second drain region 121D are disposed on two sides of the second channel region 121C along a direction parallel to the surface of the substrate 100. For example, in the embodiment shown in fig. 1A and 1B, the second source region 121S, the second channel region 121C, and the second drain region 121D are sequentially disposed along the X direction, that is, along the X direction, and the second source region 121S and the second drain region 121D are disposed at both sides of the second channel region 121C.

In some embodiments, the second junction-free transistor further includes a second source electrode 122 and a second drain electrode 123, the second source electrode 122 being disposed on a surface of the second semiconductor layer 121 and in contact with the second source region 121S as an electrical extraction structure of the second source region 121S; the second drain electrode 123 is provided on the surface of the second semiconductor layer 121 and contacts the second drain region 121D as an electrical extraction structure of the second drain region 121D. In some embodiments, in a direction parallel to the surface of the substrate 100 (such as the X direction in fig. 1A and 1B), the second source region 121S and the second drain region 121D respectively include a protruding region (not labeled in the drawings) protruding from the gate structure 124, the second source electrode 122 is disposed in the protruding region of the second source region 121S, and the second drain electrode 123 is disposed in the protruding region of the second drain region 121D.

The arrangement of the first source electrode 102, the second source electrode 122, the first drain electrode 103, and the second drain electrode 123 may be changed according to the requirements of the memory fabrication process. In some embodiments, the first source electrode 102, the second source electrode 122, the first drain electrode 103, and the second drain electrode 123 are sequentially arranged along a direction, for example, as shown in fig. 1A and 1B, the first source electrode 102, the second source electrode 122, the first drain electrode 103, and the second drain electrode 123 are sequentially arranged along an X direction; in other embodiments, the first source electrode 102, the second source electrode 122, the first drain electrode 103, and the second drain electrode 123 are arranged in a staggered manner, for example, as shown in fig. 3 and fig. 4, fig. 4 is a schematic diagram of the relationship between the first source electrode 102, the second source electrode 122, the first drain electrode 103, and the second drain electrode 123, where in fig. 4, the second semiconductor layer 121 is shown by a dotted line, the first source electrode 102 and the second source electrode 122 are arranged along the Y direction, the first drain electrode 103 and the second drain electrode 123 are arranged along the Y direction, the first source electrode 102 and the first drain electrode 103 are arranged along the X direction, the second source electrode 122 and the second drain electrode 123 are arranged along the X direction, the X direction and the Y direction are all parallel to the surface of the substrate 100, and the X direction is perpendicular to the Y direction.

The second source region 121S, the second channel region 121C, and the second drain region 121D have the same doping type, and the doping concentrations thereof are the same or different.

As shown in fig. 1A and 1B, the doping type of the second source region 121S, the second channel region 121C, and the second drain region 121D is the same, and the doping concentration is the same. The second semiconductor layer 121 may be uniformly ion-doped to form a second source region 121S, a second channel region 121C, and a second drain region 121D having the same doping concentration.

In other embodiments, the doping concentrations of the different regions of the second semiconductor layer 121 are different, and the second drain region 121D is at least located in the region with high doping concentration, so as to increase the scattering of the second semiconductor layer 121, enable more hot carriers to be deposited at the bottom of the second channel region 121C, increase the charge quantity induced by the charge trapping layer 11, and improve the electrical performance of the memory. For example, fig. 5 is a schematic cross-sectional view of a memory provided in another embodiment of the disclosure, in which the second semiconductor layer 121 includes a first region 121A and a second region 121B disposed along a direction parallel to a surface of the substrate 100 (such as an X direction in fig. 5), a doping concentration of the second region 121B is greater than that of the first region 121A, the second source region 121S is located in the first region 121A, the second drain region 121D is located in the second region 121B, and at least a portion of a region of the second channel region 121C is located in the first region 121A.

In this embodiment, a portion of the second channel region 121C is located in the first region 121A, and another portion is located in the second region 121B, wherein a dimension (e.g., a length along the X direction) of the portion located in the first region 121A is greater than a dimension (e.g., a length along the X direction) of the portion located in the second region 121B, so as to achieve both the conduction performance of the second junction-free transistor and the charge amount induced by the charge trapping layer 11. In other embodiments, the second channel region 121C may also be located entirely in the first region 121A to ensure the conduction performance of the second junction-free transistor.

In this embodiment, the doping concentration of the second region 121B is greater than that of the first region 121A, and the projection of the gate structure 124 in the Z direction partially coincides with the second region 121B, so that the electron collision degree can be improved, and more charges are generated.

In some embodiments, as shown in fig. 6, fig. 6 is a schematic cross-sectional view of a memory provided in another embodiment of the disclosure, the second semiconductor layer 121 further includes a third region 121E, the first region 121A and the second region 121B are disposed along a direction parallel to the surface of the substrate 100 (in the X direction in the drawing), where the doping concentration of the second region 121B and the third region 121E is greater than that of the first region 121A, the second source region 121S is located in the third region 121E, the second drain region 121D is located in the second region 121B, a portion of the second channel region 121C is located in the first region 121A, and another portion is located in the second region 121B. The second source region 121S is a region with a higher doping concentration, so that the contact resistance between the second source region 121S and the second source electrode 122 can be further reduced, and the electrical performance of the memory can be improved. In other embodiments, the second channel region 121C may also be entirely located in the first region 121A.

With continued reference to fig. 1A and 1B, the gate structure 124 is disposed on the surface of the second semiconductor layer 121, the gate structure 124 includes a gate dielectric layer 1241 and a conductive layer 1242, the gate dielectric layer 1241 is disposed on the first surface of the second semiconductor layer 121 along a direction perpendicular to the surface of the substrate 100 (e.g. Z direction), and the conductive layer 1242 is disposed on the surface of the gate dielectric layer 1241 along a direction perpendicular to the surface of the memory device (e.g. Z direction). The gate dielectric layer 1241 is used to isolate the conductive layer 1242 from the second channel region 121C, so that the conductivity of the second channel region 121C can be controlled by the field effect generated between the potential of the conductive layer 1242 and the second channel region 121C, i.e. the on or off state of the second channel region 121C can be switched by the voltage applied across the conductive layer 1242. The gate dielectric layer 1241 includes, but is not limited to, an oxide layer or a high-K dielectric layer, and the conductive layer 1242 includes, but is not limited to, a metal tungsten layer or a polysilicon layer. In some embodiments, the second junction-free transistor further includes a gate electrode 125, where the gate electrode 125 is disposed on a surface of the gate structure 124 and is in contact with the conductive layer 1242 to serve as an electrical extraction structure of the gate structure 124.

In some embodiments, in a direction perpendicular to the surface of the substrate 100 (e.g., the Z-direction in the figure), the front projection of the gate structure 124 onto the surface of the substrate 100 completely overlaps with the front projection of the charge trapping layer 11 onto the surface of the substrate 100, or the front projection of the charge trapping layer 11 onto the surface of the substrate 100 is within the front projection of the gate structure 124 onto the surface of the substrate 100. The projection of the charge trapping layer 11 onto the surface of the substrate 100 and the projection of the gate structure 124 onto the surface of the substrate 100 mean that the edge of the gate structure 124 protrudes beyond the edge of the charge trapping layer 11 in the extending direction (i.e., the Y direction in the drawing) of the gate structure 124, i.e., the gate structure 124 extends beyond the second channel region 121C in the extending direction thereof, so that sufficient conduction of carriers can be generated.

The memory provided by the embodiments of the present disclosure is a 2T0C memory formed by a first junction-free transistor and a second junction-free transistor, wherein the first junction-free transistor may be used as a read transistor of the memory, the second junction-free transistor may be used as a write transistor of the memory, and when the memory performs a write operation, if the second junction-free transistor (write transistor) is turned on, the charge trapping layer 11 may be capable of trapping and storing charges; when the memory performs a read operation, the first transistor (read transistor) is turned on, if the charge trapping layer 11 stores charge, the on current (i.e. drain current) of the first transistor is changed, for example, reduced, and if the charge trapping layer 11 does not store charge, the on current of the first transistor is unchanged (the on current is consistent with the on current when the first transistor is not affected by the charge trapping layer 11), so that the storage state of the memory can be determined by the change of the on current of the first transistor.

The embodiment of the disclosure also provides a read-write method of the memory. The read-write method comprises the following steps of; when a writing operation is executed, an opening voltage is applied to the second junction-free transistor to control the second junction-free transistor to be conducted, and a writing voltage is applied to the second junction-free transistor, and the charge trapping layer 11 captures and stores charges, so that the memory is changed from a first storage state to a second storage state; when a read operation is performed, a read voltage is applied to the first junction-free transistor, and a storage state of the memory is determined according to a drain current of the first junction-free transistor. In some embodiments, the first storage state is a state in which the memory does not store charge, and the second storage state is a state in which the memory stores charge. In some embodiments, the initial storage state of the memory is a first storage state, and after the charge trapping layer 11 traps charge, the memory is changed from the first storage state to a second storage state.

Specifically, referring to fig. 7, a schematic diagram of a memory in a second memory state according to an embodiment of the disclosure is shown, in which a turn-on voltage Vg is applied to a gate electrode 125 of a second junction-free transistor and a write voltage (i.e., an operating voltage) Vd1 is applied to a second drain electrode 123 of the second junction-free transistor when performing a write operation. In this embodiment, the on voltage Vg is a positive voltage, and the write voltage is a power supply voltage Vdd, which is a positive voltage. When the second junction-free transistor is turned on under the control of the on voltage Vg, a drain current exists between the second source region 121S and the second drain region 121D, electrons (such as negative charges in the second semiconductor layer in fig. 7) are transferred to the second drain region 121D and collide to generate hot carriers (such as positive charges in the second semiconductor layer 121 in fig. 7) which can accumulate at the bottom of the second channel region 121C and induce opposite charges (such as negative charges at the contact interface of the charge trap layer 112 and the second insulating layer 113 in fig. 7) in the charge trap layer 11, and the opposite charges are stored in the charge trap layer 11, so that the storage state of the memory is changed to the second storage state.

It is understood that when performing the write operation, if the storage state of the memory is required to be the first storage state (i.e. the same as the initial storage state), the control voltage may not be applied to the transistor, or the applied control voltage is smaller than the turn-on voltage of the second non-junction transistor, so as to avoid the turn-on of the second non-junction transistor.

With continued reference to fig. 7, when performing a read operation, a read voltage (operating voltage) Vd2 is applied to the first junction-free transistor, that is, a read voltage Vd2 is applied to the first drain electrode 103 of the first junction-free transistor, and a storage state of the memory is determined according to a drain current of the first junction-free transistor. In some embodiments, the read voltage Vd2 may be a power supply voltage Vdd, and no voltage is applied to the gate electrode 125 and the second drain electrode 123 at the time of a read operation.

In some embodiments, determining the storage state of the memory from the drain current of the first junction-free transistor comprises: comparing the drain current of the first junction-free transistor with a preset value, if the drain current is smaller than the preset value, the memory is in a second storage state, and if the drain current is larger than or equal to the preset value, the memory is in a first storage state. In some embodiments, the predetermined value may be a value of the conduction current when the first junction-free transistor is not affected by the charge trapping layer 11, in other embodiments, the predetermined value is less than a value of the conduction current when the first junction-free transistor is not affected by the charge trapping layer 11, but greater than a value of the conduction current when the first junction-free transistor is affected by the charge trapping layer 11.

Since the charge stored in the charge trapping layer 11 is negative, it causes the drain current of the first junction-less transistor to become small. That is, if the drain current is smaller than the preset value, it indicates that the drain current is affected, that is, the charge is stored in the charge trapping layer 11, and the memory is in the second storage state; if the drain current is greater than or equal to the preset value, it indicates that the drain current is not affected, i.e. no charge is stored in the charge trapping layer 11, and the memory is in the first storage state.

In an embodiment, the method for reading and writing the memory further includes an erasing method. When the erase operation is performed, an erase voltage Verase is applied to the second junction-free transistor, the erase voltage Verase being opposite in electrical property to the write voltage Vd1, and the charge stored in the charge trapping layer 11 is released, so that the memory is changed from the second storage state to the first storage state.

Specifically, referring to fig. 8, a schematic diagram of a memory in a first memory state according to an embodiment of the disclosure is shown, in which an erase voltage Verase is applied only to the second drain electrode 123 of the second junction-free transistor, a turn-on voltage is not applied to the second junction-free transistor, and a read voltage is not applied to the first junction-free transistor when an erase operation is performed. In this embodiment, when the erase voltage Verase is a negative voltage, the charges stored in the charge trapping layer 11 are released, and even if the charge trapping layer 11 is restored to the non-charge state, the memory is changed from the second storage state to the first storage state, so that the memory is erased, thereby facilitating the read/write operation of the subsequent memory.

The embodiment of the disclosure also provides a manufacturing method of the memory. Fig. 9 is a schematic step diagram of a method for manufacturing a memory according to an embodiment of the disclosure, referring to fig. 9, the method includes: step S90, forming a first semiconductor layer on a substrate, wherein the first semiconductor layer is used for forming a first junction-free transistor; step S91, forming a charge trapping layer on the first semiconductor layer, wherein the contact area of the first semiconductor layer and the charge trapping layer is a first channel region; step S92, forming a second semiconductor layer which covers the charge trapping layer and is insulated from the first semiconductor layer; and forming a gate structure on the surface of the second semiconductor layer, wherein the contact area of the second semiconductor layer and the gate structure is a second channel region.

Fig. 10A to 10C are schematic views of a semiconductor structure formed by main steps of a manufacturing method.

Referring to fig. 9 and 10A, in step S90, a first semiconductor layer 101 is formed on a substrate 100, and the first semiconductor layer 101 is used to form a first junction-free transistor. In this embodiment, a silicon substrate is used as the substrate 100.

In this step, a first semiconductor material layer is covered on the substrate 100 and patterned to form a first semiconductor layer 101. The first semiconductor material layer may be a silicon layer, a SiGe layer, or an IGZO layer. In this step, the first semiconductor layer 101 may be doped to form an N-type or P-type semiconductor layer.

Referring to fig. 9 and 10B, in step S91, a charge trapping layer 11 is formed on a first semiconductor layer 101, a region of the first semiconductor layer 101 contacting the charge trapping layer 11 is a first channel region 101C, and regions of the first semiconductor layer 101 located at two sides of the first channel region 101C in a direction parallel to a substrate 100 are a first source region 101S and a first drain region 101D.

As an example, the presently disclosed embodiments provide a method of forming the charge trapping layer 11. The method comprises the following steps:

A first insulating material layer, a trap material layer, and a second insulating material layer are sequentially formed on the first semiconductor layer 101. Wherein the first layer of insulating material includes, but is not limited to, a silicon dioxide layer, a silicon oxynitride layer, or a high-K dielectric layer, and the layer of trap material includes, but is not limited to, a layer of nitrogen-containing material, such as a silicon nitride layer; the second insulating material layer includes, but is not limited to, a silicon dioxide layer, a silicon oxynitride layer, or a high-K dielectric layer. Methods of forming the first insulating material layer, the trap material layer, and the second insulating material layer include, but are not limited to, chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), and the like.

The second insulating material layer, the trap material layer, and the first insulating material layer are patterned to form a second insulating layer 113, a charge trap layer 112, and a first insulating layer 111, and the second insulating layer 113, the charge trap layer 112, and the first insulating layer 111 constitute the charge trapping layer 11.

In some embodiments, after forming the charge trapping layer 11, the following steps are further included: the first source region 101S and the first drain region 101D of the first semiconductor layer 101 are ion-implanted with the charge trapping layer 11 as a mask to form the first source region 101S and the first drain region 101D having the same doping type as the first channel region 101C and different doping concentrations, the doping concentrations of the first source region 101S and the first drain region 101D being greater than those of the first channel region 101C.

In some embodiments, after forming the charge trapping layer 11, the method further includes the steps of: an isolation layer 13 is formed, the isolation layer 13 covers a portion of the first semiconductor layer 101, and the charge trapping layer 11 is exposed. The material of the isolation layer 13 includes, but is not limited to, an oxide such as silicon dioxide or silicon oxynitride.

Referring to fig. 9 and 10C, in step S92, a second semiconductor layer 121 is formed, the second semiconductor layer 121 covers the charge trapping layer 11 and is insulated from the first semiconductor layer 101, and the second semiconductor layer 121 is used for forming a second junction-free transistor; a gate structure 124 is formed on the surface of the second semiconductor layer 121, and a region of the second semiconductor layer 121 in contact with the gate structure 124 is a second channel region 121C. The charge trapping layer 11 is used to trap and store charge when the second junction-free transistor is turned on, and the charge stored in the charge trapping layer 11 can affect the drain current of the first junction-free transistor.

In some embodiments, the second semiconductor layer 121 is formed on the surfaces of the isolation layer 13 and the charge trapping layer 11, and the isolation layer 13 and the charge trapping layer 11 are disposed between the second semiconductor layer 121 and the first semiconductor layer 101, so that insulation isolation between the second semiconductor layer 121 and the first semiconductor layer 101 can be achieved. The material of the second semiconductor layer 121 may be the same as or different from the material of the first semiconductor layer 101. In some embodiments, the second semiconductor layer 121 is a polysilicon layer or an IGZO layer.

The region of the second semiconductor layer 121 in contact with the gate structure 124 is a second channel region 121C, and the regions of the second semiconductor layer 121 located at both sides of the second channel region 121C in the direction parallel to the substrate 100 are a second source region 121S and a second drain region 121D. The gate structure 124 includes a gate dielectric layer 1241 and a conductive layer 1242, where the gate dielectric layer 1241 is disposed on the surface of the second semiconductor layer 121 along a direction perpendicular to the surface of the substrate 100 (e.g., a Z direction in the drawing), and the conductive layer 1242 is disposed on the surface of the gate dielectric layer 1241 along a direction perpendicular to the surface of the substrate 100 (e.g., a Z direction in the drawing).

In some embodiments, the method of manufacturing further comprises: referring to fig. 1A and 1B, a first source electrode 102, a first drain electrode 103, a second source electrode 122, and a second drain electrode 123 are formed, where the first source electrode 102 is disposed on the surface of the first semiconductor layer 101 and contacts the first source region 101S, and is used as an electrical extraction structure of the first source region 101S; the first drain electrode 103 is disposed on the surface of the first semiconductor layer 101 and contacts the first drain region 101D as an electrical extraction structure of the first drain region 101D; the second source electrode 122 is disposed on the surface of the second semiconductor layer 121 and contacts the second source region 121S as an electrical extraction structure of the second source region 121S; the second drain electrode 123 is provided on the surface of the second semiconductor layer 121 and contacts the second drain region 121D as an electrical extraction structure of the second drain region 121D. In this step, the manufacturing method further includes a step of forming a gate electrode 125, where the gate electrode 125 is disposed on the surface of the gate structure 124 and electrically connected to the gate structure 124 to serve as an electrical lead-out structure of the gate structure 124.

In some embodiments, the doping types of the second source region 121S, the second channel region 121C, and the second drain region 121D are the same and have the same doping concentration, for example, in the embodiments shown in fig. 10A to 10C, the doping types of the second source region 121S, the second channel region 121C, and the second drain region 121D are the same and have the same doping concentration.

In other embodiments, the doping types of the second source region 121S, the second channel region 121C and the second drain region 121D are the same and have different doping concentrations, and the manufacturing method further includes a step of forming the second semiconductor layer 121 having different doping concentrations. The method comprises the following steps: forming a second semiconductor material layer which covers the charge trapping layer 11 and is insulated from the first semiconductor layer 101, for example, the second semiconductor material layer covers the isolation layer 13 and the charge trapping layer 11; a portion of the second semiconductor material layer is doped to form a first region 121A and a second region 121B having different doping concentrations, where the doping concentration of the second region 121B is greater than that of the first region 121A, see fig. 5.

In some embodiments, in the step of forming the gate structure 124, the gate structure 124 covers a portion of the first region 121A and a portion of the second region 121B, and then the second channel region 121C contacting the gate structure 124 is partially located in the first region 121A, and another portion is located in the second region 121B; the first region 121A located on one side of the second channel region 121C is referred to as a second source region 121S, and the second region 121B located on the other side of the second channel region 121C is referred to as a second drain region 121D.

In other embodiments, in the step of forming the gate structure 124, the gate structure 124 covers the first region 121A and does not cover the second region 121B, and then the second channel region 121C contacting the gate structure 124 is located entirely in the first region 121A, the first region 121A located at one side of the second channel region 121C is used as the second source region 121S, and the second region 121B located at the other side of the second channel region 121C is used as the second drain region 121D.

The manufacturing method provided by the embodiment of the disclosure can form the 2T0C memory formed by the first junction-free transistor and the second junction-free transistor, and the 2T0C memory does not need a capacitor, does not have large power consumption and large area caused by the capacitor, greatly reduces the size and the power consumption of the memory, has simple manufacturing process and is convenient to popularize and apply.

The foregoing is merely a preferred embodiment of the present disclosure, and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present disclosure, which are intended to be comprehended within the scope of the present disclosure.

Claims

1. A memory, comprising:

a substrate;

A first junction-free transistor disposed on the substrate, comprising a first semiconductor layer having a first channel region;

a charge trapping layer disposed on a surface of the first channel region of the first semiconductor layer;

The second junction-free transistor comprises a second semiconductor layer and a gate structure, wherein the second semiconductor layer is provided with a second channel region, the second semiconductor layer is insulated and isolated from the first semiconductor layer, the gate structure is arranged on the first surface of the second channel region of the second semiconductor layer, the charge trapping layer is arranged on the second surface of the second channel region of the second semiconductor layer, and the first surface and the second surface are arranged oppositely.

2. The memory of claim 1, wherein the charge trapping layer comprises:

a first insulating layer disposed on a surface of the first channel region of the first semiconductor layer;

A charge trap layer disposed on a surface of the first insulating layer;

And a second insulating layer disposed on a surface of the charge trap layer, and the second insulating layer is in contact with the second surface of the second channel region of the second semiconductor layer.

3. The memory of claim 2, wherein the charge trapping layer is a nitride layer and the contact interface of the second insulating layer and the charge trapping layer is a nitrogen-rich interface.

4. The memory of claim 1, wherein the first semiconductor layer further has a first source region and a first drain region, the first source region and the first drain region being disposed on both sides of the first channel region, respectively, in a direction parallel to the substrate surface, the first junction-free transistor further comprising a first source electrode and a first drain electrode, the first source electrode being disposed on the first semiconductor layer surface and in contact with the first source region, the first drain electrode being disposed on the first semiconductor layer surface and in contact with the first drain region.

5. The memory according to claim 4, wherein the first source region and the first drain region each include a convex region protruding from the second semiconductor layer in a direction parallel to the substrate surface, wherein the first source electrode is provided in the convex region of the first source region, and wherein the first drain electrode is provided in the convex region of the first drain region.

6. The memory of claim 5, wherein the protruding regions of the first source region and the first drain region are on the same side of the first channel region and are independent of each other; or the first source region and the protruding region of the first drain region are located on different sides of the first channel region.

7. The memory of claim 1, wherein the second semiconductor layer further has a second source region and a second drain region, the second source region and the second drain region being disposed on both sides of the second channel region, respectively, in a direction parallel to the substrate surface, the second junction-free transistor further comprising a second source electrode and a second drain electrode, the second source electrode being disposed on the surface of the second semiconductor layer and in contact with the second source region, the second drain electrode being disposed on the surface of the second semiconductor layer and in contact with the second drain region.

8. The memory of claim 7, wherein the second semiconductor layer comprises a first region and a second region disposed in a direction parallel to the substrate surface, the second region having a doping concentration greater than that of the first region, the second source region being located in the first region, the second drain region being located in the second region, and at least a portion of the second channel region being located in the first region.

9. The memory according to claim 7, wherein the second semiconductor layer includes a third region, a first region, and a second region which are arranged in a direction parallel to the surface of the substrate, wherein a doping concentration of the second region and the third region is larger than that of the first region, wherein the second source region is located in the third region, wherein the second drain region is located in the second region, wherein a part of the second channel region is located in the first region, and wherein the other part is located in the second region.

10. The memory of claim 1, wherein an orthographic projection of the gate structure at the substrate surface completely overlaps an orthographic projection of the charge trapping layer at the substrate surface or the orthographic projection of the charge trapping layer at the substrate surface is within an orthographic projection of the gate structure at the substrate surface.

11. The memory of claim 1, further comprising an isolation layer disposed between the first semiconductor layer and the second semiconductor layer to insulate the second semiconductor layer from the first semiconductor layer, the charge trapping layer disposed within the isolation layer.

12. A method of manufacturing a memory, comprising:

Forming a first semiconductor layer on a substrate, the first semiconductor layer being used to form a first junction-free transistor;

Forming a charge trapping layer on the first semiconductor layer, wherein a region of the first semiconductor layer, which is in contact with the charge trapping layer, is a first channel region;

Forming a second semiconductor layer overlying the charge trapping layer and insulated from the first semiconductor layer, the second semiconductor layer for forming a second junction-free transistor; and forming a gate structure on the surface of the second semiconductor layer, wherein the contact area of the second semiconductor layer and the gate structure is a second channel region.

13. The method of manufacturing a memory according to claim 12, wherein the step of forming a charge trapping layer over the first semiconductor layer comprises:

sequentially forming a first insulating material layer, a trap material layer and a second insulating material layer on the first semiconductor layer;

And patterning the second insulating material layer, the trap material layer and the first insulating material layer to form a second insulating layer, a charge trap layer and a first insulating layer, wherein the second insulating layer, the charge trap layer and the first insulating layer form the charge trapping layer.

14. The method of manufacturing a memory device according to claim 12, further comprising, after the step of forming a charge trapping layer over the first semiconductor layer:

Forming an isolation layer that covers a portion of the first semiconductor layer and exposes the charge trapping layer;

And forming the second semiconductor layer on the surfaces of the isolation layer and the charge trapping layer.

15. The method of manufacturing a memory device according to claim 12, wherein the first semiconductor layer includes a first source region and a first drain region provided on both sides of the first channel region, wherein the second semiconductor layer includes a second source region and a second drain region provided on both sides of the second channel region, and wherein the method further comprises:

The method comprises the steps of forming a first source electrode, a first drain electrode, a second source electrode and a second drain electrode, wherein the first source electrode is arranged on the surface of the first semiconductor layer and is in contact with the first source region, the first drain electrode is arranged on the surface of the first semiconductor layer and is in contact with the first drain region, the second source electrode is arranged on the surface of the second semiconductor layer and is in contact with the second source region, and the second drain electrode is arranged on the surface of the second semiconductor layer and is in contact with the second drain region.

16. The method of manufacturing a memory according to claim 12, wherein the step of forming the second semiconductor layer includes:

Forming a second semiconductor material layer covering the charge trapping layer and insulated from the first semiconductor layer;

And doping part of the second semiconductor material layer to form a first region and a second region with different doping concentrations, wherein the doping concentration of the second region is larger than that of the first region.

17. A read-write method, characterized by being applied to the memory according to any one of claims 1 to 11, comprising;

when a write operation is executed, applying a starting voltage to the second junction-free transistor to control the second junction-free transistor to be conducted, and applying a write voltage to the second junction-free transistor, wherein the charge trapping layer captures and stores charges so that the memory is changed from a first storage state to a second storage state;

And when a read operation is executed, applying a read voltage to the first junction-free transistor, and determining the storage state of the memory according to the drain current of the first junction-free transistor.

18. The method of claim 17, wherein determining the storage state of the memory based on the drain current of the first junction-free transistor comprises: comparing the drain current of the first junction-free transistor with a preset value, if the drain current is smaller than the preset value, the memory is in the second storage state, and if the drain current is larger than or equal to the preset value, the memory is in the first storage state.

19. The method of reading and writing as recited in claim 17, further comprising:

When an erase operation is performed, an erase voltage is applied to the second junction-free transistor, the erase voltage being opposite in electrical property to the write voltage, and the charge stored by the charge trapping layer is released, so that the memory is changed from the second storage state to the first storage state.