CN118571856A - Low-inductance symmetrical SiC MOSFET device packaging structure and method - Google Patents
Low-inductance symmetrical SiC MOSFET device packaging structure and method Download PDFInfo
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000000919 ceramic Substances 0.000 claims abstract description 110
- 229910052751 metal Inorganic materials 0.000 claims abstract description 83
- 239000002184 metal Substances 0.000 claims abstract description 83
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052802 copper Inorganic materials 0.000 claims abstract description 29
- 239000010949 copper Substances 0.000 claims abstract description 29
- 230000017525 heat dissipation Effects 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims description 29
- 238000003466 welding Methods 0.000 claims description 16
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 238000005245 sintering Methods 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 37
- 229910010271 silicon carbide Inorganic materials 0.000 description 36
- 239000000463 material Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
The utility model provides a SiC MOSFET device packaging structure and method of low sense symmetry, in the structure, be equipped with the heat dissipation copper base plate in the casing, first copper-clad ceramic plate welds on the heat dissipation copper base plate, first copper-clad ceramic plate has the first metal level of connecting the heat dissipation copper base plate and the second metal level that is located on the first copper-clad ceramic plate, the second metal level is relative to first metal level, a plurality of power chips distribute on the first copper-clad ceramic plate, the power chip includes first power pole and second power pole, first power pole connects the second metal level, the second copper-clad ceramic plate is located on the first copper-clad ceramic plate, the second copper-clad ceramic plate has the third metal level of connecting the second metal level and is located on the second copper-clad ceramic plate, fourth metal level electrical connection second power pole relative to the third metal level, power terminal includes the wire outlet terminal of locating on the first copper-clad ceramic plate and locates on the second copper-clad ceramic plate, a plurality of signal terminals locate on the first copper-clad ceramic plate.
Description
Technical Field
The invention belongs to the technical field of power electronics, and particularly relates to a low-inductance symmetrical SiC MOSFET device packaging structure and a packaging method.
Background
The medium-low voltage direct current power grid has the advantages of high power density, low line loss and high electric energy quality, and can be widely applied to the field of renewable energy sources. The direct current power grid is difficult to break due to faults, the requirement on the protection action speed is high, and the solid state circuit breaker based on the power semiconductor device is extremely high in breaking speed, so that the solid state circuit breaker is key protection equipment applied to a medium-low voltage direct current network.
The silicon carbide (SiC) power device based on the third generation wide bandgap semiconductor material has the advantages of low on-resistance, high switching frequency, high temperature resistance, high pressure resistance and the like, and provides a new choice for the power device of the solid-state circuit breaker. However, due to the limitations of semiconductor materials and manufacturing process technologies, single power semiconductor devices have limited capacity and often need to be used in parallel when applied to solid state circuit breakers to enhance turn-off capability. The direct parallel connection of the separating devices has the problems of larger stray inductance, larger volume and poor balance of all parallel branches. The traditional SiC power device packaging technology is that the lower surface of a SiC chip is welded at the upper copper layer of a DBC, the upper surface of the SiC chip is connected with other independent upper copper layers by using a bonding aluminum wire, the lower copper layer of the DBC is welded on a substrate, the substrate is directly connected with a shell for heat dissipation, and different layers are connected through solder layers. However, the package structure has the problems of larger stray inductance and poorer balance of parallel branches. In order to improve the parallel current sharing performance of the multi-chip and reduce the stray inductance of the package, the package structure needs to be improved.
The above information disclosed in the background section is only for enhancement of understanding of the background of the invention and therefore may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
In order to solve the technical problems, the invention provides a low-inductance symmetrical SiC MOSFET device packaging structure and a packaging method, which have higher power density, increase current balance of parallel chips and improve the performance of a solid-state direct-current circuit breaker.
The low-inductance symmetrical SiC MOSFET device packaging structure comprises:
A shell in which a heat dissipation copper substrate is arranged,
A first copper-clad ceramic plate welded to the heat-dissipating copper substrate, the first copper-clad ceramic plate having a first metal layer connected to the heat-dissipating copper substrate and a second metal layer on the first copper-clad ceramic plate, the second metal layer being opposite to the first metal layer,
A plurality of power chips distributed on the first copper-clad ceramic plate, the power chips including a first power pole and a second power pole, the first power pole being connected to the second metal layer,
A second copper-clad ceramic plate provided on the first copper-clad ceramic plate, the second copper-clad ceramic plate having a third metal layer connected to the second metal layer and a fourth metal layer provided on the second copper-clad ceramic plate, the fourth metal layer being electrically connected to the second power electrode with respect to the third metal layer,
A plurality of power terminals, wherein the power terminals comprise an outgoing line power terminal arranged on the first copper-clad ceramic plate and an incoming line terminal arranged on the second copper-clad ceramic plate,
And a plurality of signal terminals arranged on the first copper-clad ceramic plate.
In the SiC MOSFET device packaging structure with the low-inductance symmetry, power chips are distributed in a sector shape on the first copper-clad ceramic plate relative to the incoming line terminal.
In the SiC MOSFET device packaging structure with the low-inductance symmetry, the first metal layer is arranged in the Kelvin source metal area corresponding to each power chip respectively.
In the SiC MOSFET device packaging structure with the low-inductance symmetry, the fourth metal layer is electrically connected with the second power poles of the power chips in a bonding wire bonding mode.
In the SiC MOSFET device packaging structure with the low-inductance symmetry, the third metal layer is a negative electrode bus.
In the low-inductance symmetrical SiC MOSFET device packaging structure, the low-inductance symmetrical SiCMOSFET device packaging structure further comprises an NTC thermistor arranged in the shell.
In the SiC MOSFET device packaging structure with the low-inductance symmetry, a plurality of power chips are symmetrically distributed on the first copper-clad ceramic plate.
In the SiC MOSFET device packaging structure with the low-inductance symmetry, a plurality of power chips, a first copper-clad ceramic plate, a second copper-clad ceramic plate, a plurality of power terminals and a plurality of signal terminals are two groups to form two same modules.
In the SiC MOSFET device packaging structure with the low-inductance symmetry, two modules are independently used, used in parallel or used in series through connection of the incoming line terminals.
The packaging method of the low-inductance symmetrical SiC MOSFET device packaging structure comprises the following steps of,
Processing a first copper-clad ceramic plate and a second copper-clad ceramic plate, wherein a second metal layer of the first copper-clad ceramic plate is divided into a plurality of conductive areas according to set gaps, and the second copper-clad ceramic plate is processed into a sector shape;
Arranging a power chip and a second copper-clad ceramic plate, wherein the second copper-clad ceramic plate is arranged on the first copper-clad ceramic plate, the third metal layer is welded with the second metal layer, a plurality of power chips are distributed on the first copper-clad ceramic plate through a silver sintering or welding process, the first power electrode is connected with the second metal layer, the second power electrode is electrically connected with the fourth metal layer through bonding wire bonding, the control electrode and the Kelvin source electrode are electrically connected with a metal area,
Welding a power terminal and a signal terminal on a first copper-clad ceramic substrate, connecting a first metal layer of the first copper-clad ceramic substrate with a heat dissipation copper substrate through a welding process,
And the shell is additionally arranged, so that the heat dissipation copper substrate is tightly connected with the shell.
Compared with the prior art, the invention has the following advantages:
The SiC MOSFET device packaging structure with the symmetrical low inductance optimizes the layout of the power chip and adopts a plurality of copper-clad ceramic plates to form a multi-layer conductive path, thereby being beneficial to reducing the stray inductance of the package and the stray difference of parallel branches, improving the parallel current sharing performance of the SiC power chip and reducing the off overvoltage peak value.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
FIG. 1 is a schematic diagram of a low inductance symmetrical SiC MOSFET device package structure in one embodiment of the invention;
FIG. 2 is a schematic diagram of the connection of a low inductance symmetrical SiC MOSFET device package structure in one embodiment of the invention;
FIG. 3 is a schematic cross-sectional view of a low inductance symmetrical SiC MOSFET device package structure in one embodiment of the invention;
fig. 4 is a schematic circuit diagram of a low inductance symmetrical SiC MOSFET device package structure in one embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the substances, and not restrictive of the invention. It should be further noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
In addition, the embodiments of the present invention and the features of the embodiments may be combined with each other without collision. The technical scheme of the present invention will be described in detail below with reference to the accompanying drawings in combination with embodiments.
Unless otherwise indicated, the exemplary implementations/embodiments shown are to be understood as providing exemplary features of various details of some of the ways in which the technical concepts of the present invention may be practiced. Thus, unless otherwise indicated, the features of the various implementations/embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concepts of the present invention.
Cross-hatching and/or shading may be used in the drawings to generally clarify the boundaries between adjacent components. As such, the presence or absence of cross-hatching or shading does not convey or represent any preference or requirement for a particular material, material property, dimension, proportion, commonality between illustrated components, and/or any other characteristic, attribute, property, etc. of a component, unless indicated. In addition, in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. While the exemplary embodiments may be variously implemented, the particular process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in reverse order from that described. Moreover, like reference numerals designate like parts.
When an element is referred to as being "on" or "over", "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. For this reason, the term "connected" may refer to physical connections, electrical connections, and the like, with or without intermediate components.
For descriptive purposes, the invention may use spatially relative terms such as "under … …," under … …, "" under … …, "" lower, "" over … …, "" upper, "" over … …, "" upper "and" side (e.g., as in "sidewall") to describe one component's relationship to another (other) component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the exemplary term "below … …" may encompass both an orientation of "above" and "below". Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising," and variations thereof, are used in the present specification, the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof is described, but the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximation terms and not as degree terms, and as such, are used to explain the inherent deviations of measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.
Referring to fig. 1 to 4, in one embodiment, the low-inductance symmetrical SiC MOSFET device package structure according to the present invention includes:
A housing 2 having a heat dissipating copper substrate 4 disposed therein,
A first copper-clad ceramic plate 6 soldered to the heat-dissipating copper substrate 4, the first copper-clad ceramic plate 6 having a first metal layer connecting the heat-dissipating copper substrate 4 and a second metal layer on the first copper-clad ceramic plate 6, the second metal layer being opposite to the first metal layer,
A plurality of power chips 5 distributed on the first copper-clad ceramic plate 6, the power chips 5 including a first power pole and a second power pole, the first power pole being connected to the second metal layer,
A second copper-clad ceramic plate 7 provided on the first copper-clad ceramic plate 6, the second copper-clad ceramic plate 7 having a third metal layer connected to the second metal layer and a fourth metal layer provided on the second copper-clad ceramic plate 7, the fourth metal layer opposite to the third metal layer being electrically connected to the second power electrode,
A plurality of power terminals 1, the power terminals 1 including an outgoing power terminal 1 provided on a first copper-clad ceramic plate 6 and an incoming terminal provided on a second copper-clad ceramic plate 7,
A plurality of signal terminals 3 provided on the first copper-clad ceramic board 6.
In the preferred embodiment of the low-inductance symmetrical SiC MOSFET device package structure, the power chips 5 are distributed in a sector shape on the first copper-clad ceramic plate 6 with respect to the incoming line terminals.
In the preferred embodiment of the low-inductance symmetrical SiC MOSFET device package structure, the first metal layer is disposed in a kelvin source metal region corresponding to each power chip 5.
In the preferred embodiment of the low-inductance symmetrical SiC MOSFET device package structure, the fourth metal layer is electrically connected to the second power poles of the plurality of power chips 5 by bonding with the bonding wire 8.
In the preferred embodiment of the low-inductance symmetrical SiC MOSFET device package structure, the third metal layer is a negative bus bar.
In the preferred embodiment of the low-inductance symmetrical SiC MOSFET device package structure, the low-inductance symmetrical SiC MOSFET device package structure further includes an NTC thermistor disposed in the housing 2.
In the preferred embodiment of the low-inductance symmetrical SiC MOSFET device package structure, a plurality of power chips 5 are symmetrically distributed on the first copper-clad ceramic plate 6.
In the preferred embodiment of the low inductance symmetrical SiC MOSFET device package structure, the plurality of power chips 5, the first copper-clad ceramic plate 6, the second copper-clad ceramic plate 7, the plurality of power terminals 1 and the plurality of signal terminals 3 are all in two groups to constitute two identical modules.
In the preferred embodiment of the low-inductance symmetrical SiC MOSFET device packaging structure, two modules are used independently, in parallel or in series through connection of the incoming line terminals.
In one embodiment, the first access terminal is configured as an incoming power terminal 1 of a low-inductance symmetrical SiC MOSFET device package structure, and the second access terminal is configured as an outgoing power terminal 1 of a low-inductance symmetrical SiC MOSFET device package structure. The first metal layer of the first copper-clad ceramic plate 6 is provided with a kelvin source metal region corresponding to each power chip 5, and is electrically connected with the second power electrode contact surface of the corresponding power chip 5 by adopting a bonding wire bonding mode. The third metal layer of the second copper-clad ceramic plate 7 is used as a negative bus, and is bonded by a bonding wire to realize electrical connection with the second power electrode contact surface of the multi-power chip 5. The outgoing power terminals 1 are arranged on the third metal layer of the second copper-clad ceramic plate 7, and are electrically connected in a welding mode, and the power chips 5, the copper-clad ceramic plates, the power terminals 1 and the signal terminals 3 are two groups. Each group is arranged in the same manner as previously described, forming two identical modules.
The packaging method of the low-inductance symmetrical SiC MOSFET device packaging structure comprises the following steps of,
Processing a first copper-clad ceramic plate 6 and a second copper-clad ceramic plate 7, wherein the second metal layer of the first copper-clad ceramic plate 6 is divided into a plurality of conductive areas according to set gaps, and the second copper-clad ceramic plate 7 is processed into a sector shape;
A power chip 5 and a second copper-clad ceramic plate 7 are arranged, the second copper-clad ceramic plate 7 is arranged on the first copper-clad ceramic plate 6, the third metal layer is welded with the second metal layer, a plurality of power chips 5 are distributed on the first copper-clad ceramic plate 6 through a silver sintering or welding process, the first power electrode is connected with the second metal layer, the second power electrode is electrically connected with the fourth metal layer through bonding wire bonding, and the control electrode and the Kelvin source electrode are electrically connected with a metal area,
The power terminal 1 and the signal terminal 3 are welded on the first copper-clad ceramic substrate, the first metal layer of the first copper-clad ceramic plate 6 is connected with the heat dissipation copper substrate 4 through a welding process, the shell 2 is additionally arranged, and the substrate and the shell 2 are tightly connected.
In one embodiment, the low-inductance symmetrical SiC MOSFET device packaging structure is a low-inductance symmetrical packaging structure, and comprises a shell 2, wherein a heat dissipation copper substrate 4 is arranged in the shell 2 and is connected with the shell through a threaded fastener. The first copper-clad ceramic plates 6 are divided into two groups, and are arranged on the heat dissipation copper substrate 4 and are connected with the heat dissipation copper substrate 4 in a welding mode. The power chips 5 are divided into two groups and are arranged on the first copper-clad ceramic plate and distributed according to a fan-shaped layout; the first power electrode is connected with the second metal layer of the first copper-clad ceramic plate 6 in a welding mode. The second copper-clad ceramic plate 7 is arranged on the first copper-clad ceramic plate 6, and a third metal layer of the second copper-clad ceramic plate is welded with the second metal layer of the first copper-clad ceramic plate 6; the fourth metal layer is electrically connected with the second power poles of the power chips in a bonding mode through bonding wires 8.
The plurality of power terminals 1 are divided into two groups, the outgoing power terminals are arranged on the first copper-clad ceramic plate 6, the incoming power terminals are arranged on the second copper-clad ceramic plate 7, and the outgoing power terminals are connected in a welding mode. The plurality of signal terminals 3 are provided on the first copper-clad ceramic board 6 and are connected by soldering.
In a preferred embodiment, the encapsulation method comprises the steps of:
the copper-clad ceramic plate is processed, and the second conductive layer of the first copper-clad ceramic plate 6 is divided into a plurality of conductive areas according to set gaps. The second copper-clad ceramic plate 7 is processed into a fan shape.
The power chip and the second copper-clad ceramic board are arranged. The plurality of power chips 5 and the second copper-clad ceramic board 7 are arranged in the layout shown in fig. 2.
And welding the chip. The multi-power chip and the first copper-clad ceramic plate are reliably and electrically connected through silver sintering or welding and other processes.
And bonding wires are connected. And through bonding wire bonding, the second power poles of the power chips are electrically connected with the fourth metal layer of the second copper-clad ceramic plate, and the control poles and the Kelvin source electrodes are electrically connected with the corresponding metal areas.
And welding the power terminals. The power terminals and the signal terminals are arranged on the first copper-clad ceramic substrate 6, and the power terminals are connected by soldering.
And connecting the heat dissipation copper substrate. And the second metal layer of the first copper-clad ceramic plate is reliably connected with the heat dissipation copper substrate through a welding process.
And adding a shell. And the shell is additionally arranged, so that the substrate and the shell are tightly connected.
In the description of the present specification, reference to the terms "one embodiment/manner," "some embodiments/manner," "example," "a particular example," "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/manner or example is included in at least one embodiment/manner or example of the application. In this specification, the schematic representations of the above terms are not necessarily for the same embodiment/manner or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/modes or examples described in this specification and the features of the various embodiments/modes or examples can be combined and combined by persons skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
It will be appreciated by persons skilled in the art that the above embodiments are provided for clarity of illustration only and are not intended to limit the scope of the invention. Other variations or modifications will be apparent to persons skilled in the art from the foregoing disclosure, and such variations or modifications are intended to be within the scope of the present invention.
Claims (10)
1. A low inductance symmetrical SiC MOSFET device package structure, comprising:
A shell in which a heat dissipation copper substrate is arranged,
A first copper-clad ceramic plate welded to the heat-dissipating copper substrate, the first copper-clad ceramic plate having a first metal layer connected to the heat-dissipating copper substrate and a second metal layer on the first copper-clad ceramic plate, the second metal layer being opposite to the first metal layer,
A plurality of power chips distributed on the first copper-clad ceramic plate, the power chips including a first power pole and a second power pole, the first power pole being connected to the second metal layer,
A second copper-clad ceramic plate provided on the first copper-clad ceramic plate, the second copper-clad ceramic plate having a third metal layer connected to the second metal layer and a fourth metal layer provided on the second copper-clad ceramic plate, the fourth metal layer being electrically connected to the second power electrode with respect to the third metal layer,
A plurality of power terminals, wherein the power terminals comprise an outgoing line power terminal arranged on the first copper-clad ceramic plate and an incoming line terminal arranged on the second copper-clad ceramic plate,
And a plurality of signal terminals arranged on the first copper-clad ceramic plate.
2. The low inductance symmetrical SiC MOSFET device package of claim 1, wherein preferably the power chips are fanned out on the first copper clad ceramic plate with respect to the incoming terminals.
3. The low inductance symmetrical SiC MOSFET device package of claim 1, wherein the first metal layer is disposed in a kelvin source metal region corresponding to each power chip, respectively.
4. The low inductance symmetrical SiC MOSFET device package of claim 1, wherein the fourth metal layer is electrically connected to the second power poles of the plurality of power chips by bonding wires.
5. The low inductance symmetrical SiC MOSFET device package of claim 1, wherein the third metal layer is a negative bus bar.
6. The low-inductance symmetrical SiC MOSFET device package of claim 1, further comprising an NTC thermistor disposed within the housing.
7. The low inductance symmetrical SiC MOSFET device package of claim 1, wherein a plurality of power chips are symmetrically distributed on the first copper clad ceramic plate.
8. The low inductance symmetrical SiC MOSFET device package of claim 1, wherein the plurality of power chips, the first copper clad ceramic plate, the second copper clad ceramic plate, the plurality of power terminals and the plurality of signal terminals are all in two groups to form two identical modules.
9. The low inductance symmetrical SiC MOSFET device package of claim 8, wherein the two modules are used alone, in parallel or in series by connection of the incoming line terminals.
10. The method for packaging a low inductance symmetrical SiC MOSFET device package according to any one of claim 1 to 9, comprising the steps of,
Processing a first copper-clad ceramic plate and a second copper-clad ceramic plate, wherein a second metal layer of the first copper-clad ceramic plate is divided into a plurality of conductive areas according to set gaps, and the second copper-clad ceramic plate is processed into a sector shape;
Arranging a power chip and a second copper-clad ceramic plate, wherein the second copper-clad ceramic plate is arranged on the first copper-clad ceramic plate, the third metal layer is welded with the second metal layer, a plurality of power chips are distributed on the first copper-clad ceramic plate through a silver sintering or welding process, the first power electrode is connected with the second metal layer, the second power electrode is electrically connected with the fourth metal layer through bonding wire bonding, the control electrode and the Kelvin source electrode are electrically connected with a metal area,
Welding a power terminal and a signal terminal on a first copper-clad ceramic substrate, connecting a first metal layer of the first copper-clad ceramic substrate with a heat dissipation copper substrate through a welding process,
And the shell is additionally arranged, so that the heat dissipation copper substrate is tightly connected with the shell.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311226026.3A CN118571856A (en) | 2023-09-21 | 2023-09-21 | Low-inductance symmetrical SiC MOSFET device packaging structure and method |
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| CN202311226026.3A CN118571856A (en) | 2023-09-21 | 2023-09-21 | Low-inductance symmetrical SiC MOSFET device packaging structure and method |
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