CN118571856A - Low-inductance symmetrical SiC MOSFET device packaging structure and method - Google Patents
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000000919 ceramic Substances 0.000 claims abstract description 109
- 229910052751 metal Inorganic materials 0.000 claims abstract description 84
- 239000002184 metal Substances 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 31
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052802 copper Inorganic materials 0.000 claims abstract description 29
- 239000010949 copper Substances 0.000 claims abstract description 29
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- 238000003466 welding Methods 0.000 claims description 17
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- 239000004332 silver Substances 0.000 claims description 4
- 238000005245 sintering Methods 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 38
- 229910010271 silicon carbide Inorganic materials 0.000 description 37
- 239000000463 material Substances 0.000 description 6
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- 239000004065 semiconductor Substances 0.000 description 4
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- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
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Abstract
低感对称的SiC MOSFET器件封装结构及方法，结构中，壳体内设有散热铜基板，第一覆铜陶瓷板焊接于散热铜基板上，第一覆铜陶瓷板具有连接散热铜基板的第一金属层和位于第一覆铜陶瓷板上的第二金属层，第二金属层相对于第一金属层，多个功率芯片分布于第一覆铜陶瓷板上，功率芯片包括第一功率极和第二功率极，第一功率极连接第二金属层，第二覆铜陶瓷板设于第一覆铜陶瓷板上，第二覆铜陶瓷板具有连接第二金属层的第三金属层和位于第二覆铜陶瓷板上的第四金属层，相对于第三金属层的第四金属层电气连接第二功率极，功率端子包括设于第一覆铜陶瓷板上的出线功率端子和设于第二覆铜陶瓷板上的进线端子，多个信号端子设于第一覆铜陶瓷板上。
A low-inductance symmetrical SiC MOSFET device packaging structure and method, in which a heat dissipation copper substrate is provided in a shell, a first copper-clad ceramic plate is welded on the heat dissipation copper substrate, the first copper-clad ceramic plate has a first metal layer connected to the heat dissipation copper substrate and a second metal layer located on the first copper-clad ceramic plate, the second metal layer is relative to the first metal layer, a plurality of power chips are distributed on the first copper-clad ceramic plate, the power chip includes a first power pole and a second power pole, the first power pole is connected to the second metal layer, the second copper-clad ceramic plate is provided on the first copper-clad ceramic plate, the second copper-clad ceramic plate has a third metal layer connected to the second metal layer and a fourth metal layer located on the second copper-clad ceramic plate, the fourth metal layer relative to the third metal layer is electrically connected to the second power pole, the power terminal includes an outgoing power terminal provided on the first copper-clad ceramic plate and an incoming terminal provided on the second copper-clad ceramic plate, and a plurality of signal terminals are provided on the first copper-clad ceramic plate.
Description
技术领域Technical Field
本发明属于电力电子学技术领域，特别是低感对称的SiC MOSFET器件封装结构及封装方法。The present invention belongs to the technical field of power electronics, and in particular to a low-inductance symmetrical SiC MOSFET device packaging structure and a packaging method.
背景技术Background Art
中低压直流电网输送功率密度大、线路损耗小、电能质量高的优点，在可再生能源领域有广泛应用。直流电网故障开断困难、对保护动作速度要求高，基于功率半导体器件的固态断路器开断速度极快，是应用于中低压直流网络的关键保护设备。Medium and low voltage DC power grids have the advantages of high transmission power density, low line loss, and high power quality, and are widely used in the field of renewable energy. DC power grid faults are difficult to break, and require high protection action speed. Solid-state circuit breakers based on power semiconductor devices have extremely fast breaking speeds and are key protection devices used in medium and low voltage DC networks.
基于第三代宽禁带半导体材料的碳化硅(SiC)功率器件有着导通电阻低、开关频率高、耐高温高压等优势，为固态断路器的功率器件提供了新的选择。但受半导体材料和制造工艺技术的限制，单个功率半导体器件容量有限，在应用与固态断路器时往往需要并联使用，以提升关断能力。采用分离器件直接并联存在杂散电感较大、体积较大、各并联支路均衡性差的问题。传统SiC功率器件封装技术是将SiC芯片下表面焊接在DBC上铜层处，利用键合铝线将SiC芯片上表面与其余独立的上铜层相连，DBC下铜层焊接在基板上，基板直接与外壳相连进行散热，不同层间通过焊料层连接。但这种封装结构存在杂散电感较大、并联支路均衡性较差的问题。为了提高多芯片并联均流性能，降低封装的杂散电感，需要对封装结构进行改进。Silicon carbide (SiC) power devices based on third-generation wide bandgap semiconductor materials have the advantages of low on-resistance, high switching frequency, high temperature and high pressure resistance, etc., providing a new choice for power devices of solid-state circuit breakers. However, due to the limitations of semiconductor materials and manufacturing process technology, the capacity of a single power semiconductor device is limited. When used in solid-state circuit breakers, they often need to be used in parallel to improve the shutdown capability. The use of separate devices in direct parallel connection has the problems of large stray inductance, large volume, and poor balance of each parallel branch. The traditional SiC power device packaging technology is to weld the lower surface of the SiC chip to the DBC upper copper layer, use bonding aluminum wire to connect the upper surface of the SiC chip to the other independent upper copper layers, weld the DBC lower copper layer to the substrate, and the substrate is directly connected to the shell for heat dissipation. Different layers are connected through solder layers. However, this packaging structure has the problems of large stray inductance and poor balance of parallel branches. In order to improve the current sharing performance of multi-chip parallel connection and reduce the stray inductance of the package, the packaging structure needs to be improved.
在背景技术部分中公开的上述信息仅仅用于增强对本发明背景的理解，因此可能包含不构成本领域普通技术人员公知的现有技术的信息。The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.
发明内容Summary of the invention
为了解决上述技术问题，本发明提供了低感对称的SiC MOSFET器件封装结构及封装方法，功率密度更高、并联芯片电流均衡性增加，提高固态直流断路器的性能。In order to solve the above technical problems, the present invention provides a low-inductance symmetrical SiC MOSFET device packaging structure and packaging method, which has higher power density, increased current balance of parallel chips, and improved performance of solid-state DC circuit breakers.
低感对称的SiC MOSFET器件封装结构包括：The low-inductance symmetrical SiC MOSFET device package structure includes:
壳体，其内设有散热铜基板，The housing has a heat dissipation copper substrate inside.
第一覆铜陶瓷板，其焊接于所述散热铜基板上，所述第一覆铜陶瓷板具有连接散热铜基板的第一金属层和位于第一覆铜陶瓷板上的第二金属层，所述第二金属层相对于所述第一金属层，A first copper-clad ceramic board is welded on the heat dissipation copper substrate, wherein the first copper-clad ceramic board has a first metal layer connected to the heat dissipation copper substrate and a second metal layer located on the first copper-clad ceramic board, wherein the second metal layer is opposite to the first metal layer,
多个功率芯片，其分布于所述第一覆铜陶瓷板上，所述功率芯片包括第一功率极和第二功率极，所述第一功率极连接所述第二金属层，A plurality of power chips are distributed on the first copper-clad ceramic board, the power chip comprises a first power electrode and a second power electrode, the first power electrode is connected to the second metal layer,
第二覆铜陶瓷板，其设于第一覆铜陶瓷板上，所述第二覆铜陶瓷板具有连接第二金属层的第三金属层和位于第二覆铜陶瓷板上的第四金属层，相对于所述第三金属层的所述第四金属层电气连接所述第二功率极，a second copper-clad ceramic board, which is disposed on the first copper-clad ceramic board, wherein the second copper-clad ceramic board has a third metal layer connected to the second metal layer and a fourth metal layer located on the second copper-clad ceramic board, and the fourth metal layer relative to the third metal layer is electrically connected to the second power pole,
多个功率端子，功率端子包括设于第一覆铜陶瓷板上的出线功率端子和设于第二覆铜陶瓷板上的进线端子，A plurality of power terminals, the power terminals comprising an outgoing power terminal arranged on the first copper-clad ceramic board and an incoming power terminal arranged on the second copper-clad ceramic board,
多个信号端子，其设于第一覆铜陶瓷板上。A plurality of signal terminals are arranged on the first copper-clad ceramic board.
所述的低感对称的SiC MOSFET器件封装结构中，功率芯片在第一覆铜陶瓷板上关于所述进线端子呈扇形分布。In the low-inductance symmetrical SiC MOSFET device packaging structure, the power chips are distributed in a fan-shaped manner on the first copper-clad ceramic board with respect to the incoming terminal.
所述的低感对称的SiC MOSFET器件封装结构中，第一金属层设置分别对应每个功率芯片的开尔文源极金属区域。In the low-inductance symmetrical SiC MOSFET device packaging structure, the first metal layer is arranged to correspond to the Kelvin source metal region of each power chip.
所述的低感对称的SiC MOSFET器件封装结构中，第四金属层通过键合线键合的方式与多个功率芯片的第二功率极实现电气连接。In the low-inductance symmetrical SiC MOSFET device packaging structure, the fourth metal layer is electrically connected to the second power poles of multiple power chips by bonding wires.
所述的低感对称的SiC MOSFET器件封装结构中，第三金属层为负极母线。In the low-inductance symmetrical SiC MOSFET device packaging structure, the third metal layer is the negative busbar.
所述的低感对称的SiC MOSFET器件封装结构中，低感对称的SiCMOSFET器件封装结构还包括设于壳体内的NTC热敏电阻。In the low-inductance symmetrical SiC MOSFET device packaging structure, the low-inductance symmetrical SiC MOSFET device packaging structure also includes an NTC thermistor arranged in the shell.
所述的低感对称的SiC MOSFET器件封装结构中，多个功率芯片对称分布于所述第一覆铜陶瓷板上。In the low-inductance symmetrical SiC MOSFET device packaging structure, a plurality of power chips are symmetrically distributed on the first copper-clad ceramic board.
所述的低感对称的SiC MOSFET器件封装结构中，多个功率芯片、第一覆铜陶瓷板、第二覆铜陶瓷板、多个功率端子和多个信号端子均为两组以构成两个相同的模块。In the low-inductance symmetrical SiC MOSFET device packaging structure, the multiple power chips, the first copper-clad ceramic board, the second copper-clad ceramic board, the multiple power terminals and the multiple signal terminals are all in two groups to form two identical modules.
所述的低感对称的SiC MOSFET器件封装结构中，通过进线端子的连接，两个模块单独使用、并联使用或串联使用。In the low-inductance symmetrical SiC MOSFET device packaging structure, two modules are used individually, in parallel or in series through the connection of the incoming terminals.
低感对称的SiC MOSFET器件封装结构的封装方法包括以下步骤，The packaging method of the low-inductance symmetrical SiC MOSFET device packaging structure includes the following steps:
加工第一覆铜陶瓷板和第二覆铜陶瓷板，第一覆铜陶瓷板的第二金属层按设定间隙分为多个导电区域，第二覆铜陶瓷板加工为扇形；Processing a first copper-clad ceramic plate and a second copper-clad ceramic plate, wherein the second metal layer of the first copper-clad ceramic plate is divided into a plurality of conductive areas according to a set gap, and the second copper-clad ceramic plate is processed into a fan shape;
布置功率芯片和第二覆铜陶瓷板，第二覆铜陶瓷板设于第一覆铜陶瓷板上，所述第三金属层焊接第二金属层，通过银烧结或焊接工艺使多个功率芯片分布于所述第一覆铜陶瓷板上，所述第一功率极连接所述第二金属层，通过键合线键合实现第二功率极电气连接第四金属层，以及控制极和开尔文源极电气连接金属区域，The power chip and the second copper-clad ceramic board are arranged, the second copper-clad ceramic board is arranged on the first copper-clad ceramic board, the third metal layer is welded to the second metal layer, a plurality of power chips are distributed on the first copper-clad ceramic board by silver sintering or welding process, the first power electrode is connected to the second metal layer, the second power electrode is electrically connected to the fourth metal layer by bonding wire bonding, and the control electrode and the Kelvin source electrode are electrically connected to the metal area,
在第一覆铜陶瓷基板上焊接功率端子和信号端子，通过焊接工艺使第一覆铜陶瓷板第一金属层与散热铜基板连接，The power terminal and the signal terminal are welded on the first copper-clad ceramic substrate, and the first metal layer of the first copper-clad ceramic substrate is connected to the heat dissipation copper substrate through a welding process.
加装壳体，实现散热铜基板与壳体紧固连接。A shell is added to achieve a tight connection between the heat dissipation copper substrate and the shell.
和现有技术相比，本发明具有以下优点：Compared with the prior art, the present invention has the following advantages:
低感对称的SiC MOSFET器件封装结构优化功率芯片布局和采用多个覆铜陶瓷板构成多层导电路径，有利于降低封装的杂散电感和并联支路杂散差异，提高多碳化硅功率芯片并联的均流性能，降低关断过电压峰值。The low-inductance symmetrical SiC MOSFET device packaging structure optimizes the power chip layout and uses multiple copper-clad ceramic plates to form a multi-layer conductive path, which is beneficial to reducing the stray inductance of the package and the stray difference of the parallel branches, improving the current sharing performance of multiple silicon carbide power chips in parallel, and reducing the turn-off overvoltage peak.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
附图示出了本发明的示例性实施方式，并与其说明一起用于解释本发明的原理，其中包括了这些附图以提供对本发明的进一步理解，并且附图包括在本说明书中并构成本说明书的一部分。The accompanying drawings illustrate exemplary embodiments of the present invention and together with the description serve to explain the principles of the present invention. These drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification.
图1是本发明一个实施例中的低感对称的SiC MOSFET器件封装结构的结构示意图；FIG1 is a schematic structural diagram of a low-inductance symmetrical SiC MOSFET device packaging structure in one embodiment of the present invention;
图2是本发明一个实施例中的低感对称的SiC MOSFET器件封装结构的连接示意图；FIG2 is a schematic diagram of the connection of a low-inductance symmetrical SiC MOSFET device packaging structure in one embodiment of the present invention;
图3是本发明一个实施例中的低感对称的SiC MOSFET器件封装结构的截面示意图；FIG3 is a cross-sectional schematic diagram of a low-inductance symmetrical SiC MOSFET device packaging structure in one embodiment of the present invention;
图4是本发明一个实施例中的低感对称的SiC MOSFET器件封装结构的电路原理示意图。FIG. 4 is a schematic diagram of a circuit principle of a low-inductance symmetrical SiC MOSFET device packaging structure in one embodiment of the present invention.
具体实施方式DETAILED DESCRIPTION
下面结合附图和实施方式对本发明作进一步的详细说明。可以理解的是，此处所描述的具体实施方式仅用于解释相关内容，而非对本发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本发明相关的部分。The present invention will be further described in detail below in conjunction with the accompanying drawings and implementations. It is to be understood that the specific implementations described herein are only used to explain the relevant content, rather than to limit the present invention. It should also be noted that, for ease of description, only the parts related to the present invention are shown in the accompanying drawings.
需要说明的是，在不冲突的情况下，本发明中的实施方式及实施方式中的特征可以相互组合。下面将参考附图并结合实施方式来详细说明本发明的技术方案。It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
除非另有说明，否则示出的示例性实施方式/实施例将被理解为提供可以在实践中实施本发明的技术构思的一些方式的各种细节的示例性特征。因此，除非另有说明，否则在不脱离本发明的技术构思的情况下，各种实施方式/实施例的特征可以另外地组合、分离、互换和/或重新布置。Unless otherwise specified, the exemplary embodiments/embodiments shown will be understood as exemplary features that provide various details of some ways in which the technical concept of the present invention can be implemented in practice. Therefore, unless otherwise specified, the features of the various embodiments/embodiments can be combined, separated, interchanged and/or rearranged without departing from the technical concept of the present invention.
在附图中可能使用交叉影线和/或阴影通常用于使相邻部件之间的边界变得清晰。如此，除非说明，否则交叉影线或阴影的存在与否均不传达或表示对部件的具体材料、材料性质、尺寸、比例、示出的部件之间的共性和/或部件的任何其它特性、属性、性质等的任何偏好或者要求。此外，在附图中，为了清楚和/或描述性的目的，可以夸大部件的尺寸和相对尺寸。当可以不同地实施示例性实施例时，可以以不同于所描述的步骤顺序来执行具体的工艺顺序。例如，可以基本同时执行或者以与所描述的顺序相反的顺序执行两个连续描述的工艺。此外，同样的附图标记表示同样的部件。Cross-hatching and/or shading may be used in the drawings, typically to make the boundaries between adjacent components clear. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for the specific materials, material properties, dimensions, proportions, commonalities between the components shown, and/or any other characteristics, attributes, properties, etc. of the components. In addition, in the drawings, the sizes and relative sizes of the components may be exaggerated for clarity and/or descriptive purposes. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed in a different order than the described step sequence. For example, two successively described processes may be performed substantially simultaneously or in an order opposite to the described order. In addition, the same figure numbers represent the same components.
当一个部件被称作“在”另一部件“上”或“之上”、“连接到”或“结合到”另一部件时，该部件可以直接在所述另一部件上、直接连接到或直接结合到所述另一部件，或者可以存在中间部件。然而，当部件被称作“直接在”另一部件“上”、“直接连接到”或“直接结合到”另一部件时，不存在中间部件。为此，术语“连接”可以指物理连接、电气连接等，并且具有或不具有中间部件。When a component is referred to as being "on" or "over," "connected to," or "coupled to" another component, the component may be directly on, directly connected to, or directly coupled to the other component, or intervening components may be present. However, when a component is referred to as being "directly on," "directly connected to," or "directly coupled to" another component, there are no intervening components. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, etc., with or without intervening components.
为了描述性目的，本发明可使用诸如“在……之下”、“在……下方”、“在……下”、“下”、“在……上方”、“上”、“在……之上”、“较高的”和“侧(例如，如在“侧壁”中)”等的空间相对术语，从而来描述如附图中示出的一个部件与另一(其它)部件的关系。除了附图中描绘的方位之外，空间相对术语还意图包含设备在使用、操作和/或制造中的不同方位。例如，如果附图中的设备被翻转，则被描述为“在”其它部件或特征“下方”或“之下”的部件将随后被定位为“在”所述其它部件或特征“上方”。因此，示例性术语“在……下方”可以包含“上方”和“下方”两种方位。此外，设备可被另外定位(例如，旋转90度或者在其它方位处)，如此，相应地解释这里使用的空间相对描述语。For descriptive purposes, the present invention may use spatially relative terms such as "below", "beneath", "under", "lower", "above", "upper", "above", "higher", and "side (e.g., as in "sidewall")" to describe the relationship of one component to another (other) component as shown in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, components described as "below" or "beneath" other components or features would then be positioned "above" the other components or features. Thus, the exemplary term "below" can encompass both the "above" and "below" orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.
这里使用的术语是为了描述具体实施例的目的，而不意图是限制性的。如这里所使用的，除非上下文另外清楚地指出，否则单数形式“一个(种、者)”和“所述(该)”也意图包括复数形式。此外，当在本说明书中使用术语“包含”和/或“包括”以及它们的变型时，说明存在所陈述的特征、整体、步骤、操作、部件、组件和/或它们的组，但不排除存在或附加一个或更多个其它特征、整体、步骤、操作、部件、组件和/或它们的组。还要注意的是，如这里使用的，术语“基本上”、“大约”和其它类似的术语被用作近似术语而不用作程度术语，如此，它们被用来解释本领域普通技术人员将认识到的测量值、计算值和/或提供的值的固有偏差。The terms used here are for the purpose of describing specific embodiments, and are not intended to be restrictive. As used here, unless the context clearly indicates otherwise, the singular forms "one (kind, person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprise" and/or "include" and their variations are used in this specification, it is explained that there are stated features, integral bodies, steps, operations, parts, assemblies and/or their groups, but it is not excluded that there are or add one or more other features, integral bodies, steps, operations, parts, assemblies and/or their groups. It should also be noted that, as used here, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as degree terms, so that they are used to explain the inherent deviations of the measured values, calculated values and/or the values provided that will be recognized by those of ordinary skill in the art.
参见图1至图4，在一个实施例中，本发明所述的低感对称的SiC MOSFET器件封装结构包括：Referring to FIG. 1 to FIG. 4 , in one embodiment, the low-inductance symmetrical SiC MOSFET device packaging structure of the present invention includes:
壳体2，其内设有散热铜基板4，The housing 2 has a heat dissipation copper substrate 4 disposed therein.
第一覆铜陶瓷板6，其焊接于所述散热铜基板4上，所述第一覆铜陶瓷板6具有连接散热铜基板4的第一金属层和位于第一覆铜陶瓷板6上的第二金属层，所述第二金属层相对于所述第一金属层，The first copper-clad ceramic board 6 is welded on the heat dissipation copper substrate 4. The first copper-clad ceramic board 6 has a first metal layer connected to the heat dissipation copper substrate 4 and a second metal layer located on the first copper-clad ceramic board 6. The second metal layer is opposite to the first metal layer.
多个功率芯片5，其分布于所述第一覆铜陶瓷板6上，所述功率芯片5包括第一功率极和第二功率极，所述第一功率极连接所述第二金属层，A plurality of power chips 5 are distributed on the first copper-clad ceramic board 6. The power chip 5 includes a first power electrode and a second power electrode. The first power electrode is connected to the second metal layer.
第二覆铜陶瓷板7，其设于第一覆铜陶瓷板6上，所述第二覆铜陶瓷板7具有连接第二金属层的第三金属层和位于第二覆铜陶瓷板7上的第四金属层，相对于所述第三金属层的所述第四金属层电气连接所述第二功率极，The second copper-clad ceramic board 7 is provided on the first copper-clad ceramic board 6. The second copper-clad ceramic board 7 has a third metal layer connected to the second metal layer and a fourth metal layer located on the second copper-clad ceramic board 7. The fourth metal layer relative to the third metal layer is electrically connected to the second power pole.
多个功率端子1，功率端子1包括设于第一覆铜陶瓷板6上的出线功率端子1和设于第二覆铜陶瓷板7上的进线端子，A plurality of power terminals 1, the power terminals 1 comprising an outgoing power terminal 1 arranged on the first copper-clad ceramic board 6 and an incoming power terminal arranged on the second copper-clad ceramic board 7,
多个信号端子3，其设于第一覆铜陶瓷板6上。A plurality of signal terminals 3 are disposed on the first copper-clad ceramic board 6 .
所述的低感对称的SiC MOSFET器件封装结构的优选实施例中，功率芯片5在第一覆铜陶瓷板6上关于所述进线端子呈扇形分布。In a preferred embodiment of the low-inductance symmetrical SiC MOSFET device packaging structure, the power chips 5 are distributed on the first copper-clad ceramic board 6 in a fan-shaped manner with respect to the incoming terminal.
所述的低感对称的SiC MOSFET器件封装结构的优选实施例中，第一金属层设置分别对应每个功率芯片5的开尔文源极金属区域。In a preferred embodiment of the low-inductance symmetrical SiC MOSFET device packaging structure, the first metal layer is arranged to correspond to the Kelvin source metal region of each power chip 5 .
所述的低感对称的SiC MOSFET器件封装结构的优选实施例中，第四金属层通过键合线8键合的方式与多个功率芯片5的第二功率极实现电气连接。In the preferred embodiment of the low-inductance symmetrical SiC MOSFET device packaging structure, the fourth metal layer is electrically connected to the second power poles of the plurality of power chips 5 by bonding with bonding wires 8 .
所述的低感对称的SiC MOSFET器件封装结构的优选实施例中，第三金属层为负极母线。In a preferred embodiment of the low-inductance symmetrical SiC MOSFET device packaging structure, the third metal layer is a negative busbar.
所述的低感对称的SiC MOSFET器件封装结构的优选实施例中，低感对称的SiCMOSFET器件封装结构还包括设于壳体2内的NTC热敏电阻。In a preferred embodiment of the low-inductance symmetrical SiC MOSFET device packaging structure, the low-inductance symmetrical SiC MOSFET device packaging structure further includes an NTC thermistor disposed in the housing 2 .
所述的低感对称的SiC MOSFET器件封装结构的优选实施例中，多个功率芯片5对称分布于所述第一覆铜陶瓷板6上。In a preferred embodiment of the low-inductance symmetrical SiC MOSFET device packaging structure, a plurality of power chips 5 are symmetrically distributed on the first copper-clad ceramic board 6 .
所述的低感对称的SiC MOSFET器件封装结构的优选实施例中，多个功率芯片5、第一覆铜陶瓷板6、第二覆铜陶瓷板7、多个功率端子1和多个信号端子3均为两组以构成两个相同的模块。In a preferred embodiment of the low-inductance symmetrical SiC MOSFET device packaging structure, the multiple power chips 5, the first copper-clad ceramic board 6, the second copper-clad ceramic board 7, the multiple power terminals 1 and the multiple signal terminals 3 are all in two groups to form two identical modules.
所述的低感对称的SiC MOSFET器件封装结构的优选实施例中，通过进线端子的连接，两个模块单独使用、并联使用或串联使用。In a preferred embodiment of the low-inductance symmetrical SiC MOSFET device packaging structure, two modules are used individually, in parallel or in series through the connection of the incoming terminals.
在一个实施例中，第一接入端配置成低感对称的SiC MOSFET器件封装结构的进线功率端子1，第二接入端配置成低感对称的SiC MOSFET器件封装结构的出线功率端子1。所述第一覆铜陶瓷板6的第一金属层设置有开尔文源极金属区域，分别对应每个功率芯片5，并采用键合线键合的方式与对应功率芯片5的第二功率极接触面实现电气连接。所述第二覆铜陶瓷板7的第三金属层作为负极母线，其通过键合线键合实现与多功率芯片5第二功率极接触面的电气连接。所述出线功率端子1设置于第二覆铜陶瓷板7的第三金属层上，并采用焊接的方式实现电气连接，所述多个功率芯片5、多个覆铜陶瓷板、多个功率端子1、多个信号端子3均为两组。每组均按照前述的相同方式布置，组成两个相同的模块。In one embodiment, the first access end is configured as an incoming power terminal 1 of a low-inductance symmetrical SiC MOSFET device package structure, and the second access end is configured as an outgoing power terminal 1 of a low-inductance symmetrical SiC MOSFET device package structure. The first metal layer of the first copper-clad ceramic plate 6 is provided with a Kelvin source metal region, which corresponds to each power chip 5 respectively, and is electrically connected to the second power pole contact surface of the corresponding power chip 5 by means of bonding wire bonding. The third metal layer of the second copper-clad ceramic plate 7 is used as a negative busbar, which is electrically connected to the second power pole contact surface of the multi-power chip 5 by bonding wire bonding. The outgoing power terminal 1 is arranged on the third metal layer of the second copper-clad ceramic plate 7, and is electrically connected by welding. The multiple power chips 5, multiple copper-clad ceramic plates, multiple power terminals 1, and multiple signal terminals 3 are all in two groups. Each group is arranged in the same manner as described above to form two identical modules.
所述的低感对称的SiC MOSFET器件封装结构的封装方法包括以下步骤，The packaging method of the low-inductance symmetrical SiC MOSFET device packaging structure comprises the following steps:
加工第一覆铜陶瓷板6和第二覆铜陶瓷板7，第一覆铜陶瓷板6的第二金属层按设定间隙分为多个导电区域，第二覆铜陶瓷板7加工为扇形；Processing a first copper-clad ceramic plate 6 and a second copper-clad ceramic plate 7, wherein the second metal layer of the first copper-clad ceramic plate 6 is divided into a plurality of conductive areas according to a set gap, and the second copper-clad ceramic plate 7 is processed into a fan shape;
布置功率芯片5和第二覆铜陶瓷板7，第二覆铜陶瓷板7设于第一覆铜陶瓷板6上，所述第三金属层焊接第二金属层，通过银烧结或焊接工艺使多个功率芯片5分布于所述第一覆铜陶瓷板6上，所述第一功率极连接所述第二金属层，通过键合线键合实现第二功率极电气连接第四金属层，以及控制极和开尔文源极电气连接金属区域，The power chip 5 and the second copper-clad ceramic board 7 are arranged, the second copper-clad ceramic board 7 is arranged on the first copper-clad ceramic board 6, the third metal layer is welded to the second metal layer, and multiple power chips 5 are distributed on the first copper-clad ceramic board 6 through silver sintering or welding process, the first power electrode is connected to the second metal layer, the second power electrode is electrically connected to the fourth metal layer through bonding wire bonding, and the control electrode and the Kelvin source are electrically connected to the metal area,
在第一覆铜陶瓷基板上焊接功率端子1和信号端子3，通过焊接工艺使第一覆铜陶瓷板6第一金属层与散热铜基板4连接，加装壳体2，实现基板与壳体2紧固连接。The power terminal 1 and the signal terminal 3 are welded on the first copper-clad ceramic substrate, the first metal layer of the first copper-clad ceramic board 6 is connected to the heat dissipation copper substrate 4 through welding process, and the shell 2 is installed to achieve a tight connection between the substrate and the shell 2.
在一个实施例中，低感对称的SiC MOSFET器件封装结构为低感对称的封装结构，低感对称的SiC MOSFET器件封装结构包括壳体2，壳体2内设有散热铜基板4，与壳体通过螺纹紧固件连接。第一覆铜陶瓷板6分为两组，设于散热铜基板4上，与散热铜基板4采用焊接的方式连接。多个功率芯片5分为两组，设于第一覆铜陶瓷板上，按扇形布局分布；其第一功率极与第一覆铜陶瓷板6的第二金属层采用焊接的方式连接。第二覆铜陶瓷板7设于第一覆铜陶瓷板6上，其第三金属层与第一覆铜陶瓷板6的第二金属层焊接；其第四金属层通过键合线8键合的方式与多个功率芯片的第二功率极实现电气连接。In one embodiment, a low-inductance symmetrical SiC MOSFET device packaging structure is a low-inductance symmetrical packaging structure, and the low-inductance symmetrical SiC MOSFET device packaging structure includes a housing 2, a heat dissipation copper substrate 4 is provided in the housing 2, and the housing is connected to the housing by a threaded fastener. The first copper-clad ceramic plate 6 is divided into two groups, which are arranged on the heat dissipation copper substrate 4 and connected to the heat dissipation copper substrate 4 by welding. A plurality of power chips 5 are divided into two groups, which are arranged on the first copper-clad ceramic plate and distributed in a fan-shaped layout; the first power pole thereof is connected to the second metal layer of the first copper-clad ceramic plate 6 by welding. The second copper-clad ceramic plate 7 is arranged on the first copper-clad ceramic plate 6, and the third metal layer thereof is welded to the second metal layer of the first copper-clad ceramic plate 6; the fourth metal layer thereof is electrically connected to the second power poles of the plurality of power chips by bonding with bonding wires 8.
多个功率端子1分为两组，出线功率端子设于第一覆铜陶瓷板6上，进线端子设于第二覆铜陶瓷板7上，采用焊接的方式连接。多个信号端子3设于第一覆铜陶瓷板6上，采用焊接的方式连接。The multiple power terminals 1 are divided into two groups, the outgoing power terminals are arranged on the first copper-clad ceramic board 6, and the incoming terminals are arranged on the second copper-clad ceramic board 7, and are connected by welding. The multiple signal terminals 3 are arranged on the first copper-clad ceramic board 6, and are connected by welding.
在一个优选实施方式中，封装方法包括以下步骤：In a preferred embodiment, the packaging method comprises the following steps:
加工覆铜陶瓷板，第一覆铜陶瓷板6的第二导电层按设定间隙分为多个导电区域。第二覆铜陶瓷板7加工为扇形。The copper-clad ceramic plate is processed, and the second conductive layer of the first copper-clad ceramic plate 6 is divided into a plurality of conductive areas according to a set gap. The second copper-clad ceramic plate 7 is processed into a fan shape.
布置功率芯片和第二覆铜陶瓷板。按图2所式布局方式布置多个功率芯片5和第二覆铜陶瓷板7。Arrange the power chip and the second copper-clad ceramic board. Arrange a plurality of power chips 5 and the second copper-clad ceramic board 7 in the layout shown in FIG.
焊接芯片。通过银烧结或焊接等工艺使多功率芯片与第一覆铜陶瓷板实现可靠电气连接。Welding the chip. Through silver sintering or welding, the multi-power chip is reliably electrically connected to the first copper-clad ceramic board.
键合线连接。通过键合线键合，实现多个功率芯片第二功率极与第二覆铜陶瓷板的第四金属层电气连接以及控制极和开尔文源极与对应的金属区域电气连接。Bonding wire connection: Through bonding wire bonding, the second power electrodes of multiple power chips are electrically connected to the fourth metal layer of the second copper-clad ceramic board, and the control electrode and Kelvin source electrode are electrically connected to the corresponding metal area.
焊接功率端子。在第一覆铜陶瓷基板6上布置功率端子和信号端子，采用焊接方式连接功率端子。Welding the power terminals: The power terminals and the signal terminals are arranged on the first copper-clad ceramic substrate 6, and the power terminals are connected by welding.
连接散热铜基板。通过焊接工艺使第一覆铜陶瓷板第二金属层与散热铜基板可靠连接。Connect the heat dissipation copper substrate. The second metal layer of the first copper-clad ceramic board is reliably connected to the heat dissipation copper substrate through a welding process.
加装壳体。加装壳体，实现基板与壳体紧固连接。Install the shell. Install the shell to achieve a tight connection between the base plate and the shell.
在本说明书的描述中，参考术语“一个实施例/方式”、“一些实施例/方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例/方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例/方式或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例/方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例/方式或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例/方式或示例以及不同实施例/方式或示例的特征进行结合和组合。In the description of this specification, the description with reference to the terms "one embodiment/method", "some embodiments/methods", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment/method or example are included in at least one embodiment/method or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment/method or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments/methods or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments/methods or examples described in this specification and the features of the different embodiments/methods or examples, unless they are contradictory.
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
本领域的技术人员应当理解，上述实施方式仅仅是为了清楚地说明本发明，而并非是对本发明的范围进行限定。对于所属领域的技术人员而言，在上述公开的基础上还可以做出其它变化或变型，并且这些变化或变型仍处于本发明的范围内。It should be understood by those skilled in the art that the above embodiments are only for the purpose of clearly illustrating the present invention, and are not intended to limit the scope of the present invention. For those skilled in the art, other changes or modifications may be made based on the above disclosure, and these changes or modifications are still within the scope of the present invention.
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