CN118539902A - True single-phase clock master-slave type all-static D trigger - Google Patents
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Abstract
The invention discloses a true single-phase clock master-slave type all-static D trigger, which comprises a data input circuit, a master trigger circuit, a slave trigger circuit and a data output circuit which are sequentially connected; the data input circuit is used for receiving a data input signal; the master trigger circuit and the slave trigger circuit are controlled by a clock signal CK; when the clock signal CK is in a low level, the master trigger circuit receives a data input signal, and the slave trigger circuit is in a maintenance state; when the clock signal CK is at a high level, the master flip-flop is in a hold state, and the slave flip-flop receives the memory state of the master flip-flop. The invention has the advantages of small transistor quantity, small clock control transistor quantity, simple circuit structure and the like, overcomes the defect that the storage state of the traditional true single-phase clock D trigger is changed due to electric leakage, and reduces the delay by 7-12% compared with the traditional D trigger; in addition, the input of the differential pattern may enhance the anti-noise performance.
Description
Technical Field
The invention mainly relates to the technical field of digital circuit design, in particular to a true single-phase clock master-slave type all-static D trigger.
Background
Since the advent of CMOS integrated circuit technology, flip-flops have been one of the core components of digital integrated circuits, being the basic unit for implementing sequential logic such as pipelines, state machines, counters, register files, etc., whose speed directly affects digital circuit and chip performance. The digital circuit has various flip-flops, and RS flip-flops, JK flip-flops, D flip-flops and T flip-flops are common. According to the different trigger circuit structures, the trigger circuit is divided into a master-slave type trigger, a sense amplifier type trigger, a hold-up type trigger and the like. Among them, master-slave D flip-flops are the most adaptable and most widely used in digital integrated circuit technology.
Fig. 1 is a schematic diagram of a D flip-flop circuit unit. Fig. 2 shows a basic circuit structure of a conventional D flip-flop circuit unit widely used in the design of a standard cell library of commercial digital circuits under each process node, which is commonly called Conventional transmission-gate flip-flop (TGFF), and this structure has the advantage of simple structure and the disadvantage of requiring complementary clock signals. The concept of true single phase clocks was invented and applied in flip-flop designs at the end of the 80 th century, which overcomes the disadvantage of the complementary clock signal required for conventional D flip-flops based on transmission gates or C2MOS logic. This flip-flop or its variant has been used in the design implementation of Alpha 21064 (92 years old) microprocessors, which has been 10% faster than the conventional D flip-flop/latch scheme according to Bowhill et al.
Mohamed Elgamel et al systematically illustrate the design principle of a conventional True single-phase clock D flip-flop (see document M. Elgamel, T. Darwish, and M. Bayoumi, "Noise Tolerant Low Power Dynamic TSPCL D Flip-Flops", in Proceeding of the IEEE Computer Society Annual Symposium on VLSI, pp. 89-94, 2002. doi: 10.1109/ISVLSI.2002.1016880.）,, fig. 3, which shows the practical structure of the conventional True single-phase clock D flip-flop (see patent US20080106315A1 of Ting-Sheng Jau et al), referred to as True SINGLE PHASE clock basic flip-flop (tscbff), which is advantageous in area and performance over TCFF.
Disclosure of Invention
Aiming at the technical problems existing in the prior art, the invention provides a true single-phase clock master-slave type all-static D trigger with all-static state, low clock power consumption and good delay characteristic.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
a true single-phase clock master-slave type all-static D trigger comprises a data input circuit, a master trigger circuit, a slave trigger circuit and a data output circuit; the data input circuit, the master trigger circuit, the slave trigger circuit and the data output circuit are connected in sequence;
A data input circuit for receiving a data input signal; a data output circuit for outputting an output signal from the trigger circuit;
The master trigger circuit and the slave trigger circuit are controlled by a clock signal CK;
when the clock signal CK is in a low level, the master trigger circuit receives a data input signal, and the slave trigger circuit is in a maintenance state;
When the clock signal CK is at a high level, the main trigger circuit is in a maintenance state, and the slave trigger circuit receives a storage state of the main trigger circuit;
The main trigger circuit comprises PMOS transistors MP1-MP5 and NMOS transistors MN6-MN7;
the PMOS tube MP1 substrate and the source electrode are connected with a power supply VDD, and the grid electrode is connected with a clock signal CK;
the PMOS tube MP2 substrate is connected with a power supply VDD, the grid electrode is connected with a signal dn, the source electrode is connected with the drain electrode of MP1, and the drain electrode drives a signal ml_b;
the PMOS tube MP3 substrate is connected with a power supply VDD, the grid electrode is connected with a signal dnn, the source electrode is connected with the drain electrode of MP1 and the source electrode of MP2, and the drain electrode drives a signal ml_ax;
the PMOS tube MP4 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal ml_ax, and the drain electrode is driven by a signal ml_b;
the PMOS tube MP5 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal ml_b, and the drain electrode is driven by a signal ml_ax;
NMOS transistor MN6 substrate and source electrode are grounded VSS, the grid electrode is driven by signal ml_ax, and the drain electrode is driven by signal ml_b;
NMOS transistor MN7 has substrate and source grounded VSS, gate driven by signal ml_b, drain driven signal ml_ax;
Wherein signal ml_ax and signal ml_b are complementary signal pairs in the primary trigger circuit; the signal dn and signal dnn are complementary or differential signal pairs generated by the data input circuit.
Preferably, the slave trigger circuit comprises NMOS transistors MN1-MN5 and PMOS transistors MP6-MP7;
NMOS transistor MN1 substrate and source ground VSS, the grid electrode is connected with a clock signal CK;
the substrate of the NMOS tube MN2 is grounded to VSS, the grid electrode is connected with a signal ml_ax, the source electrode is connected with the drain electrode of the MN1, and the drain electrode drives the signal sl_a;
the substrate of the NMOS tube MN3 is grounded, the grid electrode is connected with a signal ml_b, the source electrode is connected with the drain electrode of the MN1 and the source electrode of the NM2, and the drain electrode drives the signal sl_bx;
The substrate and the source electrode of the NMOS tube MN4 are grounded and the grid electrode is driven by a signal sl_bx, and the drain electrode drives a signal sl_a;
The substrate and the source electrode of the NMOS tube MN5 are grounded and the grid electrode is driven by a signal sl_a, and the drain electrode is driven by a signal sl_bx;
the PMOS tube MP6 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal sl_bx, and the drain electrode is driven by a signal sl_a;
the PMOS tube MP7 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal sl_a, and the drain electrode is driven by a signal sl_bx;
Where the signal sl_bx and the signal sl_a are complementary signal pairs in the slave flip-flop.
Preferably, the data output circuit includes an inverter X3, an input terminal of the inverter X3 is driven by a signal sl_bx, and an output terminal of the inverter X3 drives an output signal Q.
Preferably, the data input circuit includes an inverter X1 and an inverter X2 for receiving the data input signal D and generating complementary or differential signal pairs dn and dnn;
The input end of the inverter X1 is connected with the data input signal D, and the output signal of the inverter X1 is dn; the input of the inverter X2 is connected with the signal dn, and the output signal of the inverter X2 is dnn.
Preferably, the data input circuit comprises inverters X2 and X4, PMOS transistors MP 11-MP 14 and NMOS transistors MN11-MN14;
the inverter X4 is used for generating a complementary signal sen of the enable signal SE;
Inverter X2 is used to generate a complementary signal dnn to signal dn;
The PMOS tube MP11 substrate and the source electrode are connected with a power supply VDD, and the grid electrode is controlled by an enable signal SE;
The substrate and the source electrode of the PMOS tube MP12 are connected with a power supply VDD, and the grid electrode is controlled by a scanning signal SI;
The PMOS tube MP13 substrate is connected with a power supply VDD, the source electrode is connected with the drain electrode of MP11, and the grid electrode is controlled by a data input signal D; and a drain driving signal dn;
The substrate of the PMOS tube MP14 is connected with a power supply VDD, the source electrode of the PMOS tube MP14 is connected with the drain electrode of the MP12, the gate is controlled by the signal sen, the drain driving signal dn;
The substrate and the source of the NMOS transistor MN11 are connected with a power supply VSS, and the grid is controlled by a complementary signal sen of an enable signal SE;
the substrate and the source of the NMOS tube MN12 are connected with a power supply VSS, and the grid is controlled by a scanning signal SI;
The substrate of NMOS transistor MN13 is connected with power source VSS, its source is connected with drain electrode of MN11, the grid is controlled by a data input signal D, and the drain electrode drives a signal dn;
The NMOS transistor MN14 has a substrate connected to a power source VSS, a source connected to the drain of MN12, a gate controlled by an enable signal SE, and a drain driving signal dn.
Preferably, the data input circuit includes an inverter X1, an input terminal of the inverter X1 is connected to the data input signal D, and an output signal of the inverter X1 is dn; the data input signal D is provided as signal dnn.
Compared with the prior art, the invention has the advantages that:
Compared with the traditional true single-phase clock D trigger TSPCBFF, the true single-phase clock master-slave type full-static D trigger overcomes the defect that the dynamic trigger cannot maintain a storage state for a long time, and when the clock is in a low level for a long time, the slave trigger circuit is in a maintenance state, and the states of signals sl_a and sl_bx cannot be changed due to electric leakage, so that the Q value can be maintained for a long time; the method is more suitable for digital integrated circuit design, and can be applied to chip designs such as CPU, GPU, ASIC and the like.
Compared with the traditional D trigger TGFF, the true single-phase clock master-slave type all-static D trigger greatly reduces clock load, reduces the number of clock signal driving transistors and can save dynamic power consumption; the number of the transistors is smaller, so that the area can be saved; only two-stage reverse logic is needed to conduct the input change to the output Q at the rising edge moment of the clock, and the circuit delay characteristic is good; meanwhile, the differential input is adopted, so that the anti-noise performance is better, and the digital integrated circuit is more suitable for digital integrated circuit design.
Drawings
FIG. 1 is a circuit diagram of a conventional flip-flop; d is a data input signal, CK is a clock signal, and Q is an output signal.
Fig. 2 is a circuit configuration diagram of a conventional D flip-flop TGFF.
Fig. 3 is a circuit configuration diagram of a conventional true single-phase clock D flip-flop TSPCBFF.
Fig. 4 is a circuit configuration diagram of a true single-phase clock master-slave type all-static flip-flop according to a first embodiment of the present invention.
Fig. 5 is a circuit configuration diagram of a true single-phase clock master-slave type all-static flip-flop with a scanning structure in a second embodiment of the present invention.
Fig. 6 is a circuit configuration diagram of a master-slave type all-static flip-flop with a simplified true single-phase clock in a third embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the drawings and specific examples.
Embodiment one:
As shown in fig. 1, the true single-phase clock master-slave type all-static D flip-flop of the embodiment of the present invention includes a data input circuit, a master flip-flop circuit, a slave flip-flop circuit, and a data output circuit, where the master flip-flop circuit and the slave flip-flop circuit are controlled by a clock signal CK;
when the clock signal CK is at a low level, the master trigger circuit receives a data input, and the slave trigger circuit is in a maintenance state;
when the clock signal CK is at a high level, the master trigger circuit is in a sustain state without being affected by the input signal, and the slave trigger circuit receives the memory state of the master trigger circuit so that the flip-flop state is updated.
Specifically, the data input circuit includes an inverter X1 and an inverter X2 for receiving the data input signal D and producing complementary or differential signal pairs dn and dnn;
The input end of the inverter X1 is connected with the data input signal D, and the output signal of the inverter X1 is dn; the input of the inverter X2 is connected with the signal dn, and the output signal of the inverter X2 is dnn.
Specifically, the main trigger circuit comprises PMOS transistors MP1-MP5 and NMOS transistors MN6-MN7;
the PMOS tube MP1 substrate and the source electrode are connected with a power supply VDD, and the grid electrode is connected with a clock signal CK;
the PMOS tube MP2 substrate is connected with a power supply VDD, the grid electrode is connected with a signal dn, the source electrode is connected with the drain electrode of MP1, and the drain electrode drives a signal ml_b;
the PMOS tube MP3 substrate is connected with a power supply VDD, the grid electrode is connected with a signal dnn, the source electrode is connected with the drain electrode of MP1 and the source electrode of MP2, and the drain electrode drives a signal ml_ax;
the PMOS tube MP4 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal ml_ax, and the drain electrode is driven by a signal ml_b;
the PMOS tube MP5 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal ml_b, and the drain electrode is driven by a signal ml_ax;
NMOS transistor MN6 substrate and source electrode are grounded VSS, the grid electrode is driven by signal ml_ax, and the drain electrode is driven by signal ml_b;
NMOS transistor MN7 has substrate and source grounded VSS, gate driven by signal ml_b, drain driven signal ml_ax;
Wherein signal ml_ax and signal ml_b are complementary signal pairs in the primary trigger circuit;
specifically, the slave trigger circuit comprises NMOS transistors MN1-MN5 and PMOS transistors MP6-MP7;
NMOS transistor MN1 substrate and source ground VSS, the grid electrode is connected with a clock signal CK;
the substrate of the NMOS tube MN2 is grounded to VSS, the grid electrode is connected with a signal ml_ax, the source electrode is connected with the drain electrode of the MN1, and the drain electrode drives the signal sl_a;
the substrate of the NMOS tube MN3 is grounded, the grid electrode is connected with a signal ml_b, the source electrode is connected with the drain electrode of the MN1 and the source electrode of the NM2, and the drain electrode drives the signal sl_bx;
The substrate and the source electrode of the NMOS tube MN4 are grounded and the grid electrode is driven by a signal sl_bx, and the drain electrode drives a signal sl_a;
The substrate and the source electrode of the NMOS tube MN5 are grounded and the grid electrode is driven by a signal sl_a, and the drain electrode is driven by a signal sl_bx;
the PMOS tube MP6 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal sl_bx, and the drain electrode is driven by a signal sl_a;
The PMOS tube MP7 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal sl_a, and the drain electrode is driven by a signal sl_bx.
The data output circuit comprises an inverter X3, wherein the input end of the inverter X3 is driven by a signal sl_bx, and the output end of the inverter X3 is driven to output a signal Q.
When the true single-phase clock master-slave type all-static D trigger is applied specifically, the specific working principle is as follows:
When the clock signal CK is low, MP1 is turned on and MN1 is turned off; at this time, the slave flip-flop is in a hold state, and the inverter X3 is stably driven to hold the Q value of the output signal; at the same time the master trigger circuit is in the accept data state. When the data input signal D is at a high level, the dn and dnn signals are at a low level and a high level, respectively, so that MP2 is turned on and MP3 is turned off, the signal ml_b is pulled up to a high level by the MP2 pipe, and the pull-up of the signal ml_b causes MN7 to be turned on, pulling down the signal ml_ax to a low level. Conversely, when the data input signal D is low, the signal dn and the signal dnn are high and low, respectively, so that MP2 is turned off and MP3 is turned on, the signal ml_ax is pulled up to high by the MP3 pipe, and the pull-up of the signal ml_ax causes MN6 to be turned on, and the signal ml_b is pulled down to low;
When the clock signal CK is at a high level, MP1 is turned off and MN1 is turned on; at this time, the main trigger circuit is in a maintenance state, so that ml_b and ml_ax signals are kept stable; while the slave flip-flop circuit is in the accept data state. If the ml_b signal is at high level, MN3 is turned on and MN2 is turned off, the signal sl_bx is pulled down to low level, and the pull-down of the signal sl_bx further causes MP6 to be turned on, so that the signal sl_a is pulled up to high level; if the signal ml_b is at low level, the MN3 is turned off and the MN2 is turned on, the signal sl_a is pulled down to low level, the pull-down of the signal sl_a further enables the MP7 to be turned on, and the signal sl_bx is pulled up to high level; the update of the signal sl_bx drives the inverter X3 so that the output signal Q value is updated.
In the period in which the clock signal CK is at the high level, since the main flip-flop circuit is in the sustain state, the signals ml_b and ml_ax remain stable without being affected by the data input signal D, and thus the state update from the flip-flop circuit occurs at the timing when the clock signal CK transitions from the low level to the high level, i.e., the flip-flop of the present invention is a rising edge triggered D flip-flop.
Compared with the traditional True single-phase clock D trigger TSPCBFF, the True single-phase clock master-slave type full-static D trigger (True single-phase clock master-SLAVE FLIP-flop, abbreviated as TSPCMSFF) overcomes the defect that a dynamic trigger cannot maintain a storage state for a long time, and when a clock is in a low level for a long time, a slave trigger circuit is in a maintenance state, and the states of signals sl_a and sl_bx cannot be changed due to electric leakage, so that the Q value can be maintained for a long time; the more digital integrated circuit design can be applied to chip designs such as CPU, GPU, ASIC.
Compared with the traditional D trigger TGFF, the true single-phase clock master-slave type all-static D Trigger (TSPCMSFF) of the invention greatly reduces clock load, reduces the number of clock signal driving transistors (from 12 in FIG. 2 to 2 in FIG. 4), and can save dynamic power consumption; the number of the transistors is smaller, so that the area can be saved; only two-stage reverse logic is needed to conduct the input change to the output Q at the rising edge moment of the clock, and the circuit delay characteristic is good; meanwhile, the differential input is adopted, so that the anti-noise performance is better, and the digital integrated circuit is more suitable for digital integrated circuit design.
The invention has the characteristics of complete static state, low clock power consumption and good delay characteristic.
Embodiment two:
The D flip-flop in the first embodiment is easily expanded to a true single-phase clock master-slave type all-static D flip-flop with a scanning structure, thereby supporting widely-required testability design in digital integrated circuit design. As shown in fig. 5, the circuit structure of the true single-phase clock master-slave type all-static D flip-flop with the scan structure is changed only in the data input circuit as compared with the flip-flop in the first embodiment. Specifically, the data input circuit comprises inverters X2 and X4, PMOS transistors MP 11-MP 14 and NMOS transistors MN11-MN14;
the inverter X4 is used for generating a complementary signal sen of the enable signal SE;
Inverter X2 is used to generate a complementary signal dnn to signal dn;
The PMOS tube MP11 substrate and the source electrode are connected with a power supply VDD, and the grid electrode is controlled by an enable signal SE;
The substrate and the source electrode of the PMOS tube MP12 are connected with a power supply VDD, and the grid electrode is controlled by a scanning signal SI;
The PMOS tube MP13 substrate is connected with the power supply VDD, the source electrode is connected with the drain electrode of MP11, the grid is controlled by a data input signal D; and a drain driving signal dn;
The substrate of the PMOS tube MP14 is connected with a power supply VDD, the source electrode of the PMOS tube MP14 is connected with the drain electrode of the MP12, the gate is controlled by the signal sen, the drain driving signal dn;
The substrate and the source of the NMOS transistor MN11 are connected with a power supply VSS, and the grid is controlled by a complementary signal sen of an enable signal SE;
the substrate and the source of the NMOS tube MN12 are connected with a power supply VSS, and the grid is controlled by a scanning signal SI;
The substrate of NMOS transistor MN13 is connected with power source VSS, its source is connected with drain electrode of MN11, the grid is controlled by a data input signal D, and the drain electrode drives a signal dn;
The NMOS transistor MN14 has a substrate connected to a power source VSS, a source connected to the drain of MN12, a gate controlled by an enable signal SE, and a drain driving signal dn.
Other matters not described are the same as those of the first embodiment, and are not described herein.
Embodiment III:
In an application scenario where the scan architecture or design for testability is not required, the D flip-flop in the first embodiment can be further simplified, i.e., the inverter X2 is eliminated, the inverter X1 is reserved, and the gate of MP3 that is originally driven by the signal dnn is directly driven by the data input signal D. The simplified circuit configuration is shown in fig. 6, in which only the data input circuit is changed.
Other matters not described are the same as those of the first embodiment, and are not described herein.
Finally, to compare performance characteristics of TSPCMSFF of the present invention, under a certain commercial FinFET bulk silicon process, SPICE simulation analysis and comparison are performed on the conventional D flip-flop TGFF, the conventional TSPC D flip-flop TSPCBFF, and TSPCMSFF of the first embodiment of the present invention based on the circuit simulation tool hspin, and analysis and comparison results are shown in table 1:
TABLE 1 transistor count comparison and CK2Q delay simulation result comparison
As can be seen from the comparison of the parameters related to the flip-flop in table 1, compared with the conventional D flip-flop, the number of the flip-flop transistors in the present invention is reduced by 16.7%, and the number of the clocked transistors is reduced by 83.3%, which is the design style with the least number of the clocked transistors in the current flip-flop design.
In the circuit simulation, a clock signal CK is a quasi-square wave signal with the frequency of 1GHz, the duty ratio of 50% and the rising/falling jump time of 20 ps; the data input D is a quasi-square wave signal with 500MHz, the duty ratio is 50% and the rising/falling jump time is 50 ps; the output end of the trigger circuit is provided with 1 capacitor of 10fF as a load.
Under comparable circumstances, the CK2Q delay of the flip-flop TSPCMSFF of the present invention is reduced by 7% -12% compared to the conventional D flip-flop TGFF. Therefore, compared with the traditional D flip-flop, the true single-phase clock master-slave type all-static D flip-flop has smaller area, lower clock power consumption and smaller CK2Q delay, is more suitable for the design of a standard cell library, and has wide prospects in the design of digital integrated circuits and the design of chips.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.
Claims (6)
1. The true single-phase clock master-slave type all-static D trigger is characterized by comprising a data input circuit, a master trigger circuit, a slave trigger circuit and a data output circuit; the data input circuit, the master trigger circuit, the slave trigger circuit and the data output circuit are connected in sequence;
A data input circuit for receiving a data input signal; a data output circuit for outputting an output signal from the trigger circuit;
The master trigger circuit and the slave trigger circuit are controlled by a clock signal CK;
when the clock signal CK is in a low level, the master trigger circuit receives a data input signal, and the slave trigger circuit is in a maintenance state;
When the clock signal CK is at a high level, the main trigger circuit is in a maintenance state, and the slave trigger circuit receives a storage state of the main trigger circuit;
The main trigger circuit comprises PMOS transistors MP1-MP5 and NMOS transistors MN6-MN7;
the PMOS tube MP1 substrate and the source electrode are connected with a power supply VDD, and the grid electrode is connected with a clock signal CK;
the PMOS tube MP2 substrate is connected with a power supply VDD, the grid electrode is connected with a signal dn, the source electrode is connected with the drain electrode of MP1, and the drain electrode drives a signal ml_b;
the PMOS tube MP3 substrate is connected with a power supply VDD, the grid electrode is connected with a signal dnn, the source electrode is connected with the drain electrode of MP1 and the source electrode of MP2, and the drain electrode drives a signal ml_ax;
the PMOS tube MP4 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal ml_ax, and the drain electrode is driven by a signal ml_b;
the PMOS tube MP5 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal ml_b, and the drain electrode is driven by a signal ml_ax;
NMOS transistor MN6 substrate and source electrode are grounded VSS, the grid electrode is driven by signal ml_ax, and the drain electrode is driven by signal ml_b;
NMOS transistor MN7 has substrate and source grounded VSS, gate driven by signal ml_b, drain driven signal ml_ax;
Wherein signal ml_ax and signal ml_b are complementary signal pairs in the primary trigger circuit; the signal dn and signal dnn are complementary or differential signal pairs generated by the data input circuit.
2. The true single-phase clock master-slave type all-static D trigger according to claim 1, wherein the slave trigger circuit comprises NMOS transistors MN1-MN5 and PMOS transistors MP6-MP7;
NMOS transistor MN1 substrate and source ground VSS, the grid electrode is connected with a clock signal CK;
the substrate of the NMOS tube MN2 is grounded to VSS, the grid electrode is connected with a signal ml_ax, the source electrode is connected with the drain electrode of the MN1, and the drain electrode drives the signal sl_a;
the substrate of the NMOS tube MN3 is grounded, the grid electrode is connected with a signal ml_b, the source electrode is connected with the drain electrode of the MN1 and the source electrode of the NM2, and the drain electrode drives the signal sl_bx;
The substrate and the source electrode of the NMOS tube MN4 are grounded and the grid electrode is driven by a signal sl_bx, and the drain electrode drives a signal sl_a;
The substrate and the source electrode of the NMOS tube MN5 are grounded and the grid electrode is driven by a signal sl_a, and the drain electrode is driven by a signal sl_bx;
the PMOS tube MP6 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal sl_bx, and the drain electrode is driven by a signal sl_a;
the PMOS tube MP7 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal sl_a, and the drain electrode is driven by a signal sl_bx;
Where the signal sl_bx and the signal sl_a are complementary signal pairs in the slave flip-flop.
3. The true single phase clock master slave type all static D flip-flop according to claim 2, wherein said data output circuit comprises an inverter X3, the input of the inverter X3 being driven by a signal sl_bx and the output driving an output signal Q.
4. A true single phase clock master slave full static D flip-flop according to claim 1 or 2 or 3, wherein said data input circuit comprises an inverter X1 and an inverter X2 for receiving an input signal D and generating complementary or differential signal pairs dn and dnn;
The input end of the inverter X1 is connected with the data input signal D, and the output signal of the inverter X1 is dn; the input of the inverter X2 is connected with the signal dn, and the output signal of the inverter X2 is dnn.
5. A true single-phase clock master-slave type all-static D flip-flop according to claim 1, 2 or 3, wherein said data input circuit comprises inverters X2, X4, PMOS transistors MP11-MP14, NMOS transistors MN11-MN14;
the inverter X4 is used for generating a complementary signal sen of the enable signal SE;
Inverter X2 is used to generate a complementary signal dnn to signal dn;
The PMOS tube MP11 substrate and the source electrode are connected with a power supply VDD, and the grid electrode is controlled by an enable signal SE;
The substrate and the source electrode of the PMOS tube MP12 are connected with a power supply VDD, and the grid electrode is controlled by a scanning signal SI;
The PMOS tube MP13 substrate is connected with a power supply VDD, the source electrode is connected with the drain electrode of MP11, and the grid electrode is controlled by a data input signal D; and a drain driving signal dn;
The substrate of the PMOS tube MP14 is connected with a power supply VDD, the source electrode of the PMOS tube MP14 is connected with the drain electrode of the MP12, the gate is controlled by the signal sen, the drain driving signal dn;
The substrate and the source of the NMOS transistor MN11 are connected with a power supply VSS, and the grid is controlled by a complementary signal sen of an enable signal SE;
the substrate and the source of the NMOS tube MN12 are connected with a power supply VSS, and the grid is controlled by a scanning signal SI;
The substrate of NMOS transistor MN13 is connected with power source VSS, its source is connected with drain electrode of MN11, the grid is controlled by a data input signal D, and the drain electrode drives a signal dn;
The NMOS transistor MN14 has a substrate connected to a power source VSS, a source connected to the drain of MN12, a gate controlled by an enable signal SE, and a drain driving signal dn.
6. A true single phase clock master slave type all static D flip-flop according to claim 1,2 or 3, wherein said data input circuit comprises an inverter X1, the input of the inverter X1 being connected to the data input signal D, the output signal of the inverter X1 being dn; the data input signal D is provided as signal dnn.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1761153A (en) * | 2005-11-04 | 2006-04-19 | 清华大学 | High-speed master-slave type D trigger in low power consumption |
| CN1898865A (en) * | 2004-08-10 | 2007-01-17 | 日本电信电话株式会社 | Master-slave flip-flop, trigger flip-flop and counter |
| US20130173977A1 (en) * | 2011-12-31 | 2013-07-04 | Texas Instruments Incorporated | High density flip-flop with asynchronous reset |
| US20180115306A1 (en) * | 2016-10-20 | 2018-04-26 | Advanced Micro Devices, Inc. | Low power master-slave flip-flop |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1898865A (en) * | 2004-08-10 | 2007-01-17 | 日本电信电话株式会社 | Master-slave flip-flop, trigger flip-flop and counter |
| CN1761153A (en) * | 2005-11-04 | 2006-04-19 | 清华大学 | High-speed master-slave type D trigger in low power consumption |
| US20130173977A1 (en) * | 2011-12-31 | 2013-07-04 | Texas Instruments Incorporated | High density flip-flop with asynchronous reset |
| US20180115306A1 (en) * | 2016-10-20 | 2018-04-26 | Advanced Micro Devices, Inc. | Low power master-slave flip-flop |
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